add new system file

hc

2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/pci/controller/pcie-rockchip.c
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@@ -14,6 +14,7 @@
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 #include <linux/clk.h>
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 #include <linux/delay.h>
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 #include <linux/gpio/consumer.h>
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+#include <linux/iopoll.h>
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 #include <linux/module.h>
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 #include <linux/of_pci.h>
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 #include <linux/phy/phy.h>
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@@ -154,6 +155,12 @@
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 }
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 EXPORT_SYMBOL_GPL(rockchip_pcie_parse_dt);
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+#define rockchip_pcie_read_addr(addr) rockchip_pcie_read(rockchip, addr)
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+/* 100 ms max wait time for PHY PLLs to lock */
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+#define RK_PHY_PLL_LOCK_TIMEOUT_US 100000
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+/* Sleep should be less than 20ms */
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+#define RK_PHY_PLL_LOCK_SLEEP_US 1000
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+
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 int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
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 {
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 	struct device *dev = rockchip->dev;
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@@ -255,6 +262,16 @@
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 		}
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 	}
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+	err = readx_poll_timeout(rockchip_pcie_read_addr,
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+				 PCIE_CLIENT_SIDE_BAND_STATUS,
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+				 regs, !(regs & PCIE_CLIENT_PHY_ST),
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+				 RK_PHY_PLL_LOCK_SLEEP_US,
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+				 RK_PHY_PLL_LOCK_TIMEOUT_US);
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+	if (err) {
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+		dev_err(dev, "PHY PLLs could not lock, %d\n", err);
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+		goto err_power_off_phy;
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+	}
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+
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 	/*
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 	 * Please don't reorder the deassert sequence of the following
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 	 * four reset pins.