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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/pci/controller/dwc/pcie-histb.c
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@@ -122,31 +122,36 @@
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 	histb_pcie_dbi_w_mode(&pci->pp, false);
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 }
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-static int histb_pcie_rd_own_conf(struct pcie_port *pp, int where,
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-				  int size, u32 *val)
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+static int histb_pcie_rd_own_conf(struct pci_bus *bus, unsigned int devfn,
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+				  int where, int size, u32 *val)
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 {
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-	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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-	int ret;
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+	struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata);
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-	histb_pcie_dbi_r_mode(pp, true);
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-	ret = dw_pcie_read(pci->dbi_base + where, size, val);
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-	histb_pcie_dbi_r_mode(pp, false);
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+	if (PCI_SLOT(devfn)) {
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+		*val = ~0;
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+		return PCIBIOS_DEVICE_NOT_FOUND;
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+	}
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-	return ret;
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+	*val = dw_pcie_read_dbi(pci, where, size);
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+	return PCIBIOS_SUCCESSFUL;
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 }
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-static int histb_pcie_wr_own_conf(struct pcie_port *pp, int where,
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-				  int size, u32 val)
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+static int histb_pcie_wr_own_conf(struct pci_bus *bus, unsigned int devfn,
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+				  int where, int size, u32 val)
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 {
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-	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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-	int ret;
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+	struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata);
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-	histb_pcie_dbi_w_mode(pp, true);
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-	ret = dw_pcie_write(pci->dbi_base + where, size, val);
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-	histb_pcie_dbi_w_mode(pp, false);
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+	if (PCI_SLOT(devfn))
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+		return PCIBIOS_DEVICE_NOT_FOUND;
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-	return ret;
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+	dw_pcie_write_dbi(pci, where, size, val);
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+	return PCIBIOS_SUCCESSFUL;
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 }
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+
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+static struct pci_ops histb_pci_ops = {
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+	.read = histb_pcie_rd_own_conf,
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+	.write = histb_pcie_wr_own_conf,
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+};
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 static int histb_pcie_link_up(struct dw_pcie *pci)
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 {
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@@ -194,17 +199,15 @@
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 static int histb_pcie_host_init(struct pcie_port *pp)
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 {
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-	histb_pcie_establish_link(pp);
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+	pp->bridge->ops = &histb_pci_ops;
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-	if (IS_ENABLED(CONFIG_PCI_MSI))
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-		dw_pcie_msi_init(pp);
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+	histb_pcie_establish_link(pp);
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+	dw_pcie_msi_init(pp);
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 	return 0;
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 }
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-static struct dw_pcie_host_ops histb_pcie_host_ops = {
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-	.rd_own_conf = histb_pcie_rd_own_conf,
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-	.wr_own_conf = histb_pcie_wr_own_conf,
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+static const struct dw_pcie_host_ops histb_pcie_host_ops = {
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 	.host_init = histb_pcie_host_init,
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 };
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@@ -304,7 +307,6 @@
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 	struct histb_pcie *hipcie;
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 	struct dw_pcie *pci;
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 	struct pcie_port *pp;
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-	struct resource *res;
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 	struct device_node *np = pdev->dev.of_node;
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 	struct device *dev = &pdev->dev;
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 	enum of_gpio_flags of_flags;
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@@ -324,15 +326,13 @@
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 	pci->dev = dev;
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 	pci->ops = &dw_pcie_ops;
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-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "control");
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-	hipcie->ctrl = devm_ioremap_resource(dev, res);
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+	hipcie->ctrl = devm_platform_ioremap_resource_byname(pdev, "control");
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 	if (IS_ERR(hipcie->ctrl)) {
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 		dev_err(dev, "cannot get control reg base\n");
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 		return PTR_ERR(hipcie->ctrl);
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 	}
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-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc-dbi");
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-	pci->dbi_base = devm_ioremap_resource(dev, res);
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+	pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "rc-dbi");
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 	if (IS_ERR(pci->dbi_base)) {
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 		dev_err(dev, "cannot get rc-dbi base\n");
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 		return PTR_ERR(pci->dbi_base);
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@@ -402,10 +402,8 @@
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 	if (IS_ENABLED(CONFIG_PCI_MSI)) {
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 		pp->msi_irq = platform_get_irq_byname(pdev, "msi");
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-		if (pp->msi_irq < 0) {
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-			dev_err(dev, "Failed to get MSI IRQ\n");
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+		if (pp->msi_irq < 0)
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 			return pp->msi_irq;
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-		}
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 	}
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 	hipcie->phy = devm_phy_get(dev, "phy");