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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/pci/controller/dwc/pcie-dw-rockchip.c
....@@ -8,6 +8,7 @@
88  * Author: Simon Xue <xxm@rock-chips.com>
99  */
1010 
11
+#include <dt-bindings/phy/phy.h>
1112 #include <linux/clk.h>
1213 #include <linux/delay.h>
1314 #include <linux/fs.h>
....@@ -142,6 +143,7 @@
142143 #define PCIE_PL_ORDER_RULE_CTRL_OFF	0x8B4
143144 #define RK_PCIE_L2_TMOUT_US		5000
144145 #define RK_PCIE_HOTRESET_TMOUT_US	10000
146
+#define RK_PCIE_ENUM_HW_RETRYIES	2
145147 
146148 enum rk_pcie_ltssm_code {
147149 	S_L0 = 0x11,
....@@ -202,6 +204,8 @@
202204 };
203205 
204206 #define to_rk_pcie(x)	dev_get_drvdata((x)->dev)
207
+static int rk_pcie_disable_power(struct rk_pcie *rk_pcie);
208
+static int rk_pcie_enable_power(struct rk_pcie *rk_pcie);
205209 
206210 static int rk_pcie_read(void __iomem *addr, int size, u32 *val)
207211 {
....@@ -702,24 +706,6 @@
702706 	rk_pcie_writel_apb(rk_pcie, 0x0, 0xC000C);
703707 }
704708 
705
-static int rk_pcie_link_up(struct dw_pcie *pci)
706
-{
707
-	struct rk_pcie *rk_pcie = to_rk_pcie(pci);
708
-	u32 val;
709
-
710
-	if (rk_pcie->is_rk1808) {
711
-		val = rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_GENERAL_DEBUG);
712
-		if ((val & (PCIE_PHY_LINKUP | PCIE_DATA_LINKUP)) == 0x3)
713
-			return 1;
714
-	} else {
715
-		val = rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS);
716
-		if ((val & (RDLH_LINKUP | SMLH_LINKUP)) == 0x30000)
717
-			return 1;
718
-	}
719
-
720
-	return 0;
721
-}
722
-
723709 static void rk_pcie_enable_debug(struct rk_pcie *rk_pcie)
724710 {
725711 	if (!IS_ENABLED(CONFIG_DEBUG_FS))
....@@ -758,6 +744,8 @@
758744 	int retries, power;
759745 	struct rk_pcie *rk_pcie = to_rk_pcie(pci);
760746 	bool std_rc = rk_pcie->mode == RK_PCIE_RC_TYPE && !rk_pcie->dma_obj;
747
+	int hw_retries = 0;
748
+	u32 ltssm;
761749 
762750 	/*
763751 	 * For standard RC, even if the link has been setup by firmware,
....@@ -769,77 +757,92 @@
769757 		return 0;
770758 	}
771759 
772
-	/* Rest the device */
773
-	gpiod_set_value_cansleep(rk_pcie->rst_gpio, 0);
760
+	for (hw_retries = 0; hw_retries < RK_PCIE_ENUM_HW_RETRYIES; hw_retries++) {
761
+		/* Rest the device */
762
+		gpiod_set_value_cansleep(rk_pcie->rst_gpio, 0);
774763 
775
-	rk_pcie_disable_ltssm(rk_pcie);
776
-	rk_pcie_link_status_clear(rk_pcie);
777
-	rk_pcie_enable_debug(rk_pcie);
764
+		rk_pcie_disable_ltssm(rk_pcie);
765
+		rk_pcie_link_status_clear(rk_pcie);
766
+		rk_pcie_enable_debug(rk_pcie);
778767 
779
-	/* Enable client reset or link down interrupt */
780
-	rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_INTR_MASK, 0x40000);
768
+		/* Enable client reset or link down interrupt */
769
+		rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_INTR_MASK, 0x40000);
781770 
782
-	/* Enable LTSSM */
783
-	rk_pcie_enable_ltssm(rk_pcie);
771
+		/* Enable LTSSM */
772
+		rk_pcie_enable_ltssm(rk_pcie);
784773 
785
-	/*
786
-	 * In resume routine, function devices' resume function must be late after
787
-	 * controllers'. Some devices, such as Wi-Fi, need special IO setting before
788
-	 * finishing training. So there must be timeout here. These kinds of devices
789
-	 * need rescan devices by its driver when used. So no need to waste time waiting
790
-	 * for training pass.
791
-	 */
792
-	if (rk_pcie->in_suspend && rk_pcie->skip_scan_in_resume) {
793
-		rfkill_get_wifi_power_state(&power);
794
-		if (!power) {
795
-			gpiod_set_value_cansleep(rk_pcie->rst_gpio, 1);
796
-			return 0;
797
-		}
798
-	}
799
-
800
-	/*
801
-	 * PCIe requires the refclk to be stable for 100µs prior to releasing
802
-	 * PERST and T_PVPERL (Power stable to PERST# inactive) should be a
803
-	 * minimum of 100ms.  See table 2-4 in section 2.6.2 AC, the PCI Express
804
-	 * Card Electromechanical Specification 3.0. So 100ms in total is the min
805
-	 * requuirement here. We add a 200ms by default for sake of hoping everthings
806
-	 * work fine. If it doesn't, please add more in DT node by add rockchip,perst-inactive-ms.
807
-	 */
808
-	msleep(rk_pcie->perst_inactive_ms);
809
-	gpiod_set_value_cansleep(rk_pcie->rst_gpio, 1);
810
-
811
-	/*
812
-	 * Add this 1ms delay because we observe link is always up stably after it and
813
-	 * could help us save 20ms for scanning devices.
814
-	 */
815
-	usleep_range(1000, 1100);
816
-
817
-	for (retries = 0; retries < 100; retries++) {
818
-		if (dw_pcie_link_up(pci)) {
819
-			/*
820
-			 * We may be here in case of L0 in Gen1. But if EP is capable
821
-			 * of Gen2 or Gen3, Gen switch may happen just in this time, but
822
-			 * we keep on accessing devices in unstable link status. Given
823
-			 * that LTSSM max timeout is 24ms per period, we can wait a bit
824
-			 * more for Gen switch.
825
-			 */
826
-			msleep(50);
827
-			/* In case link drop after linkup, double check it */
828
-			if (dw_pcie_link_up(pci)) {
829
-				dev_info(pci->dev, "PCIe Link up, LTSSM is 0x%x\n",
830
-					 rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS));
831
-				rk_pcie_debug_dump(rk_pcie);
774
+		/*
775
+		 * In resume routine, function devices' resume function must be late after
776
+		 * controllers'. Some devices, such as Wi-Fi, need special IO setting before
777
+		 * finishing training. So there must be timeout here. These kinds of devices
778
+		 * need rescan devices by its driver when used. So no need to waste time waiting
779
+		 * for training pass.
780
+		 */
781
+		if (rk_pcie->in_suspend && rk_pcie->skip_scan_in_resume) {
782
+			rfkill_get_wifi_power_state(&power);
783
+			if (!power) {
784
+				gpiod_set_value_cansleep(rk_pcie->rst_gpio, 1);
832785 				return 0;
833786 			}
834787 		}
835788 
836
-		dev_info_ratelimited(pci->dev, "PCIe Linking... LTSSM is 0x%x\n",
837
-				     rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS));
838
-		rk_pcie_debug_dump(rk_pcie);
839
-		msleep(20);
840
-	}
789
+		/*
790
+		 * PCIe requires the refclk to be stable for 100µs prior to releasing
791
+		 * PERST and T_PVPERL (Power stable to PERST# inactive) should be a
792
+		 * minimum of 100ms.  See table 2-4 in section 2.6.2 AC, the PCI Express
793
+		 * Card Electromechanical Specification 3.0. So 100ms in total is the min
794
+		 * requuirement here. We add a 200ms by default for sake of hoping everthings
795
+		 * work fine. If it doesn't, please add more in DT node by add rockchip,perst-inactive-ms.
796
+		 */
797
+		msleep(rk_pcie->perst_inactive_ms);
798
+		gpiod_set_value_cansleep(rk_pcie->rst_gpio, 1);
841799 
842
-	dev_err(pci->dev, "PCIe Link Fail\n");
800
+		/*
801
+		 * Add this 1ms delay because we observe link is always up stably after it and
802
+		 * could help us save 20ms for scanning devices.
803
+		 */
804
+		usleep_range(1000, 1100);
805
+
806
+		for (retries = 0; retries < 100; retries++) {
807
+			if (dw_pcie_link_up(pci)) {
808
+				/*
809
+				 * We may be here in case of L0 in Gen1. But if EP is capable
810
+				 * of Gen2 or Gen3, Gen switch may happen just in this time, but
811
+				 * we keep on accessing devices in unstable link status. Given
812
+				 * that LTSSM max timeout is 24ms per period, we can wait a bit
813
+				 * more for Gen switch.
814
+				 */
815
+				msleep(50);
816
+				/* In case link drop after linkup, double check it */
817
+				if (dw_pcie_link_up(pci)) {
818
+					dev_info(pci->dev, "PCIe Link up, LTSSM is 0x%x\n",
819
+						rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS));
820
+					rk_pcie_debug_dump(rk_pcie);
821
+					return 0;
822
+				}
823
+			}
824
+
825
+			dev_info_ratelimited(pci->dev, "PCIe Linking... LTSSM is 0x%x\n",
826
+					rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS));
827
+			rk_pcie_debug_dump(rk_pcie);
828
+			msleep(20);
829
+		}
830
+
831
+		/*
832
+		 * In response to the situation where PCIe peripherals cannot be
833
+		 * enumerated due tosignal abnormalities, reset PERST# and reset
834
+		 * the peripheral power supply, then restart the enumeration.
835
+		 */
836
+		ltssm = rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS);
837
+		dev_err(pci->dev, "PCIe Link Fail, LTSSM is 0x%x, hw_retries=%d\n", ltssm, hw_retries);
838
+		if (ltssm >= 3 && !rk_pcie->is_signal_test) {
839
+			rk_pcie_disable_power(rk_pcie);
840
+			msleep(1000);
841
+			rk_pcie_enable_power(rk_pcie);
842
+		} else {
843
+			break;
844
+		}
845
+	}
843846 
844847 	return rk_pcie->is_signal_test == true ? 0 : -EINVAL;
845848 }
....@@ -1129,8 +1132,8 @@
11291132 	dw_pcie_setup_rc(pp);
11301133 
11311134 	/* Disable BAR0 BAR1 */
1132
-	dw_pcie_writel_dbi(pci, PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + BAR_0 * 4, 0);
1133
-	dw_pcie_writel_dbi(pci, PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + BAR_1 * 4, 0);
1135
+	dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_0, 0x0);
1136
+	dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_1, 0x0);
11341137 
11351138 	ret = rk_pcie_establish_link(pci);
11361139 
....@@ -1203,7 +1206,6 @@
12031206 		return ret;
12041207 	}
12051208 
1206
-	rk_pcie->pci->dbi_base2 = rk_pcie->pci->dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET;
12071209 	rk_pcie->pci->atu_base = rk_pcie->pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;
12081210 	rk_pcie->pci->iatu_unroll_enabled = rk_pcie_iatu_unroll_enabled(rk_pcie->pci);
12091211 
....@@ -1263,6 +1265,7 @@
12631265 		return PTR_ERR(rk_pcie->dbi_base);
12641266 
12651267 	rk_pcie->pci->dbi_base = rk_pcie->dbi_base;
1268
+	rk_pcie->pci->dbi_base2 = rk_pcie->pci->dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET;
12661269 
12671270 	apb_base = platform_get_resource_byname(pdev, IORESOURCE_MEM,
12681271 						"pcie-apb");
....@@ -1601,7 +1604,6 @@
16011604 
16021605 static const struct dw_pcie_ops dw_pcie_ops = {
16031606 	.start_link = rk_pcie_establish_link,
1604
-	.link_up = rk_pcie_link_up,
16051607 };
16061608 
16071609 static int rk1808_pcie_fixup(struct rk_pcie *rk_pcie, struct device_node *np)
....@@ -1988,6 +1990,7 @@
19881990 
19891991 	if (!IS_ERR_OR_NULL(rk_pcie->prsnt_gpio)) {
19901992 		if (!gpiod_get_value(rk_pcie->prsnt_gpio)) {
1993
+			dev_info(dev, "device isn't present\n");
19911994 			ret = -ENODEV;
19921995 			goto release_driver;
19931996 		}
....@@ -2354,6 +2357,12 @@
23542357 no_l2:
23552358 	rk_pcie_disable_ltssm(rk_pcie);
23562359 
2360
+	ret = phy_validate(rk_pcie->phy, PHY_TYPE_PCIE, 0, NULL);
2361
+	if (ret && ret != -EOPNOTSUPP) {
2362
+		dev_err(dev, "PHY is reused by other controller, check the dts!\n");
2363
+		return ret;
2364
+	}
2365
+
23572366 	/* make sure assert phy success */
23582367 	usleep_range(200, 300);
23592368