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hc

2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/pci/controller/cadence/pcie-cadence-host.c
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@@ -12,6 +12,8 @@
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 #include "pcie-cadence.h"
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+#define LINK_RETRAIN_TIMEOUT HZ
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+
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 static u64 bar_max_size[] = {
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 	[RP_BAR0] = _ULL(128 * SZ_2G),
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 	[RP_BAR1] = SZ_2G,
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@@ -77,6 +79,27 @@
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 	.write		= pci_generic_config_write,
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 };
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+static int cdns_pcie_host_training_complete(struct cdns_pcie *pcie)
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+{
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+	u32 pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET;
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+	unsigned long end_jiffies;
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+	u16 lnk_stat;
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+
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+	/* Wait for link training to complete. Exit after timeout. */
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+	end_jiffies = jiffies + LINK_RETRAIN_TIMEOUT;
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+	do {
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+		lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA);
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+		if (!(lnk_stat & PCI_EXP_LNKSTA_LT))
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+			break;
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+		usleep_range(0, 1000);
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+	} while (time_before(jiffies, end_jiffies));
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+
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+	if (!(lnk_stat & PCI_EXP_LNKSTA_LT))
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+		return 0;
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+
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+	return -ETIMEDOUT;
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+}
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+
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 static int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie)
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 {
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 	struct device *dev = pcie->dev;
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@@ -118,6 +141,10 @@
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 		cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL,
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 				    lnk_ctl);
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+		ret = cdns_pcie_host_training_complete(pcie);
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+		if (ret)
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+			return ret;
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+
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 		ret = cdns_pcie_host_wait_for_link(pcie);
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 	}
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 	return ret;