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33 | 33 | #endif |
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34 | 34 | |
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35 | 35 | #define PCI_OP_READ(size, type, len) \ |
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36 | | -int pci_bus_read_config_##size \ |
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| 36 | +int noinline pci_bus_read_config_##size \ |
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37 | 37 | (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \ |
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38 | 38 | { \ |
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39 | 39 | int res; \ |
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48 | 48 | } |
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49 | 49 | |
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50 | 50 | #define PCI_OP_WRITE(size, type, len) \ |
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51 | | -int pci_bus_write_config_##size \ |
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| 51 | +int noinline pci_bus_write_config_##size \ |
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52 | 52 | (struct pci_bus *bus, unsigned int devfn, int pos, type value) \ |
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53 | 53 | { \ |
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54 | 54 | int res; \ |
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332 | 332 | return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS; |
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333 | 333 | } |
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334 | 334 | |
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335 | | -static bool pcie_downstream_port(const struct pci_dev *dev) |
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336 | | -{ |
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337 | | - int type = pci_pcie_type(dev); |
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338 | | - |
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339 | | - return type == PCI_EXP_TYPE_ROOT_PORT || |
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340 | | - type == PCI_EXP_TYPE_DOWNSTREAM || |
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341 | | - type == PCI_EXP_TYPE_PCIE_BRIDGE; |
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342 | | -} |
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343 | | - |
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344 | 335 | bool pcie_cap_has_lnkctl(const struct pci_dev *dev) |
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345 | 336 | { |
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346 | 337 | int type = pci_pcie_type(dev); |
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360 | 351 | pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT; |
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361 | 352 | } |
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362 | 353 | |
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363 | | -static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev) |
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| 354 | +bool pcie_cap_has_rtctl(const struct pci_dev *dev) |
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364 | 355 | { |
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365 | 356 | int type = pci_pcie_type(dev); |
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366 | 357 | |
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414 | 405 | |
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415 | 406 | *val = 0; |
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416 | 407 | if (pos & 1) |
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417 | | - return -EINVAL; |
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| 408 | + return PCIBIOS_BAD_REGISTER_NUMBER; |
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418 | 409 | |
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419 | 410 | if (pcie_capability_reg_implemented(dev, pos)) { |
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420 | 411 | ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val); |
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449 | 440 | |
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450 | 441 | *val = 0; |
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451 | 442 | if (pos & 3) |
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452 | | - return -EINVAL; |
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| 443 | + return PCIBIOS_BAD_REGISTER_NUMBER; |
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453 | 444 | |
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454 | 445 | if (pcie_capability_reg_implemented(dev, pos)) { |
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455 | 446 | ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val); |
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474 | 465 | int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) |
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475 | 466 | { |
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476 | 467 | if (pos & 1) |
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477 | | - return -EINVAL; |
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| 468 | + return PCIBIOS_BAD_REGISTER_NUMBER; |
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478 | 469 | |
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479 | 470 | if (!pcie_capability_reg_implemented(dev, pos)) |
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480 | 471 | return 0; |
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486 | 477 | int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val) |
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487 | 478 | { |
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488 | 479 | if (pos & 3) |
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489 | | - return -EINVAL; |
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| 480 | + return PCIBIOS_BAD_REGISTER_NUMBER; |
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490 | 481 | |
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491 | 482 | if (!pcie_capability_reg_implemented(dev, pos)) |
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492 | 483 | return 0; |
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