add new system file

hc

2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/nvmem/rockchip-otp.c
..
..
@@ -77,6 +77,18 @@
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 #define OTPC_TIMEOUT_PROG		100000
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 #define RK3568_NBYTES			2
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+#define RK3588_OTPC_AUTO_CTRL		0x04
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+#define RK3588_OTPC_AUTO_EN		0x08
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+#define RK3588_OTPC_INT_ST		0x84
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+#define RK3588_OTPC_DOUT0		0x20
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+#define RK3588_NO_SECURE_OFFSET		0x300
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+#define RK3588_NBYTES			4
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+#define RK3588_BURST_NUM		1
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+#define RK3588_BURST_SHIFT		8
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+#define RK3588_ADDR_SHIFT		16
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+#define RK3588_AUTO_EN			BIT(0)
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+#define RK3588_RD_DONE			BIT(1)
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+
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 #define RV1126_OTP_NVM_CEB		0x00
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 #define RV1126_OTP_NVM_RSTB		0x04
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 #define RV1126_OTP_NVM_ST		0x18
..
..
@@ -144,7 +156,7 @@
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 struct rockchip_otp {
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 	struct device *dev;
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 	void __iomem *base;
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-	struct clk_bulk_data *clks;
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+	struct clk_bulk_data	*clks;
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 	int num_clks;
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 	struct reset_control *rst;
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 	struct nvmem_config *config;
..
..
@@ -302,7 +314,7 @@
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 			dev_err(otp->dev, "timeout during wait dp2stb\n");
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 			return ret;
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 		}
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-		/* fall through */
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+		fallthrough;
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 	case OTPC_STANDBY:
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 		writel(OTPC_ACTIVE, otp->base + OTPC_MODE_CTRL);
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 		ret = px30s_otp_wait_status(otp, OTPC_STB2ACT_IRQ_ST);
..
..
@@ -333,7 +345,7 @@
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 			dev_err(otp->dev, "timeout during wait act2stb\n");
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 			return ret;
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 		}
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-		/* fall through */
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+		fallthrough;
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 	case OTPC_STANDBY:
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 		writel(OTPC_DEEP_STANDBY, otp->base + OTPC_MODE_CTRL);
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 		ret = px30s_otp_wait_status(otp, OTPC_STB2DP_IRQ_ST);
..
..
@@ -481,6 +493,80 @@
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 read_end:
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 	writel(0x0 | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
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 disable_clks:
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+	clk_bulk_disable_unprepare(otp->num_clks, otp->clks);
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+out:
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+	kfree(buf);
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+
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+	return ret;
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+}
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+
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+static int rk3588_otp_wait_status(struct rockchip_otp *otp, u32 flag)
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+{
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+	u32 status = 0;
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+	int ret;
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+
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+	ret = readl_poll_timeout_atomic(otp->base + RK3588_OTPC_INT_ST, status,
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+					(status & flag), 1, OTPC_TIMEOUT);
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+	if (ret)
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+		return ret;
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+
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+	/* clean int status */
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+	writel(flag, otp->base + RK3588_OTPC_INT_ST);
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+
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+	return 0;
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+}
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+
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+static int rk3588_otp_read(void *context, unsigned int offset, void *val,
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+			   size_t bytes)
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+{
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+	struct rockchip_otp *otp = context;
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+	unsigned int addr_start, addr_end, addr_offset, addr_len;
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+	int ret = 0, i = 0;
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+	u32 out_value;
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+	u8 *buf;
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+
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+	if (offset >= otp->data->size)
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+		return -ENOMEM;
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+	if (offset + bytes > otp->data->size)
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+		bytes = otp->data->size - offset;
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+
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+	addr_start = rounddown(offset, RK3588_NBYTES) / RK3588_NBYTES;
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+	addr_end = roundup(offset + bytes, RK3588_NBYTES) / RK3588_NBYTES;
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+	addr_offset = offset % RK3588_NBYTES;
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+	addr_len = addr_end - addr_start;
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+	addr_start += RK3588_NO_SECURE_OFFSET;
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+
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+	buf = kzalloc(array3_size(addr_len, RK3588_NBYTES, sizeof(*buf)),
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+		      GFP_KERNEL);
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+	if (!buf)
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+		return -ENOMEM;
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+
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+	ret = clk_bulk_prepare_enable(otp->num_clks, otp->clks);
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+	if (ret < 0) {
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+		dev_err(otp->dev, "failed to prepare/enable clks\n");
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+		goto out;
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+	}
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+
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+	while (addr_len--) {
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+		writel((addr_start << RK3588_ADDR_SHIFT) |
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+		       (RK3588_BURST_NUM << RK3588_BURST_SHIFT),
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+		       otp->base + RK3588_OTPC_AUTO_CTRL);
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+		writel(RK3588_AUTO_EN, otp->base + RK3588_OTPC_AUTO_EN);
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+		ret = rk3588_otp_wait_status(otp, RK3588_RD_DONE);
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+		if (ret < 0) {
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+			dev_err(otp->dev, "timeout during read setup\n");
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+			goto read_end;
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+		}
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+
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+		out_value = readl(otp->base + RK3588_OTPC_DOUT0);
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+		memcpy(&buf[i], &out_value, RK3588_NBYTES);
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+		i += RK3588_NBYTES;
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+		addr_start++;
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+	}
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+
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+	memcpy(val, buf + addr_offset, bytes);
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+
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+read_end:
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 	clk_bulk_disable_unprepare(otp->num_clks, otp->clks);
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 out:
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 	kfree(buf);
..
..
@@ -686,6 +772,17 @@
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 	.reg_read = rk3568_otp_read,
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 };
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+static const char * const rk3562_otp_clocks[] = {
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+	"usr", "sbpi", "apb", "arb", "phy",
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+};
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+
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+static const struct rockchip_data rk3562_data = {
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+	.size = 0x80,
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+	.clocks = rk3562_otp_clocks,
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+	.num_clks = ARRAY_SIZE(rk3562_otp_clocks),
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+	.reg_read = rk3568_otp_read,
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+};
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+
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 static const char * const rk3568_otp_clocks[] = {
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 	"usr", "sbpi", "apb", "phy",
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 };
..
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@@ -694,6 +791,28 @@
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 	.size = 0x80,
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 	.clocks = rk3568_otp_clocks,
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 	.num_clks = ARRAY_SIZE(rk3568_otp_clocks),
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+	.reg_read = rk3568_otp_read,
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+};
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+
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+static const char * const rk3588_otp_clocks[] = {
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+	"otpc", "apb", "arb", "phy",
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+};
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+
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+static const struct rockchip_data rk3588_data = {
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+	.size = 0x400,
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+	.clocks = rk3588_otp_clocks,
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+	.num_clks = ARRAY_SIZE(rk3588_otp_clocks),
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+	.reg_read = rk3588_otp_read,
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+};
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+
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+static const char * const rv1106_otp_clocks[] = {
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+	"usr", "sbpi", "apb", "phy", "arb", "pmc",
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+};
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+
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+static const struct rockchip_data rv1106_data = {
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+	.size = 0x80,
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+	.clocks = rv1106_otp_clocks,
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+	.num_clks = ARRAY_SIZE(rv1106_otp_clocks),
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 	.reg_read = rk3568_otp_read,
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 };
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..
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@@ -726,6 +845,10 @@
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 		.compatible = "rockchip,rk3308-otp",
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 		.data = (void *)&px30_data,
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 	},
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+	{
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+		.compatible = "rockchip,rk3308bs-otp",
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+		.data = (void *)&px30s_data,
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+	},
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 #endif
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 #ifdef CONFIG_CPU_RK3528
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 	{
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@@ -733,10 +856,28 @@
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 		.data = (void *)&rk3528_data,
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 	},
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 #endif
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+#ifdef CONFIG_CPU_RK3562
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+	{
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+		.compatible = "rockchip,rk3562-otp",
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+		.data = (void *)&rk3562_data,
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+	},
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+#endif
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 #ifdef CONFIG_CPU_RK3568
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 	{
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 		.compatible = "rockchip,rk3568-otp",
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 		.data = (void *)&rk3568_data,
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+	},
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+#endif
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+#ifdef CONFIG_CPU_RK3588
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+	{
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+		.compatible = "rockchip,rk3588-otp",
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+		.data = (void *)&rk3588_data,
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+	},
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+#endif
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+#ifdef CONFIG_CPU_RV1106
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+	{
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+		.compatible = "rockchip,rv1106-otp",
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+		.data = (void *)&rv1106_data,
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 	},
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 #endif
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 #ifdef CONFIG_CPU_RV1126
..
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@@ -749,7 +890,7 @@
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 };
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 MODULE_DEVICE_TABLE(of, rockchip_otp_match);
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-static int __init rockchip_otp_probe(struct platform_device *pdev)
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+static int rockchip_otp_probe(struct platform_device *pdev)
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 {
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 	struct device *dev = &pdev->dev;
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 	struct rockchip_otp *otp;
..
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@@ -762,7 +903,7 @@
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 		dev_err(dev, "failed to get match data\n");
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 		return -EINVAL;
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 	}
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-	if (soc_is_px30s())
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+	if (soc_is_px30s() || soc_is_rk3308bs())
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 		data = &px30s_data;
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908
 
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 	otp = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_otp),
..
..
@@ -811,19 +952,33 @@
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 }
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 static struct platform_driver rockchip_otp_driver = {
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+	.probe = rockchip_otp_probe,
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 	.driver = {
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 		.name = "rockchip-otp",
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 		.of_match_table = rockchip_otp_match,
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 	},
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 };
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-static int __init rockchip_otp_module_init(void)
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+static int __init rockchip_otp_init(void)
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 {
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-	return platform_driver_probe(&rockchip_otp_driver,
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-				     rockchip_otp_probe);
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+	int ret;
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+
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+	ret = platform_driver_register(&rockchip_otp_driver);
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+	if (ret) {
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+		pr_err("failed to register otp driver\n");
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+		return ret;
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+	}
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+
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+	return 0;
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 }
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974
 
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-subsys_initcall(rockchip_otp_module_init);
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+static void __exit rockchip_otp_exit(void)
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+{
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+	return platform_driver_unregister(&rockchip_otp_driver);
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+}
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+
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+subsys_initcall(rockchip_otp_init);
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+module_exit(rockchip_otp_exit);
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 MODULE_DESCRIPTION("Rockchip OTP driver");
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 MODULE_LICENSE("GPL v2");