forked from ~ljy/RK356X_SDK_RELEASE

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hc
2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/net/usb/lan78xx.c
....@@ -824,20 +824,19 @@
824824 				u32 length, u8 *data)
825825 {
826826 	int i;
827
-	int ret;
828827 	u32 buf;
829828 	unsigned long timeout;
830829 
831
-	ret = lan78xx_read_reg(dev, OTP_PWR_DN, &buf);
830
+	lan78xx_read_reg(dev, OTP_PWR_DN, &buf);
832831 
833832 	if (buf & OTP_PWR_DN_PWRDN_N_) {
834833 		/* clear it and wait to be cleared */
835
-		ret = lan78xx_write_reg(dev, OTP_PWR_DN, 0);
834
+		lan78xx_write_reg(dev, OTP_PWR_DN, 0);
836835 
837836 		timeout = jiffies + HZ;
838837 		do {
839838 			usleep_range(1, 10);
840
-			ret = lan78xx_read_reg(dev, OTP_PWR_DN, &buf);
839
+			lan78xx_read_reg(dev, OTP_PWR_DN, &buf);
841840 			if (time_after(jiffies, timeout)) {
842841 				netdev_warn(dev->net,
843842 					    "timeout on OTP_PWR_DN");
....@@ -847,18 +846,18 @@
847846 	}
848847 
849848 	for (i = 0; i < length; i++) {
850
-		ret = lan78xx_write_reg(dev, OTP_ADDR1,
849
+		lan78xx_write_reg(dev, OTP_ADDR1,
851850 					((offset + i) >> 8) & OTP_ADDR1_15_11);
852
-		ret = lan78xx_write_reg(dev, OTP_ADDR2,
851
+		lan78xx_write_reg(dev, OTP_ADDR2,
853852 					((offset + i) & OTP_ADDR2_10_3));
854853 
855
-		ret = lan78xx_write_reg(dev, OTP_FUNC_CMD, OTP_FUNC_CMD_READ_);
856
-		ret = lan78xx_write_reg(dev, OTP_CMD_GO, OTP_CMD_GO_GO_);
854
+		lan78xx_write_reg(dev, OTP_FUNC_CMD, OTP_FUNC_CMD_READ_);
855
+		lan78xx_write_reg(dev, OTP_CMD_GO, OTP_CMD_GO_GO_);
857856 
858857 		timeout = jiffies + HZ;
859858 		do {
860859 			udelay(1);
861
-			ret = lan78xx_read_reg(dev, OTP_STATUS, &buf);
860
+			lan78xx_read_reg(dev, OTP_STATUS, &buf);
862861 			if (time_after(jiffies, timeout)) {
863862 				netdev_warn(dev->net,
864863 					    "timeout on OTP_STATUS");
....@@ -866,7 +865,7 @@
866865 			}
867866 		} while (buf & OTP_STATUS_BUSY_);
868867 
869
-		ret = lan78xx_read_reg(dev, OTP_RD_DATA, &buf);
868
+		lan78xx_read_reg(dev, OTP_RD_DATA, &buf);
870869 
871870 		data[i] = (u8)(buf & 0xFF);
872871 	}
....@@ -878,20 +877,19 @@
878877 				 u32 length, u8 *data)
879878 {
880879 	int i;
881
-	int ret;
882880 	u32 buf;
883881 	unsigned long timeout;
884882 
885
-	ret = lan78xx_read_reg(dev, OTP_PWR_DN, &buf);
883
+	lan78xx_read_reg(dev, OTP_PWR_DN, &buf);
886884 
887885 	if (buf & OTP_PWR_DN_PWRDN_N_) {
888886 		/* clear it and wait to be cleared */
889
-		ret = lan78xx_write_reg(dev, OTP_PWR_DN, 0);
887
+		lan78xx_write_reg(dev, OTP_PWR_DN, 0);
890888 
891889 		timeout = jiffies + HZ;
892890 		do {
893891 			udelay(1);
894
-			ret = lan78xx_read_reg(dev, OTP_PWR_DN, &buf);
892
+			lan78xx_read_reg(dev, OTP_PWR_DN, &buf);
895893 			if (time_after(jiffies, timeout)) {
896894 				netdev_warn(dev->net,
897895 					    "timeout on OTP_PWR_DN completion");
....@@ -901,21 +899,21 @@
901899 	}
902900 
903901 	/* set to BYTE program mode */
904
-	ret = lan78xx_write_reg(dev, OTP_PRGM_MODE, OTP_PRGM_MODE_BYTE_);
902
+	lan78xx_write_reg(dev, OTP_PRGM_MODE, OTP_PRGM_MODE_BYTE_);
905903 
906904 	for (i = 0; i < length; i++) {
907
-		ret = lan78xx_write_reg(dev, OTP_ADDR1,
905
+		lan78xx_write_reg(dev, OTP_ADDR1,
908906 					((offset + i) >> 8) & OTP_ADDR1_15_11);
909
-		ret = lan78xx_write_reg(dev, OTP_ADDR2,
907
+		lan78xx_write_reg(dev, OTP_ADDR2,
910908 					((offset + i) & OTP_ADDR2_10_3));
911
-		ret = lan78xx_write_reg(dev, OTP_PRGM_DATA, data[i]);
912
-		ret = lan78xx_write_reg(dev, OTP_TST_CMD, OTP_TST_CMD_PRGVRFY_);
913
-		ret = lan78xx_write_reg(dev, OTP_CMD_GO, OTP_CMD_GO_GO_);
909
+		lan78xx_write_reg(dev, OTP_PRGM_DATA, data[i]);
910
+		lan78xx_write_reg(dev, OTP_TST_CMD, OTP_TST_CMD_PRGVRFY_);
911
+		lan78xx_write_reg(dev, OTP_CMD_GO, OTP_CMD_GO_GO_);
914912 
915913 		timeout = jiffies + HZ;
916914 		do {
917915 			udelay(1);
918
-			ret = lan78xx_read_reg(dev, OTP_STATUS, &buf);
916
+			lan78xx_read_reg(dev, OTP_STATUS, &buf);
919917 			if (time_after(jiffies, timeout)) {
920918 				netdev_warn(dev->net,
921919 					    "Timeout on OTP_STATUS completion");
....@@ -1040,7 +1038,6 @@
10401038 			container_of(param, struct lan78xx_priv, set_multicast);
10411039 	struct lan78xx_net *dev = pdata->dev;
10421040 	int i;
1043
-	int ret;
10441041 
10451042 	netif_dbg(dev, drv, dev->net, "deferred multicast write 0x%08x\n",
10461043 		  pdata->rfe_ctl);
....@@ -1049,14 +1046,14 @@
10491046 			       DP_SEL_VHF_HASH_LEN, pdata->mchash_table);
10501047 
10511048 	for (i = 1; i < NUM_OF_MAF; i++) {
1052
-		ret = lan78xx_write_reg(dev, MAF_HI(i), 0);
1053
-		ret = lan78xx_write_reg(dev, MAF_LO(i),
1049
+		lan78xx_write_reg(dev, MAF_HI(i), 0);
1050
+		lan78xx_write_reg(dev, MAF_LO(i),
10541051 					pdata->pfilter_table[i][1]);
1055
-		ret = lan78xx_write_reg(dev, MAF_HI(i),
1052
+		lan78xx_write_reg(dev, MAF_HI(i),
10561053 					pdata->pfilter_table[i][0]);
10571054 	}
10581055 
1059
-	ret = lan78xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
1056
+	lan78xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
10601057 }
10611058 
10621059 static void lan78xx_set_multicast(struct net_device *netdev)
....@@ -1126,7 +1123,6 @@
11261123 				      u16 lcladv, u16 rmtadv)
11271124 {
11281125 	u32 flow = 0, fct_flow = 0;
1129
-	int ret;
11301126 	u8 cap;
11311127 
11321128 	if (dev->fc_autoneg)
....@@ -1149,10 +1145,10 @@
11491145 		  (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
11501146 		  (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
11511147 
1152
-	ret = lan78xx_write_reg(dev, FCT_FLOW, fct_flow);
1148
+	lan78xx_write_reg(dev, FCT_FLOW, fct_flow);
11531149 
11541150 	/* threshold value should be set before enabling flow */
1155
-	ret = lan78xx_write_reg(dev, FLOW, flow);
1151
+	lan78xx_write_reg(dev, FLOW, flow);
11561152 
11571153 	return 0;
11581154 }
....@@ -1673,11 +1669,10 @@
16731669 static void lan78xx_init_mac_address(struct lan78xx_net *dev)
16741670 {
16751671 	u32 addr_lo, addr_hi;
1676
-	int ret;
16771672 	u8 addr[6];
16781673 
1679
-	ret = lan78xx_read_reg(dev, RX_ADDRL, &addr_lo);
1680
-	ret = lan78xx_read_reg(dev, RX_ADDRH, &addr_hi);
1674
+	lan78xx_read_reg(dev, RX_ADDRL, &addr_lo);
1675
+	lan78xx_read_reg(dev, RX_ADDRH, &addr_hi);
16811676 
16821677 	addr[0] = addr_lo & 0xFF;
16831678 	addr[1] = (addr_lo >> 8) & 0xFF;
....@@ -1710,12 +1705,12 @@
17101705 			  (addr[2] << 16) | (addr[3] << 24);
17111706 		addr_hi = addr[4] | (addr[5] << 8);
17121707 
1713
-		ret = lan78xx_write_reg(dev, RX_ADDRL, addr_lo);
1714
-		ret = lan78xx_write_reg(dev, RX_ADDRH, addr_hi);
1708
+		lan78xx_write_reg(dev, RX_ADDRL, addr_lo);
1709
+		lan78xx_write_reg(dev, RX_ADDRH, addr_hi);
17151710 	}
17161711 
1717
-	ret = lan78xx_write_reg(dev, MAF_LO(0), addr_lo);
1718
-	ret = lan78xx_write_reg(dev, MAF_HI(0), addr_hi | MAF_HI_VALID_);
1712
+	lan78xx_write_reg(dev, MAF_LO(0), addr_lo);
1713
+	lan78xx_write_reg(dev, MAF_HI(0), addr_hi | MAF_HI_VALID_);
17191714 
17201715 	ether_addr_copy(dev->net->dev_addr, addr);
17211716 }
....@@ -1848,33 +1843,8 @@
18481843 static void lan78xx_link_status_change(struct net_device *net)
18491844 {
18501845 	struct phy_device *phydev = net->phydev;
1851
-	int ret, temp;
18521846 
1853
-	/* At forced 100 F/H mode, chip may fail to set mode correctly
1854
-	 * when cable is switched between long(~50+m) and short one.
1855
-	 * As workaround, set to 10 before setting to 100
1856
-	 * at forced 100 F/H mode.
1857
-	 */
1858
-	if (!phydev->autoneg && (phydev->speed == 100)) {
1859
-		/* disable phy interrupt */
1860
-		temp = phy_read(phydev, LAN88XX_INT_MASK);
1861
-		temp &= ~LAN88XX_INT_MASK_MDINTPIN_EN_;
1862
-		ret = phy_write(phydev, LAN88XX_INT_MASK, temp);
1863
-
1864
-		temp = phy_read(phydev, MII_BMCR);
1865
-		temp &= ~(BMCR_SPEED100 | BMCR_SPEED1000);
1866
-		phy_write(phydev, MII_BMCR, temp); /* set to 10 first */
1867
-		temp |= BMCR_SPEED100;
1868
-		phy_write(phydev, MII_BMCR, temp); /* set to 100 later */
1869
-
1870
-		/* clear pending interrupt generated while workaround */
1871
-		temp = phy_read(phydev, LAN88XX_INT_STS);
1872
-
1873
-		/* enable phy interrupt back */
1874
-		temp = phy_read(phydev, LAN88XX_INT_MASK);
1875
-		temp |= LAN88XX_INT_MASK_MDINTPIN_EN_;
1876
-		ret = phy_write(phydev, LAN88XX_INT_MASK, temp);
1877
-	}
1847
+	phy_print_status(phydev);
18781848 }
18791849 
18801850 static int irq_map(struct irq_domain *d, unsigned int irq,
....@@ -1927,14 +1897,13 @@
19271897 	struct lan78xx_net *dev =
19281898 			container_of(data, struct lan78xx_net, domain_data);
19291899 	u32 buf;
1930
-	int ret;
19311900 
19321901 	/* call register access here because irq_bus_lock & irq_bus_sync_unlock
19331902 	 * are only two callbacks executed in non-atomic contex.
19341903 	 */
1935
-	ret = lan78xx_read_reg(dev, INT_EP_CTL, &buf);
1904
+	lan78xx_read_reg(dev, INT_EP_CTL, &buf);
19361905 	if (buf != data->irqenable)
1937
-		ret = lan78xx_write_reg(dev, INT_EP_CTL, data->irqenable);
1906
+		lan78xx_write_reg(dev, INT_EP_CTL, data->irqenable);
19381907 
19391908 	mutex_unlock(&data->irq_lock);
19401909 }
....@@ -2001,7 +1970,6 @@
20011970 static int lan8835_fixup(struct phy_device *phydev)
20021971 {
20031972 	int buf;
2004
-	int ret;
20051973 	struct lan78xx_net *dev = netdev_priv(phydev->attached_dev);
20061974 
20071975 	/* LED2/PME_N/IRQ_N/RGMII_ID pin to IRQ_N mode */
....@@ -2011,11 +1979,11 @@
20111979 	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8010, buf);
20121980 
20131981 	/* RGMII MAC TXC Delay Enable */
2014
-	ret = lan78xx_write_reg(dev, MAC_RGMII_ID,
1982
+	lan78xx_write_reg(dev, MAC_RGMII_ID,
20151983 				MAC_RGMII_ID_TXC_DELAY_EN_);
20161984 
20171985 	/* RGMII TX DLL Tune Adjust */
2018
-	ret = lan78xx_write_reg(dev, RGMII_TX_BYP_DLL, 0x3D00);
1986
+	lan78xx_write_reg(dev, RGMII_TX_BYP_DLL, 0x3D00);
20191987 
20201988 	dev->interface = PHY_INTERFACE_MODE_RGMII_TXID;
20211989 
....@@ -2199,28 +2167,27 @@
21992167 
22002168 static int lan78xx_set_rx_max_frame_length(struct lan78xx_net *dev, int size)
22012169 {
2202
-	int ret = 0;
22032170 	u32 buf;
22042171 	bool rxenabled;
22052172 
2206
-	ret = lan78xx_read_reg(dev, MAC_RX, &buf);
2173
+	lan78xx_read_reg(dev, MAC_RX, &buf);
22072174 
22082175 	rxenabled = ((buf & MAC_RX_RXEN_) != 0);
22092176 
22102177 	if (rxenabled) {
22112178 		buf &= ~MAC_RX_RXEN_;
2212
-		ret = lan78xx_write_reg(dev, MAC_RX, buf);
2179
+		lan78xx_write_reg(dev, MAC_RX, buf);
22132180 	}
22142181 
22152182 	/* add 4 to size for FCS */
22162183 	buf &= ~MAC_RX_MAX_SIZE_MASK_;
22172184 	buf |= (((size + 4) << MAC_RX_MAX_SIZE_SHIFT_) & MAC_RX_MAX_SIZE_MASK_);
22182185 
2219
-	ret = lan78xx_write_reg(dev, MAC_RX, buf);
2186
+	lan78xx_write_reg(dev, MAC_RX, buf);
22202187 
22212188 	if (rxenabled) {
22222189 		buf |= MAC_RX_RXEN_;
2223
-		ret = lan78xx_write_reg(dev, MAC_RX, buf);
2190
+		lan78xx_write_reg(dev, MAC_RX, buf);
22242191 	}
22252192 
22262193 	return 0;
....@@ -2277,13 +2244,12 @@
22772244 	int ll_mtu = new_mtu + netdev->hard_header_len;
22782245 	int old_hard_mtu = dev->hard_mtu;
22792246 	int old_rx_urb_size = dev->rx_urb_size;
2280
-	int ret;
22812247 
22822248 	/* no second zero-length packet read wanted after mtu-sized packets */
22832249 	if ((ll_mtu % dev->maxpacket) == 0)
22842250 		return -EDOM;
22852251 
2286
-	ret = lan78xx_set_rx_max_frame_length(dev, new_mtu + VLAN_ETH_HLEN);
2252
+	lan78xx_set_rx_max_frame_length(dev, new_mtu + VLAN_ETH_HLEN);
22872253 
22882254 	netdev->mtu = new_mtu;
22892255 
....@@ -2306,7 +2272,6 @@
23062272 	struct lan78xx_net *dev = netdev_priv(netdev);
23072273 	struct sockaddr *addr = p;
23082274 	u32 addr_lo, addr_hi;
2309
-	int ret;
23102275 
23112276 	if (netif_running(netdev))
23122277 		return -EBUSY;
....@@ -2323,12 +2288,12 @@
23232288 	addr_hi = netdev->dev_addr[4] |
23242289 		  netdev->dev_addr[5] << 8;
23252290 
2326
-	ret = lan78xx_write_reg(dev, RX_ADDRL, addr_lo);
2327
-	ret = lan78xx_write_reg(dev, RX_ADDRH, addr_hi);
2291
+	lan78xx_write_reg(dev, RX_ADDRL, addr_lo);
2292
+	lan78xx_write_reg(dev, RX_ADDRH, addr_hi);
23282293 
23292294 	/* Added to support MAC address changes */
2330
-	ret = lan78xx_write_reg(dev, MAF_LO(0), addr_lo);
2331
-	ret = lan78xx_write_reg(dev, MAF_HI(0), addr_hi | MAF_HI_VALID_);
2295
+	lan78xx_write_reg(dev, MAF_LO(0), addr_lo);
2296
+	lan78xx_write_reg(dev, MAF_HI(0), addr_hi | MAF_HI_VALID_);
23322297 
23332298 	return 0;
23342299 }
....@@ -2340,7 +2305,6 @@
23402305 	struct lan78xx_net *dev = netdev_priv(netdev);
23412306 	struct lan78xx_priv *pdata = (struct lan78xx_priv *)(dev->data[0]);
23422307 	unsigned long flags;
2343
-	int ret;
23442308 
23452309 	spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
23462310 
....@@ -2364,7 +2328,7 @@
23642328 
23652329 	spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
23662330 
2367
-	ret = lan78xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
2331
+	lan78xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
23682332 
23692333 	return 0;
23702334 }
....@@ -3820,7 +3784,6 @@
38203784 static int lan78xx_set_suspend(struct lan78xx_net *dev, u32 wol)
38213785 {
38223786 	u32 buf;
3823
-	int ret;
38243787 	int mask_index;
38253788 	u16 crc;
38263789 	u32 temp_wucsr;
....@@ -3829,26 +3792,26 @@
38293792 	const u8 ipv6_multicast[3] = { 0x33, 0x33 };
38303793 	const u8 arp_type[2] = { 0x08, 0x06 };
38313794 
3832
-	ret = lan78xx_read_reg(dev, MAC_TX, &buf);
3795
+	lan78xx_read_reg(dev, MAC_TX, &buf);
38333796 	buf &= ~MAC_TX_TXEN_;
3834
-	ret = lan78xx_write_reg(dev, MAC_TX, buf);
3835
-	ret = lan78xx_read_reg(dev, MAC_RX, &buf);
3797
+	lan78xx_write_reg(dev, MAC_TX, buf);
3798
+	lan78xx_read_reg(dev, MAC_RX, &buf);
38363799 	buf &= ~MAC_RX_RXEN_;
3837
-	ret = lan78xx_write_reg(dev, MAC_RX, buf);
3800
+	lan78xx_write_reg(dev, MAC_RX, buf);
38383801 
3839
-	ret = lan78xx_write_reg(dev, WUCSR, 0);
3840
-	ret = lan78xx_write_reg(dev, WUCSR2, 0);
3841
-	ret = lan78xx_write_reg(dev, WK_SRC, 0xFFF1FF1FUL);
3802
+	lan78xx_write_reg(dev, WUCSR, 0);
3803
+	lan78xx_write_reg(dev, WUCSR2, 0);
3804
+	lan78xx_write_reg(dev, WK_SRC, 0xFFF1FF1FUL);
38423805 
38433806 	temp_wucsr = 0;
38443807 
38453808 	temp_pmt_ctl = 0;
3846
-	ret = lan78xx_read_reg(dev, PMT_CTL, &temp_pmt_ctl);
3809
+	lan78xx_read_reg(dev, PMT_CTL, &temp_pmt_ctl);
38473810 	temp_pmt_ctl &= ~PMT_CTL_RES_CLR_WKP_EN_;
38483811 	temp_pmt_ctl |= PMT_CTL_RES_CLR_WKP_STS_;
38493812 
38503813 	for (mask_index = 0; mask_index < NUM_OF_WUF_CFG; mask_index++)
3851
-		ret = lan78xx_write_reg(dev, WUF_CFG(mask_index), 0);
3814
+		lan78xx_write_reg(dev, WUF_CFG(mask_index), 0);
38523815 
38533816 	mask_index = 0;
38543817 	if (wol & WAKE_PHY) {
....@@ -3877,30 +3840,30 @@
38773840 
38783841 		/* set WUF_CFG & WUF_MASK for IPv4 Multicast */
38793842 		crc = lan78xx_wakeframe_crc16(ipv4_multicast, 3);
3880
-		ret = lan78xx_write_reg(dev, WUF_CFG(mask_index),
3843
+		lan78xx_write_reg(dev, WUF_CFG(mask_index),
38813844 					WUF_CFGX_EN_ |
38823845 					WUF_CFGX_TYPE_MCAST_ |
38833846 					(0 << WUF_CFGX_OFFSET_SHIFT_) |
38843847 					(crc & WUF_CFGX_CRC16_MASK_));
38853848 
3886
-		ret = lan78xx_write_reg(dev, WUF_MASK0(mask_index), 7);
3887
-		ret = lan78xx_write_reg(dev, WUF_MASK1(mask_index), 0);
3888
-		ret = lan78xx_write_reg(dev, WUF_MASK2(mask_index), 0);
3889
-		ret = lan78xx_write_reg(dev, WUF_MASK3(mask_index), 0);
3849
+		lan78xx_write_reg(dev, WUF_MASK0(mask_index), 7);
3850
+		lan78xx_write_reg(dev, WUF_MASK1(mask_index), 0);
3851
+		lan78xx_write_reg(dev, WUF_MASK2(mask_index), 0);
3852
+		lan78xx_write_reg(dev, WUF_MASK3(mask_index), 0);
38903853 		mask_index++;
38913854 
38923855 		/* for IPv6 Multicast */
38933856 		crc = lan78xx_wakeframe_crc16(ipv6_multicast, 2);
3894
-		ret = lan78xx_write_reg(dev, WUF_CFG(mask_index),
3857
+		lan78xx_write_reg(dev, WUF_CFG(mask_index),
38953858 					WUF_CFGX_EN_ |
38963859 					WUF_CFGX_TYPE_MCAST_ |
38973860 					(0 << WUF_CFGX_OFFSET_SHIFT_) |
38983861 					(crc & WUF_CFGX_CRC16_MASK_));
38993862 
3900
-		ret = lan78xx_write_reg(dev, WUF_MASK0(mask_index), 3);
3901
-		ret = lan78xx_write_reg(dev, WUF_MASK1(mask_index), 0);
3902
-		ret = lan78xx_write_reg(dev, WUF_MASK2(mask_index), 0);
3903
-		ret = lan78xx_write_reg(dev, WUF_MASK3(mask_index), 0);
3863
+		lan78xx_write_reg(dev, WUF_MASK0(mask_index), 3);
3864
+		lan78xx_write_reg(dev, WUF_MASK1(mask_index), 0);
3865
+		lan78xx_write_reg(dev, WUF_MASK2(mask_index), 0);
3866
+		lan78xx_write_reg(dev, WUF_MASK3(mask_index), 0);
39043867 		mask_index++;
39053868 
39063869 		temp_pmt_ctl |= PMT_CTL_WOL_EN_;
....@@ -3921,16 +3884,16 @@
39213884 		 * for packettype (offset 12,13) = ARP (0x0806)
39223885 		 */
39233886 		crc = lan78xx_wakeframe_crc16(arp_type, 2);
3924
-		ret = lan78xx_write_reg(dev, WUF_CFG(mask_index),
3887
+		lan78xx_write_reg(dev, WUF_CFG(mask_index),
39253888 					WUF_CFGX_EN_ |
39263889 					WUF_CFGX_TYPE_ALL_ |
39273890 					(0 << WUF_CFGX_OFFSET_SHIFT_) |
39283891 					(crc & WUF_CFGX_CRC16_MASK_));
39293892 
3930
-		ret = lan78xx_write_reg(dev, WUF_MASK0(mask_index), 0x3000);
3931
-		ret = lan78xx_write_reg(dev, WUF_MASK1(mask_index), 0);
3932
-		ret = lan78xx_write_reg(dev, WUF_MASK2(mask_index), 0);
3933
-		ret = lan78xx_write_reg(dev, WUF_MASK3(mask_index), 0);
3893
+		lan78xx_write_reg(dev, WUF_MASK0(mask_index), 0x3000);
3894
+		lan78xx_write_reg(dev, WUF_MASK1(mask_index), 0);
3895
+		lan78xx_write_reg(dev, WUF_MASK2(mask_index), 0);
3896
+		lan78xx_write_reg(dev, WUF_MASK3(mask_index), 0);
39343897 		mask_index++;
39353898 
39363899 		temp_pmt_ctl |= PMT_CTL_WOL_EN_;
....@@ -3938,7 +3901,7 @@
39383901 		temp_pmt_ctl |= PMT_CTL_SUS_MODE_0_;
39393902 	}
39403903 
3941
-	ret = lan78xx_write_reg(dev, WUCSR, temp_wucsr);
3904
+	lan78xx_write_reg(dev, WUCSR, temp_wucsr);
39423905 
39433906 	/* when multiple WOL bits are set */
39443907 	if (hweight_long((unsigned long)wol) > 1) {
....@@ -3946,16 +3909,16 @@
39463909 		temp_pmt_ctl &= ~PMT_CTL_SUS_MODE_MASK_;
39473910 		temp_pmt_ctl |= PMT_CTL_SUS_MODE_0_;
39483911 	}
3949
-	ret = lan78xx_write_reg(dev, PMT_CTL, temp_pmt_ctl);
3912
+	lan78xx_write_reg(dev, PMT_CTL, temp_pmt_ctl);
39503913 
39513914 	/* clear WUPS */
3952
-	ret = lan78xx_read_reg(dev, PMT_CTL, &buf);
3915
+	lan78xx_read_reg(dev, PMT_CTL, &buf);
39533916 	buf |= PMT_CTL_WUPS_MASK_;
3954
-	ret = lan78xx_write_reg(dev, PMT_CTL, buf);
3917
+	lan78xx_write_reg(dev, PMT_CTL, buf);
39553918 
3956
-	ret = lan78xx_read_reg(dev, MAC_RX, &buf);
3919
+	lan78xx_read_reg(dev, MAC_RX, &buf);
39573920 	buf |= MAC_RX_RXEN_;
3958
-	ret = lan78xx_write_reg(dev, MAC_RX, buf);
3921
+	lan78xx_write_reg(dev, MAC_RX, buf);
39593922 
39603923 	return 0;
39613924 }