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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/net/ethernet/xilinx/xilinx_axienet.h
....@@ -13,6 +13,7 @@
1313 #include <linux/spinlock.h>
1414 #include <linux/interrupt.h>
1515 #include <linux/if_vlan.h>
16
+#include <linux/phylink.h>
1617 
1718 /* Packet size info */
1819 #define XAE_HDR_SIZE			14 /* Size of Ethernet header */
....@@ -82,6 +83,8 @@
8283 
8384 #define XAXIDMA_CR_RUNSTOP_MASK	0x00000001 /* Start/stop DMA channel */
8485 #define XAXIDMA_CR_RESET_MASK	0x00000004 /* Reset DMA engine */
86
+
87
+#define XAXIDMA_SR_HALT_MASK	0x00000001 /* Indicates DMA channel halted */
8588 
8689 #define XAXIDMA_BD_NDESC_OFFSET		0x00 /* Next descriptor pointer */
8790 #define XAXIDMA_BD_BUFA_OFFSET		0x08 /* Buffer address */
....@@ -158,17 +161,11 @@
158161 #define XAE_FCC_OFFSET		0x0000040C /* Flow Control Configuration */
159162 #define XAE_EMMC_OFFSET		0x00000410 /* EMAC mode configuration */
160163 #define XAE_PHYC_OFFSET		0x00000414 /* RGMII/SGMII configuration */
164
+#define XAE_ID_OFFSET		0x000004F8 /* Identification register */
161165 #define XAE_MDIO_MC_OFFSET	0x00000500 /* MII Management Config */
162166 #define XAE_MDIO_MCR_OFFSET	0x00000504 /* MII Management Control */
163167 #define XAE_MDIO_MWD_OFFSET	0x00000508 /* MII Management Write Data */
164168 #define XAE_MDIO_MRD_OFFSET	0x0000050C /* MII Management Read Data */
165
-#define XAE_MDIO_MIS_OFFSET	0x00000600 /* MII Management Interrupt Status */
166
-/* MII Mgmt Interrupt Pending register offset */
167
-#define XAE_MDIO_MIP_OFFSET	0x00000620
168
-/* MII Management Interrupt Enable register offset */
169
-#define XAE_MDIO_MIE_OFFSET	0x00000640
170
-/* MII Management Interrupt Clear register offset. */
171
-#define XAE_MDIO_MIC_OFFSET	0x00000660
172169 #define XAE_UAW0_OFFSET		0x00000700 /* Unicast address word 0 */
173170 #define XAE_UAW1_OFFSET		0x00000704 /* Unicast address word 1 */
174171 #define XAE_FMI_OFFSET		0x00000708 /* Filter Mask Index */
....@@ -189,7 +186,7 @@
189186 #define XAE_RAF_TXVSTRPMODE_MASK	0x00000180 /* Tx VLAN STRIP mode */
190187 #define XAE_RAF_RXVSTRPMODE_MASK	0x00000600 /* Rx VLAN STRIP mode */
191188 #define XAE_RAF_NEWFNCENBL_MASK		0x00000800 /* New function mode */
192
-/* Exteneded Multicast Filtering mode */
189
+/* Extended Multicast Filtering mode */
193190 #define XAE_RAF_EMULTIFLTRENBL_MASK	0x00001000
194191 #define XAE_RAF_STATSRST_MASK		0x00002000 /* Stats. Counter Reset */
195192 #define XAE_RAF_RXBADFRMEN_MASK		0x00004000 /* Recv Bad Frame Enable */
....@@ -332,6 +329,7 @@
332329 #define XAE_FEATURE_PARTIAL_TX_CSUM	(1 << 1)
333330 #define XAE_FEATURE_FULL_RX_CSUM	(1 << 2)
334331 #define XAE_FEATURE_FULL_TX_CSUM	(1 << 3)
332
+#define XAE_FEATURE_DMA_64BIT		(1 << 4)
335333 
336334 #define XAE_NO_CSUM_OFFLOAD		0
337335 
....@@ -344,9 +342,9 @@
344342 /**
345343  * struct axidma_bd - Axi Dma buffer descriptor layout
346344  * @next:         MM2S/S2MM Next Descriptor Pointer
347
- * @reserved1:    Reserved and not used
345
+ * @next_msb:     MM2S/S2MM Next Descriptor Pointer (high 32 bits)
348346  * @phys:         MM2S/S2MM Buffer Address
349
- * @reserved2:    Reserved and not used
347
+ * @phys_msb:     MM2S/S2MM Buffer Address (high 32 bits)
350348  * @reserved3:    Reserved and not used
351349  * @reserved4:    Reserved and not used
352350  * @cntrl:        MM2S/S2MM Control value
....@@ -356,15 +354,12 @@
356354  * @app2:         MM2S/S2MM User Application Field 2.
357355  * @app3:         MM2S/S2MM User Application Field 3.
358356  * @app4:         MM2S/S2MM User Application Field 4.
359
- * @sw_id_offset: MM2S/S2MM Sw ID
360
- * @reserved5:    Reserved and not used
361
- * @reserved6:    Reserved and not used
362357  */
363358 struct axidma_bd {
364359 	u32 next;	/* Physical address of next buffer descriptor */
365
-	u32 reserved1;
360
+	u32 next_msb;	/* high 32 bits for IP >= v7.1, reserved on older IP */
366361 	u32 phys;
367
-	u32 reserved2;
362
+	u32 phys_msb;	/* for IP >= v7.1, reserved for older IP */
368363 	u32 reserved3;
369364 	u32 reserved4;
370365 	u32 cntrl;
....@@ -373,11 +368,9 @@
373368 	u32 app1;	/* TX start << 16 | insert */
374369 	u32 app2;	/* TX csum seed */
375370 	u32 app3;
376
-	u32 app4;
377
-	u32 sw_id_offset;
378
-	u32 reserved5;
379
-	u32 reserved6;
380
-};
371
+	u32 app4;   /* Last field used by HW */
372
+	struct sk_buff *skb;
373
+} __aligned(XAXIDMA_BD_MINIMUM_ALIGNMENT);
381374 
382375 /**
383376  * struct axienet_local - axienet private per device data
....@@ -385,6 +378,7 @@
385378  * @dev:	Pointer to device structure
386379  * @phy_node:	Pointer to device node structure
387380  * @mii_bus:	Pointer to MII bus structure
381
+ * @regs_start: Resource start for axienet device addresses
388382  * @regs:	Base address for the axienet_local device address space
389383  * @dma_regs:	Base address for the axidma device address space
390384  * @dma_err_tasklet: Tasklet structure to process Axi DMA errors
....@@ -422,28 +416,40 @@
422416 	/* Connection to PHY device */
423417 	struct device_node *phy_node;
424418 
419
+	struct phylink *phylink;
420
+	struct phylink_config phylink_config;
421
+
422
+	/* Reference to PCS/PMA PHY if used */
423
+	struct mdio_device *pcs_phy;
424
+
425
+	/* Clock for AXI bus */
426
+	struct clk *clk;
427
+
425428 	/* MDIO bus data */
426429 	struct mii_bus *mii_bus;	/* MII bus reference */
427430 
428431 	/* IO registers, dma functions and IRQs */
432
+	resource_size_t regs_start;
429433 	void __iomem *regs;
430434 	void __iomem *dma_regs;
431435 
432
-	struct tasklet_struct dma_err_tasklet;
436
+	struct work_struct dma_err_task;
433437 
434438 	int tx_irq;
435439 	int rx_irq;
440
+	int eth_irq;
436441 	phy_interface_t phy_mode;
437442 
438443 	u32 options;			/* Current options word */
439
-	u32 last_link;
440444 	u32 features;
441445 
442446 	/* Buffer descriptors */
443447 	struct axidma_bd *tx_bd_v;
444448 	dma_addr_t tx_bd_p;
449
+	u32 tx_bd_num;
445450 	struct axidma_bd *rx_bd_v;
446451 	dma_addr_t rx_bd_p;
452
+	u32 rx_bd_num;
447453 	u32 tx_bd_ci;
448454 	u32 tx_bd_tail;
449455 	u32 rx_bd_ci;
....@@ -481,7 +487,12 @@
481487  */
482488 static inline u32 axienet_ior(struct axienet_local *lp, off_t offset)
483489 {
484
-	return in_be32(lp->regs + offset);
490
+	return ioread32(lp->regs + offset);
491
+}
492
+
493
+static inline u32 axinet_ior_read_mcr(struct axienet_local *lp)
494
+{
495
+	return axienet_ior(lp, XAE_MDIO_MCR_OFFSET);
485496 }
486497 
487498 /**
....@@ -496,12 +507,13 @@
496507 static inline void axienet_iow(struct axienet_local *lp, off_t offset,
497508 			       u32 value)
498509 {
499
-	out_be32((lp->regs + offset), value);
510
+	iowrite32(value, lp->regs + offset);
500511 }
501512 
502513 /* Function prototypes visible in xilinx_axienet_mdio.c for other files */
503
-int axienet_mdio_setup(struct axienet_local *lp, struct device_node *np);
504
-int axienet_mdio_wait_until_ready(struct axienet_local *lp);
514
+int axienet_mdio_enable(struct axienet_local *lp);
515
+void axienet_mdio_disable(struct axienet_local *lp);
516
+int axienet_mdio_setup(struct axienet_local *lp);
505517 void axienet_mdio_teardown(struct axienet_local *lp);
506518 
507519 #endif /* XILINX_AXI_ENET_H */