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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/net/can/xilinx_can.c
....@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /* Xilinx CAN device driver
23  *
34  * Copyright (C) 2012 - 2014 Xilinx, Inc.
....@@ -6,15 +7,6 @@
67  *
78  * Description:
89  * This driver is developed for Axi CAN IP and for Zynq CANPS Controller.
9
- * This program is free software: you can redistribute it and/or modify
10
- * it under the terms of the GNU General Public License as published by
11
- * the Free Software Foundation, either version 2 of the License, or
12
- * (at your option) any later version.
13
- *
14
- * This program is distributed in the hope that it will be useful,
15
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
16
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17
- * GNU General Public License for more details.
1810  */
1911 
2012 #include <linux/clk.h>
....@@ -58,22 +50,32 @@
5850 	XCAN_AFR_OFFSET		= 0x60, /* Acceptance Filter */
5951 
6052 	/* only on CAN FD cores */
53
+	XCAN_F_BRPR_OFFSET	= 0x088, /* Data Phase Baud Rate
54
+					  * Prescalar
55
+					  */
56
+	XCAN_F_BTR_OFFSET	= 0x08C, /* Data Phase Bit Timing */
6157 	XCAN_TRR_OFFSET		= 0x0090, /* TX Buffer Ready Request */
6258 	XCAN_AFR_EXT_OFFSET	= 0x00E0, /* Acceptance Filter */
6359 	XCAN_FSR_OFFSET		= 0x00E8, /* RX FIFO Status */
6460 	XCAN_TXMSG_BASE_OFFSET	= 0x0100, /* TX Message Space */
6561 	XCAN_RXMSG_BASE_OFFSET	= 0x1100, /* RX Message Space */
62
+	XCAN_RXMSG_2_BASE_OFFSET	= 0x2100, /* RX Message Space */
63
+	XCAN_AFR_2_MASK_OFFSET	= 0x0A00, /* Acceptance Filter MASK */
64
+	XCAN_AFR_2_ID_OFFSET	= 0x0A04, /* Acceptance Filter ID */
6665 };
6766 
6867 #define XCAN_FRAME_ID_OFFSET(frame_base)	((frame_base) + 0x00)
6968 #define XCAN_FRAME_DLC_OFFSET(frame_base)	((frame_base) + 0x04)
7069 #define XCAN_FRAME_DW1_OFFSET(frame_base)	((frame_base) + 0x08)
7170 #define XCAN_FRAME_DW2_OFFSET(frame_base)	((frame_base) + 0x0C)
71
+#define XCANFD_FRAME_DW_OFFSET(frame_base)	((frame_base) + 0x08)
7272 
7373 #define XCAN_CANFD_FRAME_SIZE		0x48
7474 #define XCAN_TXMSG_FRAME_OFFSET(n)	(XCAN_TXMSG_BASE_OFFSET + \
7575 					 XCAN_CANFD_FRAME_SIZE * (n))
7676 #define XCAN_RXMSG_FRAME_OFFSET(n)	(XCAN_RXMSG_BASE_OFFSET + \
77
+					 XCAN_CANFD_FRAME_SIZE * (n))
78
+#define XCAN_RXMSG_2_FRAME_OFFSET(n)	(XCAN_RXMSG_2_BASE_OFFSET + \
7779 					 XCAN_CANFD_FRAME_SIZE * (n))
7880 
7981 /* the single TX mailbox used by this driver on CAN FD HW */
....@@ -123,8 +125,12 @@
123125 #define XCAN_IDR_RTR_MASK		0x00000001 /* Remote TX request */
124126 #define XCAN_DLCR_DLC_MASK		0xF0000000 /* Data length code */
125127 #define XCAN_FSR_FL_MASK		0x00003F00 /* RX Fill Level */
128
+#define XCAN_2_FSR_FL_MASK		0x00007F00 /* RX Fill Level */
126129 #define XCAN_FSR_IRI_MASK		0x00000080 /* RX Increment Read Index */
127130 #define XCAN_FSR_RI_MASK		0x0000001F /* RX Read Index */
131
+#define XCAN_2_FSR_RI_MASK		0x0000003F /* RX Read Index */
132
+#define XCAN_DLCR_EDL_MASK		0x08000000 /* EDL Mask in DLC */
133
+#define XCAN_DLCR_BRS_MASK		0x04000000 /* BRS Mask in DLC */
128134 
129135 /* CAN register bit shift - XCAN_<REG>_<BIT>_SHIFT */
130136 #define XCAN_BTR_SJW_SHIFT		7  /* Synchronous jump width */
....@@ -138,6 +144,7 @@
138144 
139145 /* CAN frame length constants */
140146 #define XCAN_FRAME_MAX_DATA_LEN		8
147
+#define XCANFD_DW_BYTES			4
141148 #define XCAN_TIMEOUT			(1 * HZ)
142149 
143150 /* TX-FIFO-empty interrupt available */
....@@ -152,8 +159,17 @@
152159  * instead of the regular FIFO at 0x50
153160  */
154161 #define XCAN_FLAG_RX_FIFO_MULTI	0x0010
162
+#define XCAN_FLAG_CANFD_2	0x0020
163
+
164
+enum xcan_ip_type {
165
+	XAXI_CAN = 0,
166
+	XZYNQ_CANPS,
167
+	XAXI_CANFD,
168
+	XAXI_CANFD_2_0,
169
+};
155170 
156171 struct xcan_devtype_data {
172
+	enum xcan_ip_type cantype;
157173 	unsigned int flags;
158174 	const struct can_bittiming_const *bittiming_const;
159175 	const char *bus_clk_name;
....@@ -180,14 +196,14 @@
180196  */
181197 struct xcan_priv {
182198 	struct can_priv can;
183
-	spinlock_t tx_lock;
199
+	spinlock_t tx_lock; /* Lock for synchronizing TX interrupt handling */
184200 	unsigned int tx_head;
185201 	unsigned int tx_tail;
186202 	unsigned int tx_max;
187203 	struct napi_struct napi;
188204 	u32 (*read_reg)(const struct xcan_priv *priv, enum xcan_reg reg);
189205 	void (*write_reg)(const struct xcan_priv *priv, enum xcan_reg reg,
190
-			u32 val);
206
+			  u32 val);
191207 	struct device *dev;
192208 	void __iomem *reg_base;
193209 	unsigned long irq_flags;
....@@ -209,10 +225,50 @@
209225 	.brp_inc = 1,
210226 };
211227 
228
+/* AXI CANFD Arbitration Bittiming constants as per AXI CANFD 1.0 spec */
212229 static const struct can_bittiming_const xcan_bittiming_const_canfd = {
213230 	.name = DRIVER_NAME,
214231 	.tseg1_min = 1,
215232 	.tseg1_max = 64,
233
+	.tseg2_min = 1,
234
+	.tseg2_max = 16,
235
+	.sjw_max = 16,
236
+	.brp_min = 1,
237
+	.brp_max = 256,
238
+	.brp_inc = 1,
239
+};
240
+
241
+/* AXI CANFD Data Bittiming constants as per AXI CANFD 1.0 specs */
242
+static const struct can_bittiming_const xcan_data_bittiming_const_canfd = {
243
+	.name = DRIVER_NAME,
244
+	.tseg1_min = 1,
245
+	.tseg1_max = 16,
246
+	.tseg2_min = 1,
247
+	.tseg2_max = 8,
248
+	.sjw_max = 8,
249
+	.brp_min = 1,
250
+	.brp_max = 256,
251
+	.brp_inc = 1,
252
+};
253
+
254
+/* AXI CANFD 2.0 Arbitration Bittiming constants as per AXI CANFD 2.0 spec */
255
+static const struct can_bittiming_const xcan_bittiming_const_canfd2 = {
256
+	.name = DRIVER_NAME,
257
+	.tseg1_min = 1,
258
+	.tseg1_max = 256,
259
+	.tseg2_min = 1,
260
+	.tseg2_max = 128,
261
+	.sjw_max = 128,
262
+	.brp_min = 1,
263
+	.brp_max = 256,
264
+	.brp_inc = 1,
265
+};
266
+
267
+/* AXI CANFD 2.0 Data Bittiming constants as per AXI CANFD 2.0 spec */
268
+static const struct can_bittiming_const xcan_data_bittiming_const_canfd2 = {
269
+	.name = DRIVER_NAME,
270
+	.tseg1_min = 1,
271
+	.tseg1_max = 32,
216272 	.tseg2_min = 1,
217273 	.tseg2_max = 16,
218274 	.sjw_max = 16,
....@@ -230,7 +286,7 @@
230286  * Write data to the paricular CAN register
231287  */
232288 static void xcan_write_reg_le(const struct xcan_priv *priv, enum xcan_reg reg,
233
-			u32 val)
289
+			      u32 val)
234290 {
235291 	iowrite32(val, priv->reg_base + reg);
236292 }
....@@ -257,7 +313,7 @@
257313  * Write data to the paricular CAN register
258314  */
259315 static void xcan_write_reg_be(const struct xcan_priv *priv, enum xcan_reg reg,
260
-			u32 val)
316
+			      u32 val)
261317 {
262318 	iowrite32be(val, priv->reg_base + reg);
263319 }
....@@ -335,6 +391,7 @@
335391 {
336392 	struct xcan_priv *priv = netdev_priv(ndev);
337393 	struct can_bittiming *bt = &priv->can.bittiming;
394
+	struct can_bittiming *dbt = &priv->can.data_bittiming;
338395 	u32 btr0, btr1;
339396 	u32 is_config_mode;
340397 
....@@ -345,7 +402,7 @@
345402 				XCAN_SR_CONFIG_MASK;
346403 	if (!is_config_mode) {
347404 		netdev_alert(ndev,
348
-		     "BUG! Cannot set bittiming - CAN is not in config mode\n");
405
+			     "BUG! Cannot set bittiming - CAN is not in config mode\n");
349406 		return -EPERM;
350407 	}
351408 
....@@ -364,9 +421,27 @@
364421 	priv->write_reg(priv, XCAN_BRPR_OFFSET, btr0);
365422 	priv->write_reg(priv, XCAN_BTR_OFFSET, btr1);
366423 
424
+	if (priv->devtype.cantype == XAXI_CANFD ||
425
+	    priv->devtype.cantype == XAXI_CANFD_2_0) {
426
+		/* Setting Baud Rate prescalar value in F_BRPR Register */
427
+		btr0 = dbt->brp - 1;
428
+
429
+		/* Setting Time Segment 1 in BTR Register */
430
+		btr1 = dbt->prop_seg + dbt->phase_seg1 - 1;
431
+
432
+		/* Setting Time Segment 2 in BTR Register */
433
+		btr1 |= (dbt->phase_seg2 - 1) << priv->devtype.btr_ts2_shift;
434
+
435
+		/* Setting Synchronous jump width in BTR Register */
436
+		btr1 |= (dbt->sjw - 1) << priv->devtype.btr_sjw_shift;
437
+
438
+		priv->write_reg(priv, XCAN_F_BRPR_OFFSET, btr0);
439
+		priv->write_reg(priv, XCAN_F_BTR_OFFSET, btr1);
440
+	}
441
+
367442 	netdev_dbg(ndev, "BRPR=0x%08x, BTR=0x%08x\n",
368
-			priv->read_reg(priv, XCAN_BRPR_OFFSET),
369
-			priv->read_reg(priv, XCAN_BTR_OFFSET));
443
+		   priv->read_reg(priv, XCAN_BRPR_OFFSET),
444
+		   priv->read_reg(priv, XCAN_BTR_OFFSET));
370445 
371446 	return 0;
372447 }
....@@ -384,9 +459,8 @@
384459 static int xcan_chip_start(struct net_device *ndev)
385460 {
386461 	struct xcan_priv *priv = netdev_priv(ndev);
387
-	u32 reg_msr, reg_sr_mask;
462
+	u32 reg_msr;
388463 	int err;
389
-	unsigned long timeout;
390464 	u32 ier;
391465 
392466 	/* Check if it is in reset mode */
....@@ -398,7 +472,13 @@
398472 	if (err < 0)
399473 		return err;
400474 
401
-	/* Enable interrupts */
475
+	/* Enable interrupts
476
+	 *
477
+	 * We enable the ERROR interrupt even with
478
+	 * CAN_CTRLMODE_BERR_REPORTING disabled as there is no
479
+	 * dedicated interrupt for a state change to
480
+	 * ERROR_WARNING/ERROR_PASSIVE.
481
+	 */
402482 	ier = XCAN_IXR_TXOK_MASK | XCAN_IXR_BSOFF_MASK |
403483 		XCAN_IXR_WKUP_MASK | XCAN_IXR_SLP_MASK |
404484 		XCAN_IXR_ERROR_MASK | XCAN_IXR_RXOFLW_MASK |
....@@ -410,13 +490,10 @@
410490 	priv->write_reg(priv, XCAN_IER_OFFSET, ier);
411491 
412492 	/* Check whether it is loopback mode or normal mode  */
413
-	if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
493
+	if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
414494 		reg_msr = XCAN_MSR_LBACK_MASK;
415
-		reg_sr_mask = XCAN_SR_LBACK_MASK;
416
-	} else {
495
+	else
417496 		reg_msr = 0x0;
418
-		reg_sr_mask = XCAN_SR_NORMAL_MASK;
419
-	}
420497 
421498 	/* enable the first extended filter, if any, as cores with extended
422499 	 * filtering default to non-receipt if all filters are disabled
....@@ -427,16 +504,8 @@
427504 	priv->write_reg(priv, XCAN_MSR_OFFSET, reg_msr);
428505 	priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK);
429506 
430
-	timeout = jiffies + XCAN_TIMEOUT;
431
-	while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & reg_sr_mask)) {
432
-		if (time_after(jiffies, timeout)) {
433
-			netdev_warn(ndev,
434
-				"timed out for correct mode\n");
435
-			return -ETIMEDOUT;
436
-		}
437
-	}
438507 	netdev_dbg(ndev, "status:#x%08x\n",
439
-			priv->read_reg(priv, XCAN_SR_OFFSET));
508
+		   priv->read_reg(priv, XCAN_SR_OFFSET));
440509 
441510 	priv->can.state = CAN_STATE_ERROR_ACTIVE;
442511 	return 0;
....@@ -475,14 +544,17 @@
475544 
476545 /**
477546  * xcan_write_frame - Write a frame to HW
547
+ * @ndev:		Pointer to net_device structure
478548  * @skb:		sk_buff pointer that contains data to be Txed
479549  * @frame_offset:	Register offset to write the frame to
480550  */
481
-static void xcan_write_frame(struct xcan_priv *priv, struct sk_buff *skb,
551
+static void xcan_write_frame(struct net_device *ndev, struct sk_buff *skb,
482552 			     int frame_offset)
483553 {
484554 	u32 id, dlc, data[2] = {0, 0};
485
-	struct can_frame *cf = (struct can_frame *)skb->data;
555
+	struct canfd_frame *cf = (struct canfd_frame *)skb->data;
556
+	u32 ramoff, dwindex = 0, i;
557
+	struct xcan_priv *priv = netdev_priv(ndev);
486558 
487559 	/* Watch carefully on the bit sequence */
488560 	if (cf->can_id & CAN_EFF_FLAG) {
....@@ -490,7 +562,7 @@
490562 		id = ((cf->can_id & CAN_EFF_MASK) << XCAN_IDR_ID2_SHIFT) &
491563 			XCAN_IDR_ID2_MASK;
492564 		id |= (((cf->can_id & CAN_EFF_MASK) >>
493
-			(CAN_EFF_ID_BITS-CAN_SFF_ID_BITS)) <<
565
+			(CAN_EFF_ID_BITS - CAN_SFF_ID_BITS)) <<
494566 			XCAN_IDR_ID1_SHIFT) & XCAN_IDR_ID1_MASK;
495567 
496568 		/* The substibute remote TX request bit should be "1"
....@@ -511,31 +583,59 @@
511583 			id |= XCAN_IDR_SRR_MASK;
512584 	}
513585 
514
-	dlc = cf->can_dlc << XCAN_DLCR_DLC_SHIFT;
586
+	dlc = can_len2dlc(cf->len) << XCAN_DLCR_DLC_SHIFT;
587
+	if (can_is_canfd_skb(skb)) {
588
+		if (cf->flags & CANFD_BRS)
589
+			dlc |= XCAN_DLCR_BRS_MASK;
590
+		dlc |= XCAN_DLCR_EDL_MASK;
591
+	}
515592 
516
-	if (cf->can_dlc > 0)
517
-		data[0] = be32_to_cpup((__be32 *)(cf->data + 0));
518
-	if (cf->can_dlc > 4)
519
-		data[1] = be32_to_cpup((__be32 *)(cf->data + 4));
593
+	if (!(priv->devtype.flags & XCAN_FLAG_TX_MAILBOXES) &&
594
+	    (priv->devtype.flags & XCAN_FLAG_TXFEMP))
595
+		can_put_echo_skb(skb, ndev, priv->tx_head % priv->tx_max);
596
+	else
597
+		can_put_echo_skb(skb, ndev, 0);
598
+
599
+	priv->tx_head++;
520600 
521601 	priv->write_reg(priv, XCAN_FRAME_ID_OFFSET(frame_offset), id);
522602 	/* If the CAN frame is RTR frame this write triggers transmission
523603 	 * (not on CAN FD)
524604 	 */
525605 	priv->write_reg(priv, XCAN_FRAME_DLC_OFFSET(frame_offset), dlc);
526
-	if (!(cf->can_id & CAN_RTR_FLAG)) {
527
-		priv->write_reg(priv, XCAN_FRAME_DW1_OFFSET(frame_offset),
528
-				data[0]);
529
-		/* If the CAN frame is Standard/Extended frame this
530
-		 * write triggers transmission (not on CAN FD)
531
-		 */
532
-		priv->write_reg(priv, XCAN_FRAME_DW2_OFFSET(frame_offset),
533
-				data[1]);
606
+	if (priv->devtype.cantype == XAXI_CANFD ||
607
+	    priv->devtype.cantype == XAXI_CANFD_2_0) {
608
+		for (i = 0; i < cf->len; i += 4) {
609
+			ramoff = XCANFD_FRAME_DW_OFFSET(frame_offset) +
610
+					(dwindex * XCANFD_DW_BYTES);
611
+			priv->write_reg(priv, ramoff,
612
+					be32_to_cpup((__be32 *)(cf->data + i)));
613
+			dwindex++;
614
+		}
615
+	} else {
616
+		if (cf->len > 0)
617
+			data[0] = be32_to_cpup((__be32 *)(cf->data + 0));
618
+		if (cf->len > 4)
619
+			data[1] = be32_to_cpup((__be32 *)(cf->data + 4));
620
+
621
+		if (!(cf->can_id & CAN_RTR_FLAG)) {
622
+			priv->write_reg(priv,
623
+					XCAN_FRAME_DW1_OFFSET(frame_offset),
624
+					data[0]);
625
+			/* If the CAN frame is Standard/Extended frame this
626
+			 * write triggers transmission (not on CAN FD)
627
+			 */
628
+			priv->write_reg(priv,
629
+					XCAN_FRAME_DW2_OFFSET(frame_offset),
630
+					data[1]);
631
+		}
534632 	}
535633 }
536634 
537635 /**
538636  * xcan_start_xmit_fifo - Starts the transmission (FIFO mode)
637
+ * @skb:	sk_buff pointer that contains data to be Txed
638
+ * @ndev:	Pointer to net_device structure
539639  *
540640  * Return: 0 on success, -ENOSPC if FIFO is full.
541641  */
....@@ -549,13 +649,9 @@
549649 			XCAN_SR_TXFLL_MASK))
550650 		return -ENOSPC;
551651 
552
-	can_put_echo_skb(skb, ndev, priv->tx_head % priv->tx_max);
553
-
554652 	spin_lock_irqsave(&priv->tx_lock, flags);
555653 
556
-	priv->tx_head++;
557
-
558
-	xcan_write_frame(priv, skb, XCAN_TXFIFO_OFFSET);
654
+	xcan_write_frame(ndev, skb, XCAN_TXFIFO_OFFSET);
559655 
560656 	/* Clear TX-FIFO-empty interrupt for xcan_tx_interrupt() */
561657 	if (priv->tx_max > 1)
....@@ -572,6 +668,8 @@
572668 
573669 /**
574670  * xcan_start_xmit_mailbox - Starts the transmission (mailbox mode)
671
+ * @skb:	sk_buff pointer that contains data to be Txed
672
+ * @ndev:	Pointer to net_device structure
575673  *
576674  * Return: 0 on success, -ENOSPC if there is no space
577675  */
....@@ -584,13 +682,9 @@
584682 		     BIT(XCAN_TX_MAILBOX_IDX)))
585683 		return -ENOSPC;
586684 
587
-	can_put_echo_skb(skb, ndev, 0);
588
-
589685 	spin_lock_irqsave(&priv->tx_lock, flags);
590686 
591
-	priv->tx_head++;
592
-
593
-	xcan_write_frame(priv, skb,
687
+	xcan_write_frame(ndev, skb,
594688 			 XCAN_TXMSG_FRAME_OFFSET(XCAN_TX_MAILBOX_IDX));
595689 
596690 	/* Mark buffer as ready for transmit */
....@@ -697,6 +791,88 @@
697791 	}
698792 
699793 	stats->rx_bytes += cf->can_dlc;
794
+	stats->rx_packets++;
795
+	netif_receive_skb(skb);
796
+
797
+	return 1;
798
+}
799
+
800
+/**
801
+ * xcanfd_rx -  Is called from CAN isr to complete the received
802
+ *		frame  processing
803
+ * @ndev:	Pointer to net_device structure
804
+ * @frame_base:	Register offset to the frame to be read
805
+ *
806
+ * This function is invoked from the CAN isr(poll) to process the Rx frames. It
807
+ * does minimal processing and invokes "netif_receive_skb" to complete further
808
+ * processing.
809
+ * Return: 1 on success and 0 on failure.
810
+ */
811
+static int xcanfd_rx(struct net_device *ndev, int frame_base)
812
+{
813
+	struct xcan_priv *priv = netdev_priv(ndev);
814
+	struct net_device_stats *stats = &ndev->stats;
815
+	struct canfd_frame *cf;
816
+	struct sk_buff *skb;
817
+	u32 id_xcan, dlc, data[2] = {0, 0}, dwindex = 0, i, dw_offset;
818
+
819
+	id_xcan = priv->read_reg(priv, XCAN_FRAME_ID_OFFSET(frame_base));
820
+	dlc = priv->read_reg(priv, XCAN_FRAME_DLC_OFFSET(frame_base));
821
+	if (dlc & XCAN_DLCR_EDL_MASK)
822
+		skb = alloc_canfd_skb(ndev, &cf);
823
+	else
824
+		skb = alloc_can_skb(ndev, (struct can_frame **)&cf);
825
+
826
+	if (unlikely(!skb)) {
827
+		stats->rx_dropped++;
828
+		return 0;
829
+	}
830
+
831
+	/* Change Xilinx CANFD data length format to socketCAN data
832
+	 * format
833
+	 */
834
+	if (dlc & XCAN_DLCR_EDL_MASK)
835
+		cf->len = can_dlc2len((dlc & XCAN_DLCR_DLC_MASK) >>
836
+				  XCAN_DLCR_DLC_SHIFT);
837
+	else
838
+		cf->len = get_can_dlc((dlc & XCAN_DLCR_DLC_MASK) >>
839
+					  XCAN_DLCR_DLC_SHIFT);
840
+
841
+	/* Change Xilinx CAN ID format to socketCAN ID format */
842
+	if (id_xcan & XCAN_IDR_IDE_MASK) {
843
+		/* The received frame is an Extended format frame */
844
+		cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> 3;
845
+		cf->can_id |= (id_xcan & XCAN_IDR_ID2_MASK) >>
846
+				XCAN_IDR_ID2_SHIFT;
847
+		cf->can_id |= CAN_EFF_FLAG;
848
+		if (id_xcan & XCAN_IDR_RTR_MASK)
849
+			cf->can_id |= CAN_RTR_FLAG;
850
+	} else {
851
+		/* The received frame is a standard format frame */
852
+		cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >>
853
+				XCAN_IDR_ID1_SHIFT;
854
+		if (!(dlc & XCAN_DLCR_EDL_MASK) && (id_xcan &
855
+					XCAN_IDR_SRR_MASK))
856
+			cf->can_id |= CAN_RTR_FLAG;
857
+	}
858
+
859
+	/* Check the frame received is FD or not*/
860
+	if (dlc & XCAN_DLCR_EDL_MASK) {
861
+		for (i = 0; i < cf->len; i += 4) {
862
+			dw_offset = XCANFD_FRAME_DW_OFFSET(frame_base) +
863
+					(dwindex * XCANFD_DW_BYTES);
864
+			data[0] = priv->read_reg(priv, dw_offset);
865
+			*(__be32 *)(cf->data + i) = cpu_to_be32(data[0]);
866
+			dwindex++;
867
+		}
868
+	} else {
869
+		for (i = 0; i < cf->len; i += 4) {
870
+			dw_offset = XCANFD_FRAME_DW_OFFSET(frame_base);
871
+			data[0] = priv->read_reg(priv, dw_offset + i);
872
+			*(__be32 *)(cf->data + i) = cpu_to_be32(data[0]);
873
+		}
874
+	}
875
+	stats->rx_bytes += cf->len;
700876 	stats->rx_packets++;
701877 	netif_receive_skb(skb);
702878 
....@@ -813,11 +989,8 @@
813989 {
814990 	struct xcan_priv *priv = netdev_priv(ndev);
815991 	struct net_device_stats *stats = &ndev->stats;
816
-	struct can_frame *cf;
817
-	struct sk_buff *skb;
992
+	struct can_frame cf = { };
818993 	u32 err_status;
819
-
820
-	skb = alloc_can_err_skb(ndev, &cf);
821994 
822995 	err_status = priv->read_reg(priv, XCAN_ESR_OFFSET);
823996 	priv->write_reg(priv, XCAN_ESR_OFFSET, err_status);
....@@ -828,32 +1001,27 @@
8281001 		/* Leave device in Config Mode in bus-off state */
8291002 		priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
8301003 		can_bus_off(ndev);
831
-		if (skb)
832
-			cf->can_id |= CAN_ERR_BUSOFF;
1004
+		cf.can_id |= CAN_ERR_BUSOFF;
8331005 	} else {
8341006 		enum can_state new_state = xcan_current_error_state(ndev);
8351007 
8361008 		if (new_state != priv->can.state)
837
-			xcan_set_error_state(ndev, new_state, skb ? cf : NULL);
1009
+			xcan_set_error_state(ndev, new_state, &cf);
8381010 	}
8391011 
8401012 	/* Check for Arbitration lost interrupt */
8411013 	if (isr & XCAN_IXR_ARBLST_MASK) {
8421014 		priv->can.can_stats.arbitration_lost++;
843
-		if (skb) {
844
-			cf->can_id |= CAN_ERR_LOSTARB;
845
-			cf->data[0] = CAN_ERR_LOSTARB_UNSPEC;
846
-		}
1015
+		cf.can_id |= CAN_ERR_LOSTARB;
1016
+		cf.data[0] = CAN_ERR_LOSTARB_UNSPEC;
8471017 	}
8481018 
8491019 	/* Check for RX FIFO Overflow interrupt */
8501020 	if (isr & XCAN_IXR_RXOFLW_MASK) {
8511021 		stats->rx_over_errors++;
8521022 		stats->rx_errors++;
853
-		if (skb) {
854
-			cf->can_id |= CAN_ERR_CRTL;
855
-			cf->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW;
856
-		}
1023
+		cf.can_id |= CAN_ERR_CRTL;
1024
+		cf.data[1] |= CAN_ERR_CRTL_RX_OVERFLOW;
8571025 	}
8581026 
8591027 	/* Check for RX Match Not Finished interrupt */
....@@ -861,72 +1029,81 @@
8611029 		stats->rx_dropped++;
8621030 		stats->rx_errors++;
8631031 		netdev_err(ndev, "RX match not finished, frame discarded\n");
864
-		if (skb) {
865
-			cf->can_id |= CAN_ERR_CRTL;
866
-			cf->data[1] |= CAN_ERR_CRTL_UNSPEC;
867
-		}
1032
+		cf.can_id |= CAN_ERR_CRTL;
1033
+		cf.data[1] |= CAN_ERR_CRTL_UNSPEC;
8681034 	}
8691035 
8701036 	/* Check for error interrupt */
8711037 	if (isr & XCAN_IXR_ERROR_MASK) {
872
-		if (skb)
873
-			cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
1038
+		bool berr_reporting = false;
1039
+
1040
+		if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) {
1041
+			berr_reporting = true;
1042
+			cf.can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
1043
+		}
8741044 
8751045 		/* Check for Ack error interrupt */
8761046 		if (err_status & XCAN_ESR_ACKER_MASK) {
8771047 			stats->tx_errors++;
878
-			if (skb) {
879
-				cf->can_id |= CAN_ERR_ACK;
880
-				cf->data[3] = CAN_ERR_PROT_LOC_ACK;
1048
+			if (berr_reporting) {
1049
+				cf.can_id |= CAN_ERR_ACK;
1050
+				cf.data[3] = CAN_ERR_PROT_LOC_ACK;
8811051 			}
8821052 		}
8831053 
8841054 		/* Check for Bit error interrupt */
8851055 		if (err_status & XCAN_ESR_BERR_MASK) {
8861056 			stats->tx_errors++;
887
-			if (skb) {
888
-				cf->can_id |= CAN_ERR_PROT;
889
-				cf->data[2] = CAN_ERR_PROT_BIT;
1057
+			if (berr_reporting) {
1058
+				cf.can_id |= CAN_ERR_PROT;
1059
+				cf.data[2] = CAN_ERR_PROT_BIT;
8901060 			}
8911061 		}
8921062 
8931063 		/* Check for Stuff error interrupt */
8941064 		if (err_status & XCAN_ESR_STER_MASK) {
8951065 			stats->rx_errors++;
896
-			if (skb) {
897
-				cf->can_id |= CAN_ERR_PROT;
898
-				cf->data[2] = CAN_ERR_PROT_STUFF;
1066
+			if (berr_reporting) {
1067
+				cf.can_id |= CAN_ERR_PROT;
1068
+				cf.data[2] = CAN_ERR_PROT_STUFF;
8991069 			}
9001070 		}
9011071 
9021072 		/* Check for Form error interrupt */
9031073 		if (err_status & XCAN_ESR_FMER_MASK) {
9041074 			stats->rx_errors++;
905
-			if (skb) {
906
-				cf->can_id |= CAN_ERR_PROT;
907
-				cf->data[2] = CAN_ERR_PROT_FORM;
1075
+			if (berr_reporting) {
1076
+				cf.can_id |= CAN_ERR_PROT;
1077
+				cf.data[2] = CAN_ERR_PROT_FORM;
9081078 			}
9091079 		}
9101080 
9111081 		/* Check for CRC error interrupt */
9121082 		if (err_status & XCAN_ESR_CRCER_MASK) {
9131083 			stats->rx_errors++;
914
-			if (skb) {
915
-				cf->can_id |= CAN_ERR_PROT;
916
-				cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
1084
+			if (berr_reporting) {
1085
+				cf.can_id |= CAN_ERR_PROT;
1086
+				cf.data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
9171087 			}
9181088 		}
919
-			priv->can.can_stats.bus_error++;
1089
+		priv->can.can_stats.bus_error++;
9201090 	}
9211091 
922
-	if (skb) {
923
-		stats->rx_packets++;
924
-		stats->rx_bytes += cf->can_dlc;
925
-		netif_rx(skb);
1092
+	if (cf.can_id) {
1093
+		struct can_frame *skb_cf;
1094
+		struct sk_buff *skb = alloc_can_err_skb(ndev, &skb_cf);
1095
+
1096
+		if (skb) {
1097
+			skb_cf->can_id |= cf.can_id;
1098
+			memcpy(skb_cf->data, cf.data, CAN_ERR_DLC);
1099
+			stats->rx_packets++;
1100
+			stats->rx_bytes += CAN_ERR_DLC;
1101
+			netif_rx(skb);
1102
+		}
9261103 	}
9271104 
9281105 	netdev_dbg(ndev, "%s: error status register:0x%x\n",
929
-			__func__, priv->read_reg(priv, XCAN_ESR_OFFSET));
1106
+		   __func__, priv->read_reg(priv, XCAN_ESR_OFFSET));
9301107 }
9311108 
9321109 /**
....@@ -952,6 +1129,7 @@
9521129 
9531130 /**
9541131  * xcan_rx_fifo_get_next_frame - Get register offset of next RX frame
1132
+ * @priv:	Driver private data structure
9551133  *
9561134  * Return: Register offset of the next frame in RX FIFO.
9571135  */
....@@ -960,7 +1138,7 @@
9601138 	int offset;
9611139 
9621140 	if (priv->devtype.flags & XCAN_FLAG_RX_FIFO_MULTI) {
963
-		u32 fsr;
1141
+		u32 fsr, mask;
9641142 
9651143 		/* clear RXOK before the is-empty check so that any newly
9661144 		 * received frame will reassert it without a race
....@@ -970,10 +1148,20 @@
9701148 		fsr = priv->read_reg(priv, XCAN_FSR_OFFSET);
9711149 
9721150 		/* check if RX FIFO is empty */
973
-		if (!(fsr & XCAN_FSR_FL_MASK))
1151
+		if (priv->devtype.flags & XCAN_FLAG_CANFD_2)
1152
+			mask = XCAN_2_FSR_FL_MASK;
1153
+		else
1154
+			mask = XCAN_FSR_FL_MASK;
1155
+
1156
+		if (!(fsr & mask))
9741157 			return -ENOENT;
9751158 
976
-		offset = XCAN_RXMSG_FRAME_OFFSET(fsr & XCAN_FSR_RI_MASK);
1159
+		if (priv->devtype.flags & XCAN_FLAG_CANFD_2)
1160
+			offset =
1161
+			  XCAN_RXMSG_2_FRAME_OFFSET(fsr & XCAN_2_FSR_RI_MASK);
1162
+		else
1163
+			offset =
1164
+			  XCAN_RXMSG_FRAME_OFFSET(fsr & XCAN_FSR_RI_MASK);
9771165 
9781166 	} else {
9791167 		/* check if RX FIFO is empty */
....@@ -1008,7 +1196,10 @@
10081196 
10091197 	while ((frame_offset = xcan_rx_fifo_get_next_frame(priv)) >= 0 &&
10101198 	       (work_done < quota)) {
1011
-		work_done += xcan_rx(ndev, frame_offset);
1199
+		if (xcan_rx_int_mask(priv) & XCAN_IXR_RXOK_MASK)
1200
+			work_done += xcanfd_rx(ndev, frame_offset);
1201
+		else
1202
+			work_done += xcan_rx(ndev, frame_offset);
10121203 
10131204 		if (priv->devtype.flags & XCAN_FLAG_RX_FIFO_MULTI)
10141205 			/* increment read index */
....@@ -1083,8 +1274,10 @@
10831274 		 *     via TXFEMP handling as we read TXFEMP *after* TXOK
10841275 		 *     clear to satisfy (1).
10851276 		 */
1086
-		while ((isr & XCAN_IXR_TXOK_MASK) && !WARN_ON(++retries == 100)) {
1087
-			priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK);
1277
+		while ((isr & XCAN_IXR_TXOK_MASK) &&
1278
+		       !WARN_ON(++retries == 100)) {
1279
+			priv->write_reg(priv, XCAN_ICR_OFFSET,
1280
+					XCAN_IXR_TXOK_MASK);
10881281 			isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
10891282 		}
10901283 
....@@ -1115,7 +1308,7 @@
11151308 /**
11161309  * xcan_interrupt - CAN Isr
11171310  * @irq:	irq number
1118
- * @dev_id:	device id poniter
1311
+ * @dev_id:	device id pointer
11191312  *
11201313  * This is the xilinx CAN Isr. It checks for the type of interrupt
11211314  * and invokes the corresponding ISR.
....@@ -1176,9 +1369,13 @@
11761369 static void xcan_chip_stop(struct net_device *ndev)
11771370 {
11781371 	struct xcan_priv *priv = netdev_priv(ndev);
1372
+	int ret;
11791373 
11801374 	/* Disable interrupts and leave the can in configuration mode */
1181
-	set_reset_mode(ndev);
1375
+	ret = set_reset_mode(ndev);
1376
+	if (ret < 0)
1377
+		netdev_dbg(ndev, "set_reset_mode() Failed\n");
1378
+
11821379 	priv->can.state = CAN_STATE_STOPPED;
11831380 }
11841381 
....@@ -1197,12 +1394,12 @@
11971394 	ret = pm_runtime_get_sync(priv->dev);
11981395 	if (ret < 0) {
11991396 		netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n",
1200
-				__func__, ret);
1201
-		return ret;
1397
+			   __func__, ret);
1398
+		goto err;
12021399 	}
12031400 
12041401 	ret = request_irq(ndev->irq, xcan_interrupt, priv->irq_flags,
1205
-			ndev->name, ndev);
1402
+			  ndev->name, ndev);
12061403 	if (ret < 0) {
12071404 		netdev_err(ndev, "irq allocation for CAN failed\n");
12081405 		goto err;
....@@ -1273,7 +1470,7 @@
12731470  * Return: 0 on success and failure value on error
12741471  */
12751472 static int xcan_get_berr_counter(const struct net_device *ndev,
1276
-					struct can_berr_counter *bec)
1473
+				 struct can_berr_counter *bec)
12771474 {
12781475 	struct xcan_priv *priv = netdev_priv(ndev);
12791476 	int ret;
....@@ -1281,7 +1478,8 @@
12811478 	ret = pm_runtime_get_sync(priv->dev);
12821479 	if (ret < 0) {
12831480 		netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n",
1284
-				__func__, ret);
1481
+			   __func__, ret);
1482
+		pm_runtime_put(priv->dev);
12851483 		return ret;
12861484 	}
12871485 
....@@ -1293,7 +1491,6 @@
12931491 
12941492 	return 0;
12951493 }
1296
-
12971494 
12981495 static const struct net_device_ops xcan_netdev_ops = {
12991496 	.ndo_open	= xcan_open,
....@@ -1406,6 +1603,8 @@
14061603 };
14071604 
14081605 static const struct xcan_devtype_data xcan_zynq_data = {
1606
+	.cantype = XZYNQ_CANPS,
1607
+	.flags = XCAN_FLAG_TXFEMP,
14091608 	.bittiming_const = &xcan_bittiming_const,
14101609 	.btr_ts2_shift = XCAN_BTR_TS2_SHIFT,
14111610 	.btr_sjw_shift = XCAN_BTR_SJW_SHIFT,
....@@ -1413,6 +1612,7 @@
14131612 };
14141613 
14151614 static const struct xcan_devtype_data xcan_axi_data = {
1615
+	.cantype = XAXI_CAN,
14161616 	.bittiming_const = &xcan_bittiming_const,
14171617 	.btr_ts2_shift = XCAN_BTR_TS2_SHIFT,
14181618 	.btr_sjw_shift = XCAN_BTR_SJW_SHIFT,
....@@ -1420,6 +1620,7 @@
14201620 };
14211621 
14221622 static const struct xcan_devtype_data xcan_canfd_data = {
1623
+	.cantype = XAXI_CANFD,
14231624 	.flags = XCAN_FLAG_EXT_FILTERS |
14241625 		 XCAN_FLAG_RXMNF |
14251626 		 XCAN_FLAG_TX_MAILBOXES |
....@@ -1430,11 +1631,25 @@
14301631 	.bus_clk_name = "s_axi_aclk",
14311632 };
14321633 
1634
+static const struct xcan_devtype_data xcan_canfd2_data = {
1635
+	.cantype = XAXI_CANFD_2_0,
1636
+	.flags = XCAN_FLAG_EXT_FILTERS |
1637
+		 XCAN_FLAG_RXMNF |
1638
+		 XCAN_FLAG_TX_MAILBOXES |
1639
+		 XCAN_FLAG_CANFD_2 |
1640
+		 XCAN_FLAG_RX_FIFO_MULTI,
1641
+	.bittiming_const = &xcan_bittiming_const_canfd2,
1642
+	.btr_ts2_shift = XCAN_BTR_TS2_SHIFT_CANFD,
1643
+	.btr_sjw_shift = XCAN_BTR_SJW_SHIFT_CANFD,
1644
+	.bus_clk_name = "s_axi_aclk",
1645
+};
1646
+
14331647 /* Match table for OF platform binding */
14341648 static const struct of_device_id xcan_of_match[] = {
14351649 	{ .compatible = "xlnx,zynq-can-1.0", .data = &xcan_zynq_data },
14361650 	{ .compatible = "xlnx,axi-can-1.00.a", .data = &xcan_axi_data },
14371651 	{ .compatible = "xlnx,canfd-1.0", .data = &xcan_canfd_data },
1652
+	{ .compatible = "xlnx,canfd-2.0", .data = &xcan_canfd2_data },
14381653 	{ /* end of list */ },
14391654 };
14401655 MODULE_DEVICE_TABLE(of, xcan_of_match);
....@@ -1450,7 +1665,6 @@
14501665  */
14511666 static int xcan_probe(struct platform_device *pdev)
14521667 {
1453
-	struct resource *res; /* IO mem resources */
14541668 	struct net_device *ndev;
14551669 	struct xcan_priv *priv;
14561670 	const struct of_device_id *of_id;
....@@ -1458,12 +1672,11 @@
14581672 	void __iomem *addr;
14591673 	int ret;
14601674 	int rx_max, tx_max;
1461
-	int hw_tx_max, hw_rx_max;
1675
+	u32 hw_tx_max = 0, hw_rx_max = 0;
14621676 	const char *hw_tx_max_property;
14631677 
14641678 	/* Get the virtual base address for the device */
1465
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1466
-	addr = devm_ioremap_resource(&pdev->dev, res);
1679
+	addr = devm_platform_ioremap_resource(pdev, 0);
14671680 	if (IS_ERR(addr)) {
14681681 		ret = PTR_ERR(addr);
14691682 		goto err;
....@@ -1512,7 +1725,7 @@
15121725 	 */
15131726 	if (!(devtype->flags & XCAN_FLAG_TX_MAILBOXES) &&
15141727 	    (devtype->flags & XCAN_FLAG_TXFEMP))
1515
-		tx_max = min(hw_tx_max, 2);
1728
+		tx_max = min(hw_tx_max, 2U);
15161729 	else
15171730 		tx_max = 1;
15181731 
....@@ -1530,6 +1743,19 @@
15301743 	priv->can.do_get_berr_counter = xcan_get_berr_counter;
15311744 	priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
15321745 					CAN_CTRLMODE_BERR_REPORTING;
1746
+
1747
+	if (devtype->cantype == XAXI_CANFD)
1748
+		priv->can.data_bittiming_const =
1749
+			&xcan_data_bittiming_const_canfd;
1750
+
1751
+	if (devtype->cantype == XAXI_CANFD_2_0)
1752
+		priv->can.data_bittiming_const =
1753
+			&xcan_data_bittiming_const_canfd2;
1754
+
1755
+	if (devtype->cantype == XAXI_CANFD ||
1756
+	    devtype->cantype == XAXI_CANFD_2_0)
1757
+		priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD;
1758
+
15331759 	priv->reg_base = addr;
15341760 	priv->tx_max = tx_max;
15351761 	priv->devtype = *devtype;
....@@ -1551,14 +1777,16 @@
15511777 	/* Getting the CAN can_clk info */
15521778 	priv->can_clk = devm_clk_get(&pdev->dev, "can_clk");
15531779 	if (IS_ERR(priv->can_clk)) {
1554
-		dev_err(&pdev->dev, "Device clock not found.\n");
1780
+		if (PTR_ERR(priv->can_clk) != -EPROBE_DEFER)
1781
+			dev_err(&pdev->dev, "Device clock not found.\n");
15551782 		ret = PTR_ERR(priv->can_clk);
15561783 		goto err_free;
15571784 	}
15581785 
15591786 	priv->bus_clk = devm_clk_get(&pdev->dev, devtype->bus_clk_name);
15601787 	if (IS_ERR(priv->bus_clk)) {
1561
-		dev_err(&pdev->dev, "bus clock not found\n");
1788
+		if (PTR_ERR(priv->bus_clk) != -EPROBE_DEFER)
1789
+			dev_err(&pdev->dev, "bus clock not found\n");
15621790 		ret = PTR_ERR(priv->bus_clk);
15631791 		goto err_free;
15641792 	}
....@@ -1570,8 +1798,8 @@
15701798 	ret = pm_runtime_get_sync(&pdev->dev);
15711799 	if (ret < 0) {
15721800 		netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n",
1573
-			__func__, ret);
1574
-		goto err_pmdisable;
1801
+			   __func__, ret);
1802
+		goto err_disableclks;
15751803 	}
15761804 
15771805 	if (priv->read_reg(priv, XCAN_SR_OFFSET) != XCAN_SR_CONFIG_MASK) {
....@@ -1593,6 +1821,11 @@
15931821 
15941822 	pm_runtime_put(&pdev->dev);
15951823 
1824
+	if (priv->devtype.flags & XCAN_FLAG_CANFD_2) {
1825
+		priv->write_reg(priv, XCAN_AFR_2_ID_OFFSET, 0x00000000);
1826
+		priv->write_reg(priv, XCAN_AFR_2_MASK_OFFSET, 0x00000000);
1827
+	}
1828
+
15961829 	netdev_dbg(ndev, "reg_base=0x%p irq=%d clock=%d, tx buffers: actual %d, using %d\n",
15971830 		   priv->reg_base, ndev->irq, priv->can.clock.freq,
15981831 		   hw_tx_max, priv->tx_max);
....@@ -1601,7 +1834,6 @@
16011834 
16021835 err_disableclks:
16031836 	pm_runtime_put(priv->dev);
1604
-err_pmdisable:
16051837 	pm_runtime_disable(&pdev->dev);
16061838 err_free:
16071839 	free_candev(ndev);