hc
2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c
kernel/drivers/mtd/spi-nor/core.c
....@@ -855,21 +855,22 @@
855855 ret = spi_nor_read_cr(nor, &sr_cr[1]);
856856 if (ret)
857857 return ret;
858
- } else if (nor->params->quad_enable) {
858
+ } else if (spi_nor_get_protocol_width(nor->read_proto) == 4 &&
859
+ spi_nor_get_protocol_width(nor->write_proto) == 4 &&
860
+ nor->params->quad_enable) {
859861 /*
860862 * If the Status Register 2 Read command (35h) is not
861863 * supported, we should at least be sure we don't
862864 * change the value of the SR2 Quad Enable bit.
863865 *
864
- * We can safely assume that when the Quad Enable method is
865
- * set, the value of the QE bit is one, as a consequence of the
866
- * nor->params->quad_enable() call.
866
+ * When the Quad Enable method is set and the buswidth is 4, we
867
+ * can safely assume that the value of the QE bit is one, as a
868
+ * consequence of the nor->params->quad_enable() call.
867869 *
868
- * We can safely assume that the Quad Enable bit is present in
869
- * the Status Register 2 at BIT(1). According to the JESD216
870
- * revB standard, BFPT DWORDS[15], bits 22:20, the 16-bit
871
- * Write Status (01h) command is available just for the cases
872
- * in which the QE bit is described in SR2 at BIT(1).
870
+ * According to the JESD216 revB standard, BFPT DWORDS[15],
871
+ * bits 22:20, the 16-bit Write Status (01h) command is
872
+ * available just for the cases in which the QE bit is
873
+ * described in SR2 at BIT(1).
873874 */
874875 sr_cr[1] = SR2_QUAD_EN_BIT1;
875876 } else {
....@@ -1314,6 +1315,8 @@
13141315 continue;
13151316
13161317 erase = &map->erase_type[i];
1318
+ if (!erase->size)
1319
+ continue;
13171320
13181321 /* Alignment is not mandatory for overlaid regions */
13191322 if (region->offset & SNOR_OVERLAID_REGION &&
....@@ -2566,6 +2569,15 @@
25662569 }
25672570
25682571 /**
2572
+ * spi_nor_mask_erase_type() - mask out a SPI NOR erase type
2573
+ * @erase: pointer to a structure that describes a SPI NOR erase type
2574
+ */
2575
+void spi_nor_mask_erase_type(struct spi_nor_erase_type *erase)
2576
+{
2577
+ erase->size = 0;
2578
+}
2579
+
2580
+/**
25692581 * spi_nor_init_uniform_erase_map() - Initialize uniform erase map
25702582 * @map: the erase map of the SPI NOR
25712583 * @erase_mask: bitmask encoding erase types that can erase the entire