add new system file

hc

2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/mmc/host/sdhci-esdhc-imx.c
..
..
@@ -103,6 +103,7 @@
103
103
 #define ESDHC_TUNING_START_TAP_DEFAULT	0x1
104
104
 #define ESDHC_TUNING_START_TAP_MASK	0x7f
105
105
 #define ESDHC_TUNING_CMD_CRC_CHECK_DISABLE	(1 << 7)
106
+#define ESDHC_TUNING_STEP_DEFAULT	0x1
106
107
 #define ESDHC_TUNING_STEP_MASK		0x00070000
107
108
 #define ESDHC_TUNING_STEP_SHIFT		16
108
109
 
..
..
@@ -165,8 +166,8 @@
165
166
 #define ESDHC_FLAG_HS400		BIT(9)
166
167
 /*
167
168
  * The IP has errata ERR010450
168
- * uSDHC: Due to the I/O timing limit, for SDR mode, SD card clock can't
169
- * exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz.
169
+ * uSDHC: At 1.8V due to the I/O timing limit, for SDR mode, SD card
170
+ * clock can't exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz.
170
171
  */
171
172
 #define ESDHC_FLAG_ERR010450		BIT(10)
172
173
 /* The IP supports HS400ES mode */
..
..
@@ -872,7 +873,8 @@
872
873
 		| ESDHC_CLOCK_MASK);
873
874
 	sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
874
875
 
875
-	if (imx_data->socdata->flags & ESDHC_FLAG_ERR010450) {
876
+	if ((imx_data->socdata->flags & ESDHC_FLAG_ERR010450) &&
877
+	    (!(host->quirks2 & SDHCI_QUIRK2_NO_1_8_V))) {
876
878
 		unsigned int max_clock;
877
879
 
878
880
 		max_clock = imx_data->is_ddr ? 45000000 : 150000000;
..
..
@@ -1300,7 +1302,7 @@
1300
1302
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1301
1303
 	struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1302
1304
 	struct cqhci_host *cq_host = host->mmc->cqe_private;
1303
-	int tmp;
1305
+	u32 tmp;
1304
1306
 
1305
1307
 	if (esdhc_is_usdhc(imx_data)) {
1306
1308
 		/*
..
..
@@ -1353,17 +1355,24 @@
1353
1355
 
1354
1356
 		if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1355
1357
 			tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1356
-			tmp |= ESDHC_STD_TUNING_EN |
1357
-				ESDHC_TUNING_START_TAP_DEFAULT;
1358
-			if (imx_data->boarddata.tuning_start_tap) {
1359
-				tmp &= ~ESDHC_TUNING_START_TAP_MASK;
1358
+			tmp |= ESDHC_STD_TUNING_EN;
1359
+
1360
+			/*
1361
+			 * ROM code or bootloader may config the start tap
1362
+			 * and step, unmask them first.
1363
+			 */
1364
+			tmp &= ~(ESDHC_TUNING_START_TAP_MASK | ESDHC_TUNING_STEP_MASK);
1365
+			if (imx_data->boarddata.tuning_start_tap)
1360
1366
 				tmp |= imx_data->boarddata.tuning_start_tap;
1361
-			}
1367
+			else
1368
+				tmp |= ESDHC_TUNING_START_TAP_DEFAULT;
1362
1369
 
1363
1370
 			if (imx_data->boarddata.tuning_step) {
1364
-				tmp &= ~ESDHC_TUNING_STEP_MASK;
1365
1371
 				tmp |= imx_data->boarddata.tuning_step
1366
1372
 					<< ESDHC_TUNING_STEP_SHIFT;
1373
+			} else {
1374
+				tmp |= ESDHC_TUNING_STEP_DEFAULT
1375
+					<< ESDHC_TUNING_STEP_SHIFT;
1367
1376
 			}
1368
1377
 
1369
1378
 			/* Disable the CMD CRC check for tuning, if not, need to