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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/misc/cardreader/rts5260.c
....@@ -1,19 +1,7 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /* Driver for Realtek PCI-Express card reader
23  *
34  * Copyright(c) 2016-2017 Realtek Semiconductor Corp. All rights reserved.
4
- *
5
- * This program is free software; you can redistribute it and/or modify it
6
- * under the terms of the GNU General Public License as published by the
7
- * Free Software Foundation; either version 2, or (at your option) any
8
- * later version.
9
- *
10
- * This program is distributed in the hope that it will be useful, but
11
- * WITHOUT ANY WARRANTY; without even the implied warranty of
12
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
13
- * General Public License for more details.
14
- *
15
- * You should have received a copy of the GNU General Public License along
16
- * with this program; if not, see <http://www.gnu.org/licenses/>.
175  *
186  * Author:
197  *   Steven FENG <steven_feng@realsil.com.cn>
....@@ -38,21 +26,17 @@
3826 
3927 static void rts5260_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
4028 {
41
-	u8 driving_3v3[6][3] = {
42
-		{0x94, 0x94, 0x94},
43
-		{0x11, 0x11, 0x18},
44
-		{0x55, 0x55, 0x5C},
45
-		{0x94, 0x94, 0x94},
46
-		{0x94, 0x94, 0x94},
47
-		{0xFF, 0xFF, 0xFF},
29
+	u8 driving_3v3[4][3] = {
30
+		{0x11, 0x11, 0x11},
31
+		{0x22, 0x22, 0x22},
32
+		{0x55, 0x55, 0x55},
33
+		{0x33, 0x33, 0x33},
4834 	};
49
-	u8 driving_1v8[6][3] = {
50
-		{0x9A, 0x89, 0x89},
51
-		{0xC4, 0xC4, 0xC4},
52
-		{0x3C, 0x3C, 0x3C},
35
+	u8 driving_1v8[4][3] = {
36
+		{0x35, 0x33, 0x33},
37
+		{0x8A, 0x88, 0x88},
38
+		{0xBD, 0xBB, 0xBB},
5339 		{0x9B, 0x99, 0x99},
54
-		{0x9A, 0x89, 0x89},
55
-		{0xFE, 0xFE, 0xFE},
5640 	};
5741 	u8 (*driving)[3], drive_sel;
5842 
....@@ -64,19 +48,22 @@
6448 		drive_sel = pcr->sd30_drive_sel_1v8;
6549 	}
6650 
67
-	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
51
+	rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL,
6852 			 0xFF, driving[drive_sel][0]);
69
-	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
53
+
54
+	rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
7055 			 0xFF, driving[drive_sel][1]);
71
-	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
56
+
57
+	rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL,
7258 			 0xFF, driving[drive_sel][2]);
7359 }
7460 
7561 static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
7662 {
63
+	struct pci_dev *pdev = pcr->pci;
7764 	u32 reg;
7865 
79
-	rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
66
+	pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg);
8067 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
8168 
8269 	if (!rtsx_vendor_setting_valid(reg)) {
....@@ -89,26 +76,13 @@
8976 	pcr->card_drive_sel &= 0x3F;
9077 	pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
9178 
92
-	rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &reg);
79
+	pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
9380 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
81
+	if (rtsx_check_mmc_support(reg))
82
+		pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
9483 	pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
9584 	if (rtsx_reg_check_reverse_socket(reg))
9685 		pcr->flags |= PCR_REVERSE_SOCKET;
97
-}
98
-
99
-static void rtsx_base_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
100
-{
101
-	/* Set relink_time to 0 */
102
-	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
103
-	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
104
-	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
105
-				RELINK_TIME_MASK, 0);
106
-
107
-	if (pm_state == HOST_ENTER_S3)
108
-		rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
109
-					D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
110
-
111
-	rtsx_pci_write_register(pcr, FPDCTL, ALL_POWER_DOWN, ALL_POWER_DOWN);
11286 }
11387 
11488 static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr)
....@@ -193,7 +167,7 @@
193167 		| SD_ASYNC_FIFO_NOT_RST, SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
194168 	rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
195169 	rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF,
196
-				CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
170
+			CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
197171 	rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
198172 
199173 	return 0;
....@@ -201,28 +175,21 @@
201175 
202176 static int rts5260_card_power_on(struct rtsx_pcr *pcr, int card)
203177 {
204
-	int err = 0;
205178 	struct rtsx_cr_option *option = &pcr->option;
206179 
207180 	if (option->ocp_en)
208181 		rtsx_pci_enable_ocp(pcr);
209182 
210
-	rtsx_pci_init_cmd(pcr);
211
-	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_CONFIG2,
212
-			 DV331812_VDD1, DV331812_VDD1);
213
-	err = rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF);
214
-	if (err < 0)
215
-		return err;
216183 
217
-	rtsx_pci_init_cmd(pcr);
218
-	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_VCC_CFG0,
184
+	rtsx_pci_write_register(pcr, LDO_CONFIG2, DV331812_VDD1, DV331812_VDD1);
185
+	rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
219186 			 RTS5260_DVCC_TUNE_MASK, RTS5260_DVCC_33);
220
-	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_VCC_CFG1,
221
-			 LDO_POW_SDVDD1_MASK, LDO_POW_SDVDD1_ON);
222
-	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_CONFIG2,
223
-			 DV331812_POWERON, DV331812_POWERON);
224
-	err = rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF);
225187 
188
+	rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_POW_SDVDD1_MASK,
189
+			LDO_POW_SDVDD1_ON);
190
+
191
+	rtsx_pci_write_register(pcr, LDO_CONFIG2,
192
+			 DV331812_POWERON, DV331812_POWERON);
226193 	msleep(20);
227194 
228195 	if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 ||
....@@ -242,12 +209,12 @@
242209 	/* Reset SD_CFG3 register */
243210 	rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0);
244211 	rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG,
245
-				SD30_CLK_STOP_CFG_EN | SD30_CLK_STOP_CFG1 |
246
-				SD30_CLK_STOP_CFG0, 0);
212
+			SD30_CLK_STOP_CFG_EN | SD30_CLK_STOP_CFG1 |
213
+			SD30_CLK_STOP_CFG0, 0);
247214 
248215 	rtsx_pci_write_register(pcr, REG_PRE_RW_MODE, EN_INFINITE_MODE, 0);
249216 
250
-	return err;
217
+	return 0;
251218 }
252219 
253220 static int rts5260_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
....@@ -273,9 +240,9 @@
273240 	}
274241 
275242 	/* set pad drive */
276
-	rtsx_pci_init_cmd(pcr);
277243 	rts5260_fill_driving(pcr, voltage);
278
-	return rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF);
244
+
245
+	return 0;
279246 }
280247 
281248 static void rts5260_stop_cmd(struct rtsx_pcr *pcr)
....@@ -290,13 +257,9 @@
290257 
291258 static void rts5260_card_before_power_off(struct rtsx_pcr *pcr)
292259 {
293
-	struct rtsx_cr_option *option = &pcr->option;
294
-
295260 	rts5260_stop_cmd(pcr);
296261 	rts5260_switch_output_voltage(pcr, OUTPUT_3V3);
297262 
298
-	if (option->ocp_en)
299
-		rtsx_pci_disable_ocp(pcr);
300263 }
301264 
302265 static int rts5260_card_power_off(struct rtsx_pcr *pcr, int card)
....@@ -304,13 +267,12 @@
304267 	int err = 0;
305268 
306269 	rts5260_card_before_power_off(pcr);
307
-
308
-	rtsx_pci_init_cmd(pcr);
309
-	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_VCC_CFG1,
270
+	err = rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
310271 			 LDO_POW_SDVDD1_MASK, LDO_POW_SDVDD1_OFF);
311
-	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_CONFIG2,
272
+	err = rtsx_pci_write_register(pcr, LDO_CONFIG2,
312273 			 DV331812_POWERON, DV331812_POWEROFF);
313
-	err = rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF);
274
+	if (pcr->option.ocp_en)
275
+		rtsx_pci_disable_ocp(pcr);
314276 
315277 	return err;
316278 }
....@@ -322,41 +284,29 @@
322284 	if (option->ocp_en) {
323285 		u8 mask, val;
324286 
287
+
288
+		rtsx_pci_write_register(pcr, RTS5260_DVCC_CTRL,
289
+				RTS5260_DVCC_OCP_THD_MASK,
290
+				option->sd_800mA_ocp_thd);
291
+
292
+		rtsx_pci_write_register(pcr, RTS5260_DV331812_CFG,
293
+				RTS5260_DV331812_OCP_THD_MASK,
294
+				RTS5260_DV331812_OCP_THD_270);
295
+
296
+		mask = SD_OCP_GLITCH_MASK;
297
+		val = pcr->hw_param.ocp_glitch;
298
+		rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val);
325299 		rtsx_pci_write_register(pcr, RTS5260_DVCC_CTRL,
326300 					RTS5260_DVCC_OCP_EN |
327301 					RTS5260_DVCC_OCP_CL_EN,
328302 					RTS5260_DVCC_OCP_EN |
329303 					RTS5260_DVCC_OCP_CL_EN);
330
-		rtsx_pci_write_register(pcr, RTS5260_DVIO_CTRL,
331
-					RTS5260_DVIO_OCP_EN |
332
-					RTS5260_DVIO_OCP_CL_EN,
333
-					RTS5260_DVIO_OCP_EN |
334
-					RTS5260_DVIO_OCP_CL_EN);
335
-
336
-		rtsx_pci_write_register(pcr, RTS5260_DVCC_CTRL,
337
-					RTS5260_DVCC_OCP_THD_MASK,
338
-					option->sd_400mA_ocp_thd);
339
-
340
-		rtsx_pci_write_register(pcr, RTS5260_DVIO_CTRL,
341
-					RTS5260_DVIO_OCP_THD_MASK,
342
-					RTS5260_DVIO_OCP_THD_350);
343
-
344
-		rtsx_pci_write_register(pcr, RTS5260_DV331812_CFG,
345
-					RTS5260_DV331812_OCP_THD_MASK,
346
-					RTS5260_DV331812_OCP_THD_210);
347
-
348
-		mask = SD_OCP_GLITCH_MASK | SDVIO_OCP_GLITCH_MASK;
349
-		val = pcr->hw_param.ocp_glitch;
350
-		rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val);
351304 
352305 		rtsx_pci_enable_ocp(pcr);
353306 	} else {
354307 		rtsx_pci_write_register(pcr, RTS5260_DVCC_CTRL,
355308 					RTS5260_DVCC_OCP_EN |
356309 					RTS5260_DVCC_OCP_CL_EN, 0);
357
-		rtsx_pci_write_register(pcr, RTS5260_DVIO_CTRL,
358
-					RTS5260_DVIO_OCP_EN |
359
-					RTS5260_DVIO_OCP_CL_EN, 0);
360310 	}
361311 }
362312 
....@@ -364,14 +314,9 @@
364314 {
365315 	u8 val = 0;
366316 
367
-	rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 0);
368
-
369317 	val = SD_OCP_INT_EN | SD_DETECT_EN;
370
-	val |= SDVIO_OCP_INT_EN | SDVIO_DETECT_EN;
371318 	rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
372
-	rtsx_pci_write_register(pcr, REG_DV3318_OCPCTL,
373
-				DV3318_DETECT_EN | DV3318_OCP_INT_EN,
374
-				DV3318_DETECT_EN | DV3318_OCP_INT_EN);
319
+
375320 }
376321 
377322 static void rts5260_disable_ocp(struct rtsx_pcr *pcr)
....@@ -379,14 +324,10 @@
379324 	u8 mask = 0;
380325 
381326 	mask = SD_OCP_INT_EN | SD_DETECT_EN;
382
-	mask |= SDVIO_OCP_INT_EN | SDVIO_DETECT_EN;
383327 	rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
384
-	rtsx_pci_write_register(pcr, REG_DV3318_OCPCTL,
385
-				DV3318_DETECT_EN | DV3318_OCP_INT_EN, 0);
386328 
387
-	rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN,
388
-				OC_POWER_DOWN);
389329 }
330
+
390331 
391332 static int rts5260_get_ocpstat(struct rtsx_pcr *pcr, u8 *val)
392333 {
....@@ -404,9 +345,7 @@
404345 	u8 val = 0;
405346 
406347 	mask = SD_OCP_INT_CLR | SD_OC_CLR;
407
-	mask |= SDVIO_OCP_INT_CLR | SDVIO_OC_CLR;
408348 	val = SD_OCP_INT_CLR | SD_OC_CLR;
409
-	val |= SDVIO_OCP_INT_CLR | SDVIO_OC_CLR;
410349 
411350 	rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
412351 	rtsx_pci_write_register(pcr, REG_DV3318_OCPCTL,
....@@ -425,35 +364,21 @@
425364 
426365 	rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
427366 	rts5260_get_ocpstat2(pcr, &pcr->ocp_stat2);
428
-	if (pcr->card_exist & SD_EXIST)
429
-		rtsx_sd_power_off_card3v3(pcr);
430
-	else if (pcr->card_exist & MS_EXIST)
431
-		rtsx_ms_power_off_card3v3(pcr);
432367 
433
-	if (!(pcr->card_exist & MS_EXIST) && !(pcr->card_exist & SD_EXIST)) {
434
-		if ((pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER |
435
-			SDVIO_OC_NOW | SDVIO_OC_EVER)) ||
436
-			(pcr->ocp_stat2 & (DV3318_OCP_NOW | DV3318_OCP_EVER)))
437
-			rtsx_pci_clear_ocpstat(pcr);
368
+	if ((pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) ||
369
+		(pcr->ocp_stat2 & (DV3318_OCP_NOW | DV3318_OCP_EVER))) {
370
+		rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
371
+		rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
372
+		rtsx_pci_clear_ocpstat(pcr);
438373 		pcr->ocp_stat = 0;
439374 		pcr->ocp_stat2 = 0;
440375 	}
441376 
442
-	if ((pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER |
443
-			SDVIO_OC_NOW | SDVIO_OC_EVER)) ||
444
-			(pcr->ocp_stat2 & (DV3318_OCP_NOW | DV3318_OCP_EVER))) {
445
-		if (pcr->card_exist & SD_EXIST)
446
-			rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
447
-		else if (pcr->card_exist & MS_EXIST)
448
-			rtsx_pci_write_register(pcr, CARD_OE, MS_OUTPUT_EN, 0);
449
-	}
450377 }
451378 
452379 static int rts5260_init_hw(struct rtsx_pcr *pcr)
453380 {
454381 	int err;
455
-
456
-	rtsx_pci_init_ocp(pcr);
457382 
458383 	rtsx_pci_init_cmd(pcr);
459384 
....@@ -483,6 +408,8 @@
483408 	if (err < 0)
484409 		return err;
485410 
411
+	rtsx_pci_init_ocp(pcr);
412
+
486413 	return 0;
487414 }
488415 
....@@ -495,10 +422,17 @@
495422 	lss_l1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN)
496423 			| rtsx_check_dev_flag(pcr, PM_L1_2_EN);
497424 
425
+	rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0);
498426 	if (lss_l1_2) {
499427 		pcr_dbg(pcr, "Set parameters for L1.2.");
500428 		rtsx_pci_write_register(pcr, PWR_GLOBAL_CTRL,
501429 					0xFF, PCIE_L1_2_EN);
430
+		rtsx_pci_write_register(pcr, RTS5260_DVCC_CTRL,
431
+					RTS5260_DVCC_OCP_EN |
432
+					RTS5260_DVCC_OCP_CL_EN,
433
+					RTS5260_DVCC_OCP_EN |
434
+					RTS5260_DVCC_OCP_CL_EN);
435
+
502436 		rtsx_pci_write_register(pcr, PWR_FE_CTL,
503437 					0xFF, PCIE_L1_2_PD_FE_EN);
504438 	} else if (lss_l1_1) {
....@@ -546,21 +480,27 @@
546480 
547481 static void rts5260_init_from_cfg(struct rtsx_pcr *pcr)
548482 {
483
+	struct pci_dev *pdev = pcr->pci;
484
+	int l1ss;
549485 	struct rtsx_cr_option *option = &pcr->option;
550486 	u32 lval;
551487 
552
-	rtsx_pci_read_config_dword(pcr, PCR_ASPM_SETTING_5260, &lval);
488
+	l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
489
+	if (!l1ss)
490
+		return;
553491 
554
-	if (lval & ASPM_L1_1_EN_MASK)
492
+	pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
493
+
494
+	if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
555495 		rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
556496 
557
-	if (lval & ASPM_L1_2_EN_MASK)
497
+	if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
558498 		rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
559499 
560
-	if (lval & PM_L1_1_EN_MASK)
500
+	if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
561501 		rtsx_set_dev_flag(pcr, PM_L1_1_EN);
562502 
563
-	if (lval & PM_L1_2_EN_MASK)
503
+	if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
564504 		rtsx_set_dev_flag(pcr, PM_L1_2_EN);
565505 
566506 	rts5260_pwr_saving_setting(pcr);
....@@ -568,7 +508,7 @@
568508 	if (option->ltr_en) {
569509 		u16 val;
570510 
571
-		pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val);
511
+		pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val);
572512 		if (val & PCI_EXP_DEVCTL2_LTR_EN) {
573513 			option->ltr_enabled = true;
574514 			option->ltr_active = true;
....@@ -611,37 +551,15 @@
611551 	 * to drive low, and we forcibly request clock.
612552 	 */
613553 	if (option->force_clkreq_0)
614
-		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
554
+		rtsx_pci_write_register(pcr, PETXCFG,
615555 				 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
616556 	else
617
-		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
557
+		rtsx_pci_write_register(pcr, PETXCFG,
618558 				 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
619559 
560
+	rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00);
561
+
620562 	return 0;
621
-}
622
-
623
-static void rts5260_set_aspm(struct rtsx_pcr *pcr, bool enable)
624
-{
625
-	struct rtsx_cr_option *option = &pcr->option;
626
-	u8 val = 0;
627
-
628
-	if (pcr->aspm_enabled == enable)
629
-		return;
630
-
631
-	if (option->dev_aspm_mode == DEV_ASPM_DYNAMIC) {
632
-		if (enable)
633
-			val = pcr->aspm_en;
634
-		rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
635
-					 ASPM_MASK_NEG, val);
636
-	} else if (option->dev_aspm_mode == DEV_ASPM_BACKDOOR) {
637
-		u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0;
638
-
639
-		if (!enable)
640
-			val = FORCE_ASPM_CTL0;
641
-		rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
642
-	}
643
-
644
-	pcr->aspm_enabled = enable;
645563 }
646564 
647565 static void rts5260_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
....@@ -687,9 +605,7 @@
687605 	.card_power_on = rts5260_card_power_on,
688606 	.card_power_off = rts5260_card_power_off,
689607 	.switch_output_voltage = rts5260_switch_output_voltage,
690
-	.force_power_down = rtsx_base_force_power_down,
691608 	.stop_cmd = rts5260_stop_cmd,
692
-	.set_aspm = rts5260_set_aspm,
693609 	.set_l1off_cfg_sub_d0 = rts5260_set_l1off_cfg_sub_d0,
694610 	.enable_ocp = rts5260_enable_ocp,
695611 	.disable_ocp = rts5260_disable_ocp,
....@@ -733,7 +649,6 @@
733649 	option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
734650 	option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
735651 	option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
736
-	option->dev_aspm_mode = DEV_ASPM_DYNAMIC;
737652 	option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
738653 	option->ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
739654 	option->ltr_l1off_snooze_sspwrgate =
....@@ -742,7 +657,7 @@
742657 	option->ocp_en = 1;
743658 	if (option->ocp_en)
744659 		hw_param->interrupt_en |= SD_OC_INT_EN;
745
-	hw_param->ocp_glitch = SD_OCP_GLITCH_10M | SDVIO_OCP_GLITCH_800U;
660
+	hw_param->ocp_glitch =  SD_OCP_GLITCH_100U | SDVIO_OCP_GLITCH_800U;
746661 	option->sd_400mA_ocp_thd = RTS5260_DVCC_OCP_THD_550;
747662 	option->sd_800mA_ocp_thd = RTS5260_DVCC_OCP_THD_970;
748663 }