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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/misc/cardreader/rts5249.c
..
..
@@ -1,19 +1,7 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
1
2
 /* Driver for Realtek PCI-Express card reader
2
3
  *
3
4
  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
4
- *
5
- * This program is free software; you can redistribute it and/or modify it
6
- * under the terms of the GNU General Public License as published by the
7
- * Free Software Foundation; either version 2, or (at your option) any
8
- * later version.
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- *
10
- * This program is distributed in the hope that it will be useful, but
11
- * WITHOUT ANY WARRANTY; without even the implied warranty of
12
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
13
- * General Public License for more details.
14
- *
15
- * You should have received a copy of the GNU General Public License along
16
- * with this program; if not, see <http://www.gnu.org/licenses/>.
17
5
  *
18
6
  * Author:
19
7
  *   Wei WANG <wei_wang@realsil.com.cn>
..
..
@@ -67,9 +55,10 @@
67
55
 
68
56
 static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
69
57
 {
58
+	struct pci_dev *pdev = pcr->pci;
70
59
 	u32 reg;
71
60
 
72
-	rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
61
+	pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg);
73
62
 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
74
63
 
75
64
 	if (!rtsx_vendor_setting_valid(reg)) {
..
..
@@ -82,55 +71,52 @@
82
71
 	pcr->card_drive_sel &= 0x3F;
83
72
 	pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
84
73
 
85
-	rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &reg);
74
+	pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
86
75
 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
76
+	if (rtsx_check_mmc_support(reg))
77
+		pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
87
78
 	pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
88
79
 	if (rtsx_reg_check_reverse_socket(reg))
89
80
 		pcr->flags |= PCR_REVERSE_SOCKET;
90
81
 }
91
82
 
92
-static void rtsx_base_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
93
-{
94
-	/* Set relink_time to 0 */
95
-	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0);
96
-	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0);
97
-	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
98
-
99
-	if (pm_state == HOST_ENTER_S3)
100
-		rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
101
-			D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
102
-
103
-	rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
104
-}
105
-
106
83
 static void rts5249_init_from_cfg(struct rtsx_pcr *pcr)
107
84
 {
85
+	struct pci_dev *pdev = pcr->pci;
86
+	int l1ss;
108
87
 	struct rtsx_cr_option *option = &(pcr->option);
109
88
 	u32 lval;
110
89
 
111
-	if (CHK_PCI_PID(pcr, PID_524A))
112
-		rtsx_pci_read_config_dword(pcr,
113
-			PCR_ASPM_SETTING_REG1, &lval);
114
-	else
115
-		rtsx_pci_read_config_dword(pcr,
116
-			PCR_ASPM_SETTING_REG2, &lval);
90
+	l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
91
+	if (!l1ss)
92
+		return;
117
93
 
118
-	if (lval & ASPM_L1_1_EN_MASK)
94
+	pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
95
+
96
+	if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
97
+		if (0 == (lval & 0x0F))
98
+			rtsx_pci_enable_oobs_polling(pcr);
99
+		else
100
+			rtsx_pci_disable_oobs_polling(pcr);
101
+	}
102
+
103
+
104
+	if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
119
105
 		rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
120
106
 
121
-	if (lval & ASPM_L1_2_EN_MASK)
107
+	if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
122
108
 		rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
123
109
 
124
-	if (lval & PM_L1_1_EN_MASK)
110
+	if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
125
111
 		rtsx_set_dev_flag(pcr, PM_L1_1_EN);
126
112
 
127
-	if (lval & PM_L1_2_EN_MASK)
113
+	if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
128
114
 		rtsx_set_dev_flag(pcr, PM_L1_2_EN);
129
115
 
130
116
 	if (option->ltr_en) {
131
117
 		u16 val;
132
118
 
133
-		pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val);
119
+		pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val);
134
120
 		if (val & PCI_EXP_DEVCTL2_LTR_EN) {
135
121
 			option->ltr_enabled = true;
136
122
 			option->ltr_active = true;
..
..
@@ -154,6 +140,112 @@
154
140
 	return 0;
155
141
 }
156
142
 
143
+static void rts52xa_save_content_from_efuse(struct rtsx_pcr *pcr)
144
+{
145
+	u8 cnt, sv;
146
+	u16 j = 0;
147
+	u8 tmp;
148
+	u8 val;
149
+	int i;
150
+
151
+	rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
152
+				REG_EFUSE_BYPASS | REG_EFUSE_POR, REG_EFUSE_POR);
153
+	udelay(1);
154
+
155
+	pcr_dbg(pcr, "Enable efuse por!");
156
+	pcr_dbg(pcr, "save efuse to autoload");
157
+
158
+	rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD, REG_EFUSE_ADD_MASK, 0x00);
159
+	rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL,
160
+				REG_EFUSE_ENABLE | REG_EFUSE_MODE, REG_EFUSE_ENABLE);
161
+	/* Wait transfer end */
162
+	for (j = 0; j < 1024; j++) {
163
+		rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp);
164
+		if ((tmp & 0x80) == 0)
165
+			break;
166
+	}
167
+	rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val);
168
+	cnt = val & 0x0F;
169
+	sv = val & 0x10;
170
+
171
+	if (sv) {
172
+		for (i = 0; i < 4; i++) {
173
+			rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD,
174
+				REG_EFUSE_ADD_MASK, 0x04 + i);
175
+			rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL,
176
+				REG_EFUSE_ENABLE | REG_EFUSE_MODE, REG_EFUSE_ENABLE);
177
+			/* Wait transfer end */
178
+			for (j = 0; j < 1024; j++) {
179
+				rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp);
180
+				if ((tmp & 0x80) == 0)
181
+					break;
182
+			}
183
+			rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val);
184
+			rtsx_pci_write_register(pcr, 0xFF04 + i, 0xFF, val);
185
+		}
186
+	} else {
187
+		rtsx_pci_write_register(pcr, 0xFF04, 0xFF, (u8)PCI_VID(pcr));
188
+		rtsx_pci_write_register(pcr, 0xFF05, 0xFF, (u8)(PCI_VID(pcr) >> 8));
189
+		rtsx_pci_write_register(pcr, 0xFF06, 0xFF, (u8)PCI_PID(pcr));
190
+		rtsx_pci_write_register(pcr, 0xFF07, 0xFF, (u8)(PCI_PID(pcr) >> 8));
191
+	}
192
+
193
+	for (i = 0; i < cnt * 4; i++) {
194
+		if (sv)
195
+			rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD,
196
+				REG_EFUSE_ADD_MASK, 0x08 + i);
197
+		else
198
+			rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD,
199
+				REG_EFUSE_ADD_MASK, 0x04 + i);
200
+		rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL,
201
+				REG_EFUSE_ENABLE | REG_EFUSE_MODE, REG_EFUSE_ENABLE);
202
+		/* Wait transfer end */
203
+		for (j = 0; j < 1024; j++) {
204
+			rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp);
205
+			if ((tmp & 0x80) == 0)
206
+				break;
207
+		}
208
+		rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val);
209
+		rtsx_pci_write_register(pcr, 0xFF08 + i, 0xFF, val);
210
+	}
211
+	rtsx_pci_write_register(pcr, 0xFF00, 0xFF, (cnt & 0x7F) | 0x80);
212
+	rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
213
+		REG_EFUSE_BYPASS | REG_EFUSE_POR, REG_EFUSE_BYPASS);
214
+	pcr_dbg(pcr, "Disable efuse por!");
215
+}
216
+
217
+static void rts52xa_save_content_to_autoload_space(struct rtsx_pcr *pcr)
218
+{
219
+	u8 val;
220
+
221
+	rtsx_pci_read_register(pcr, RESET_LOAD_REG, &val);
222
+	if (val & 0x02) {
223
+		rtsx_pci_read_register(pcr, RTS525A_BIOS_CFG, &val);
224
+		if (val & RTS525A_LOAD_BIOS_FLAG) {
225
+			rtsx_pci_write_register(pcr, RTS525A_BIOS_CFG,
226
+				RTS525A_LOAD_BIOS_FLAG, RTS525A_CLEAR_BIOS_FLAG);
227
+
228
+			rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
229
+				REG_EFUSE_POWER_MASK, REG_EFUSE_POWERON);
230
+
231
+			pcr_dbg(pcr, "Power ON efuse!");
232
+			mdelay(1);
233
+			rts52xa_save_content_from_efuse(pcr);
234
+		} else {
235
+			rtsx_pci_read_register(pcr, RTS524A_PME_FORCE_CTL, &val);
236
+			if (!(val & 0x08))
237
+				rts52xa_save_content_from_efuse(pcr);
238
+		}
239
+	} else {
240
+		pcr_dbg(pcr, "Load from autoload");
241
+		rtsx_pci_write_register(pcr, 0xFF00, 0xFF, 0x80);
242
+		rtsx_pci_write_register(pcr, 0xFF04, 0xFF, (u8)PCI_VID(pcr));
243
+		rtsx_pci_write_register(pcr, 0xFF05, 0xFF, (u8)(PCI_VID(pcr) >> 8));
244
+		rtsx_pci_write_register(pcr, 0xFF06, 0xFF, (u8)PCI_PID(pcr));
245
+		rtsx_pci_write_register(pcr, 0xFF07, 0xFF, (u8)(PCI_PID(pcr) >> 8));
246
+	}
247
+}
248
+
157
249
 static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
158
250
 {
159
251
 	struct rtsx_cr_option *option = &(pcr->option);
..
..
@@ -162,6 +254,9 @@
162
254
 	rts5249_init_from_hw(pcr);
163
255
 
164
256
 	rtsx_pci_init_cmd(pcr);
257
+
258
+	if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A))
259
+		rts52xa_save_content_to_autoload_space(pcr);
165
260
 
166
261
 	/* Rest L1SUB Config */
167
262
 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00);
..
..
@@ -181,18 +276,36 @@
181
276
 	else
182
277
 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);
183
278
 
279
+	rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF);
280
+
281
+	if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
282
+		rtsx_pci_write_register(pcr, REG_VREF, PWD_SUSPND_EN, PWD_SUSPND_EN);
283
+		rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 0x01, 0x00);
284
+		rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 0x30, 0x20);
285
+	} else {
286
+		rtsx_pci_write_register(pcr, PME_FORCE_CTL, 0xFF, 0x30);
287
+		rtsx_pci_write_register(pcr, PM_CTRL3, 0x01, 0x00);
288
+	}
289
+
184
290
 	/*
185
291
 	 * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
186
292
 	 * to drive low, and we forcibly request clock.
187
293
 	 */
188
294
 	if (option->force_clkreq_0)
189
-		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
295
+		rtsx_pci_write_register(pcr, PETXCFG,
190
296
 			FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
191
297
 	else
192
-		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
298
+		rtsx_pci_write_register(pcr, PETXCFG,
193
299
 			FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
194
300
 
195
-	return rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF);
301
+	rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00);
302
+	if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
303
+		rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
304
+				REG_EFUSE_POWER_MASK, REG_EFUSE_POWEROFF);
305
+		pcr_dbg(pcr, "Power OFF efuse!");
306
+	}
307
+
308
+	return 0;
196
309
 }
197
310
 
198
311
 static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
..
..
@@ -284,6 +397,10 @@
284
397
 static int rtsx_base_card_power_on(struct rtsx_pcr *pcr, int card)
285
398
 {
286
399
 	int err;
400
+	struct rtsx_cr_option *option = &pcr->option;
401
+
402
+	if (option->ocp_en)
403
+		rtsx_pci_enable_ocp(pcr);
287
404
 
288
405
 	rtsx_pci_init_cmd(pcr);
289
406
 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
..
..
@@ -306,12 +423,15 @@
306
423
 
307
424
 static int rtsx_base_card_power_off(struct rtsx_pcr *pcr, int card)
308
425
 {
309
-	rtsx_pci_init_cmd(pcr);
310
-	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
311
-			SD_POWER_MASK, SD_POWER_OFF);
312
-	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
313
-			LDO3318_PWR_MASK, 0x00);
314
-	return rtsx_pci_send_cmd(pcr, 100);
426
+	struct rtsx_cr_option *option = &pcr->option;
427
+
428
+	if (option->ocp_en)
429
+		rtsx_pci_disable_ocp(pcr);
430
+
431
+	rtsx_pci_write_register(pcr, CARD_PWR_CTL, SD_POWER_MASK, SD_POWER_OFF);
432
+
433
+	rtsx_pci_write_register(pcr, PWR_GATE_CTRL, LDO3318_PWR_MASK, 0x00);
434
+	return 0;
315
435
 }
316
436
 
317
437
 static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
..
..
@@ -352,31 +472,6 @@
352
472
 	return rtsx_pci_send_cmd(pcr, 100);
353
473
 }
354
474
 
355
-static void rts5249_set_aspm(struct rtsx_pcr *pcr, bool enable)
356
-{
357
-	struct rtsx_cr_option *option = &pcr->option;
358
-	u8 val = 0;
359
-
360
-	if (pcr->aspm_enabled == enable)
361
-		return;
362
-
363
-	if (option->dev_aspm_mode == DEV_ASPM_DYNAMIC) {
364
-		if (enable)
365
-			val = pcr->aspm_en;
366
-		rtsx_pci_update_cfg_byte(pcr,
367
-			pcr->pcie_cap + PCI_EXP_LNKCTL,
368
-			ASPM_MASK_NEG, val);
369
-	} else if (option->dev_aspm_mode == DEV_ASPM_BACKDOOR) {
370
-		u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0;
371
-
372
-		if (!enable)
373
-			val = FORCE_ASPM_CTL0;
374
-		rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
375
-	}
376
-
377
-	pcr->aspm_enabled = enable;
378
-}
379
-
380
475
 static const struct pcr_ops rts5249_pcr_ops = {
381
476
 	.fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
382
477
 	.extra_init_hw = rts5249_extra_init_hw,
..
..
@@ -388,8 +483,6 @@
388
483
 	.card_power_on = rtsx_base_card_power_on,
389
484
 	.card_power_off = rtsx_base_card_power_off,
390
485
 	.switch_output_voltage = rtsx_base_switch_output_voltage,
391
-	.force_power_down = rtsx_base_force_power_down,
392
-	.set_aspm = rts5249_set_aspm,
393
486
 };
394
487
 
395
488
 /* SD Pull Control Enable:
..
..
@@ -476,7 +569,6 @@
476
569
 	option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
477
570
 	option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
478
571
 	option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
479
-	option->dev_aspm_mode = DEV_ASPM_DYNAMIC;
480
572
 	option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
481
573
 	option->ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5249_DEF;
482
574
 	option->ltr_l1off_snooze_sspwrgate =
..
..
@@ -615,9 +707,7 @@
615
707
 	.card_power_on = rtsx_base_card_power_on,
616
708
 	.card_power_off = rtsx_base_card_power_off,
617
709
 	.switch_output_voltage = rtsx_base_switch_output_voltage,
618
-	.force_power_down = rtsx_base_force_power_down,
619
710
 	.set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0,
620
-	.set_aspm = rts5249_set_aspm,
621
711
 };
622
712
 
623
713
 void rts524a_init_params(struct rtsx_pcr *pcr)
..
..
@@ -630,6 +720,13 @@
630
720
 
631
721
 	pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
632
722
 	pcr->ops = &rts524a_pcr_ops;
723
+
724
+	pcr->option.ocp_en = 1;
725
+	if (pcr->option.ocp_en)
726
+		pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
727
+	pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
728
+	pcr->option.sd_800mA_ocp_thd = RTS524A_OCP_THD_800;
729
+
633
730
 }
634
731
 
635
732
 static int rts525a_card_power_on(struct rtsx_pcr *pcr, int card)
..
..
@@ -692,6 +789,8 @@
692
789
 {
693
790
 	rts5249_extra_init_hw(pcr);
694
791
 
792
+	rtsx_pci_write_register(pcr, RTS5250_CLK_CFG3, RTS525A_CFG_MEM_PD, RTS525A_CFG_MEM_PD);
793
+
695
794
 	rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
696
795
 	if (is_version(pcr, 0x525A, IC_VER_A)) {
697
796
 		rtsx_pci_write_register(pcr, L1SUB_CONFIG2,
..
..
@@ -724,9 +823,7 @@
724
823
 	.card_power_on = rts525a_card_power_on,
725
824
 	.card_power_off = rtsx_base_card_power_off,
726
825
 	.switch_output_voltage = rts525a_switch_output_voltage,
727
-	.force_power_down = rtsx_base_force_power_down,
728
826
 	.set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0,
729
-	.set_aspm = rts5249_set_aspm,
730
827
 };
731
828
 
732
829
 void rts525a_init_params(struct rtsx_pcr *pcr)
..
..
@@ -739,4 +836,10 @@
739
836
 
740
837
 	pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
741
838
 	pcr->ops = &rts525a_pcr_ops;
839
+
840
+	pcr->option.ocp_en = 1;
841
+	if (pcr->option.ocp_en)
842
+		pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
843
+	pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
844
+	pcr->option.sd_800mA_ocp_thd = RTS525A_OCP_THD_800;
742
845
 }