add new system file

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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/irqchip/qcom-pdc.c
..
..
@@ -1,24 +1,30 @@
1
1
 // SPDX-License-Identifier: GPL-2.0
2
2
 /*
3
- * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
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+ * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4
4
  */
5
5
 
6
6
 #include <linux/err.h>
7
7
 #include <linux/init.h>
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+#include <linux/interrupt.h>
8
9
 #include <linux/irq.h>
9
10
 #include <linux/irqchip.h>
10
11
 #include <linux/irqdomain.h>
11
12
 #include <linux/io.h>
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13
 #include <linux/kernel.h>
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+#include <linux/module.h>
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15
 #include <linux/of.h>
14
16
 #include <linux/of_address.h>
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17
 #include <linux/of_device.h>
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+#include <linux/of_irq.h>
19
+#include <linux/soc/qcom/irq.h>
16
20
 #include <linux/spinlock.h>
17
-#include <linux/platform_device.h>
18
21
 #include <linux/slab.h>
19
22
 #include <linux/types.h>
20
23
 
21
-#define PDC_MAX_IRQS		126
24
+#include <linux/qcom_scm.h>
25
+
26
+#define PDC_MAX_IRQS		168
27
+#define PDC_MAX_GPIO_IRQS	256
22
28
 
23
29
 #define CLEAR_INTR(reg, intr)	(reg & ~(1 << intr))
24
30
 #define ENABLE_INTR(reg, intr)	(reg | (1 << intr))
..
..
@@ -26,16 +32,28 @@
26
32
 #define IRQ_ENABLE_BANK		0x10
27
33
 #define IRQ_i_CFG		0x110
28
34
 
35
+#define PDC_NO_PARENT_IRQ	~0UL
36
+
29
37
 struct pdc_pin_region {
30
38
 	u32 pin_base;
31
39
 	u32 parent_base;
32
40
 	u32 cnt;
33
41
 };
34
42
 
43
+struct spi_cfg_regs {
44
+	union {
45
+		u64 start;
46
+		void __iomem *base;
47
+	};
48
+	resource_size_t size;
49
+	bool scm_io;
50
+};
51
+
35
52
 static DEFINE_RAW_SPINLOCK(pdc_lock);
36
53
 static void __iomem *pdc_base;
37
54
 static struct pdc_pin_region *pdc_region;
38
55
 static int pdc_region_cnt;
56
+static struct spi_cfg_regs *spi_cfg;
39
57
 
40
58
 static void pdc_reg_write(int reg, u32 i, u32 val)
41
59
 {
..
..
@@ -50,29 +68,81 @@
50
68
 static void pdc_enable_intr(struct irq_data *d, bool on)
51
69
 {
52
70
 	int pin_out = d->hwirq;
71
+	unsigned long flags;
53
72
 	u32 index, mask;
54
73
 	u32 enable;
55
74
 
56
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 	index = pin_out / 32;
57
76
 	mask = pin_out % 32;
58
77
 
59
-	raw_spin_lock(&pdc_lock);
78
+	raw_spin_lock_irqsave(&pdc_lock, flags);
60
79
 	enable = pdc_reg_read(IRQ_ENABLE_BANK, index);
61
80
 	enable = on ? ENABLE_INTR(enable, mask) : CLEAR_INTR(enable, mask);
62
81
 	pdc_reg_write(IRQ_ENABLE_BANK, index, enable);
63
-	raw_spin_unlock(&pdc_lock);
82
+	raw_spin_unlock_irqrestore(&pdc_lock, flags);
64
83
 }
65
84
 
66
-static void qcom_pdc_gic_mask(struct irq_data *d)
85
+static void qcom_pdc_gic_disable(struct irq_data *d)
67
86
 {
68
87
 	pdc_enable_intr(d, false);
69
-	irq_chip_mask_parent(d);
88
+	irq_chip_disable_parent(d);
70
89
 }
71
90
 
72
-static void qcom_pdc_gic_unmask(struct irq_data *d)
91
+static void qcom_pdc_gic_enable(struct irq_data *d)
73
92
 {
74
93
 	pdc_enable_intr(d, true);
75
-	irq_chip_unmask_parent(d);
94
+	irq_chip_enable_parent(d);
95
+}
96
+
97
+static u32 __spi_pin_read(unsigned int pin)
98
+{
99
+	void __iomem *cfg_reg = spi_cfg->base + pin * 4;
100
+	u64 scm_cfg_reg = spi_cfg->start + pin * 4;
101
+
102
+	if (spi_cfg->scm_io) {
103
+		unsigned int val;
104
+
105
+		qcom_scm_io_readl(scm_cfg_reg, &val);
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+		return val;
107
+	} else {
108
+		return readl(cfg_reg);
109
+	}
110
+}
111
+
112
+static void __spi_pin_write(unsigned int pin, unsigned int val)
113
+{
114
+	void __iomem *cfg_reg = spi_cfg->base + pin * 4;
115
+	u64 scm_cfg_reg = spi_cfg->start + pin * 4;
116
+
117
+	if (spi_cfg->scm_io)
118
+		qcom_scm_io_writel(scm_cfg_reg, val);
119
+	else
120
+		writel(val, cfg_reg);
121
+}
122
+
123
+static int spi_configure_type(irq_hw_number_t hwirq, unsigned int type)
124
+{
125
+	int spi = hwirq - 32;
126
+	u32 pin = spi / 32;
127
+	u32 mask = BIT(spi % 32);
128
+	u32 val;
129
+	unsigned long flags;
130
+
131
+	if (!spi_cfg)
132
+		return 0;
133
+
134
+	if (pin * 4 > spi_cfg->size)
135
+		return -EFAULT;
136
+
137
+	raw_spin_lock_irqsave(&pdc_lock, flags);
138
+	val = __spi_pin_read(pin);
139
+	val &= ~mask;
140
+	if (type & IRQ_TYPE_LEVEL_MASK)
141
+		val |= mask;
142
+	__spi_pin_write(pin, val);
143
+	raw_spin_unlock_irqrestore(&pdc_lock, flags);
144
+
145
+	return 0;
76
146
 }
77
147
 
78
148
 /*
..
..
@@ -111,8 +181,10 @@
111
181
  */
112
182
 static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type)
113
183
 {
114
-	int pin_out = d->hwirq;
184
+	int parent_hwirq = d->parent_data->hwirq;
115
185
 	enum pdc_irq_config_bits pdc_type;
186
+	enum pdc_irq_config_bits old_pdc_type;
187
+	int ret;
116
188
 
117
189
 	switch (type) {
118
190
 	case IRQ_TYPE_EDGE_RISING:
..
..
@@ -138,21 +210,48 @@
138
210
 		return -EINVAL;
139
211
 	}
140
212
 
141
-	pdc_reg_write(IRQ_i_CFG, pin_out, pdc_type);
213
+	old_pdc_type = pdc_reg_read(IRQ_i_CFG, d->hwirq);
214
+	pdc_reg_write(IRQ_i_CFG, d->hwirq, pdc_type);
142
215
 
143
-	return irq_chip_set_type_parent(d, type);
216
+	/* Additionally, configure (only) the GPIO in the f/w */
217
+	ret = spi_configure_type(parent_hwirq, type);
218
+	if (ret)
219
+		return ret;
220
+
221
+	ret = irq_chip_set_type_parent(d, type);
222
+	if (ret)
223
+		return ret;
224
+
225
+	/*
226
+	 * When we change types the PDC can give a phantom interrupt.
227
+	 * Clear it.  Specifically the phantom shows up when reconfiguring
228
+	 * polarity of interrupt without changing the state of the signal
229
+	 * but let's be consistent and clear it always.
230
+	 *
231
+	 * Doing this works because we have IRQCHIP_SET_TYPE_MASKED so the
232
+	 * interrupt will be cleared before the rest of the system sees it.
233
+	 */
234
+	if (old_pdc_type != pdc_type)
235
+		irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, false);
236
+
237
+	return 0;
144
238
 }
145
239
 
146
240
 static struct irq_chip qcom_pdc_gic_chip = {
147
241
 	.name			= "PDC",
148
242
 	.irq_eoi		= irq_chip_eoi_parent,
149
-	.irq_mask		= qcom_pdc_gic_mask,
150
-	.irq_unmask		= qcom_pdc_gic_unmask,
243
+	.irq_mask		= irq_chip_mask_parent,
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+	.irq_unmask		= irq_chip_unmask_parent,
245
+	.irq_disable		= qcom_pdc_gic_disable,
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+	.irq_enable		= qcom_pdc_gic_enable,
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+	.irq_get_irqchip_state	= irq_chip_get_parent_state,
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+	.irq_set_irqchip_state	= irq_chip_set_parent_state,
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249
 	.irq_retrigger		= irq_chip_retrigger_hierarchy,
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250
 	.irq_set_type		= qcom_pdc_gic_set_type,
153
251
 	.flags			= IRQCHIP_MASK_ON_SUSPEND |
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252
 				  IRQCHIP_SET_TYPE_MASKED |
155
-				  IRQCHIP_SKIP_SET_WAKE,
253
+				  IRQCHIP_SKIP_SET_WAKE |
254
+				  IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND,
156
255
 	.irq_set_vcpu_affinity	= irq_chip_set_vcpu_affinity_parent,
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256
 	.irq_set_affinity	= irq_chip_set_affinity_parent,
158
257
 };
..
..
@@ -169,8 +268,7 @@
169
268
 			return (region->parent_base + pin - region->pin_base);
170
269
 	}
171
270
 
172
-	WARN_ON(1);
173
-	return ~0UL;
271
+	return PDC_NO_PARENT_IRQ;
174
272
 }
175
273
 
176
274
 static int qcom_pdc_translate(struct irq_domain *d, struct irq_fwspec *fwspec,
..
..
@@ -199,16 +297,16 @@
199
297
 
200
298
 	ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type);
201
299
 	if (ret)
202
-		return -EINVAL;
203
-
204
-	parent_hwirq = get_parent_hwirq(hwirq);
205
-	if (parent_hwirq == ~0UL)
206
-		return -EINVAL;
300
+		return ret;
207
301
 
208
302
 	ret  = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
209
303
 					     &qcom_pdc_gic_chip, NULL);
210
304
 	if (ret)
211
305
 		return ret;
306
+
307
+	parent_hwirq = get_parent_hwirq(hwirq);
308
+	if (parent_hwirq == PDC_NO_PARENT_IRQ)
309
+		return irq_domain_disconnect_hierarchy(domain->parent, virq);
212
310
 
213
311
 	if (type & IRQ_TYPE_EDGE_BOTH)
214
312
 		type = IRQ_TYPE_EDGE_RISING;
..
..
@@ -232,9 +330,64 @@
232
330
 	.free		= irq_domain_free_irqs_common,
233
331
 };
234
332
 
333
+static int qcom_pdc_gpio_alloc(struct irq_domain *domain, unsigned int virq,
334
+			       unsigned int nr_irqs, void *data)
335
+{
336
+	struct irq_fwspec *fwspec = data;
337
+	struct irq_fwspec parent_fwspec;
338
+	irq_hw_number_t hwirq, parent_hwirq;
339
+	unsigned int type;
340
+	int ret;
341
+
342
+	ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type);
343
+	if (ret)
344
+		return ret;
345
+
346
+	if (hwirq == GPIO_NO_WAKE_IRQ)
347
+		return irq_domain_disconnect_hierarchy(domain, virq);
348
+
349
+	ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
350
+					    &qcom_pdc_gic_chip, NULL);
351
+	if (ret)
352
+		return ret;
353
+
354
+	parent_hwirq = get_parent_hwirq(hwirq);
355
+	if (parent_hwirq == PDC_NO_PARENT_IRQ)
356
+		return irq_domain_disconnect_hierarchy(domain->parent, virq);
357
+
358
+	if (type & IRQ_TYPE_EDGE_BOTH)
359
+		type = IRQ_TYPE_EDGE_RISING;
360
+
361
+	if (type & IRQ_TYPE_LEVEL_MASK)
362
+		type = IRQ_TYPE_LEVEL_HIGH;
363
+
364
+	parent_fwspec.fwnode      = domain->parent->fwnode;
365
+	parent_fwspec.param_count = 3;
366
+	parent_fwspec.param[0]    = 0;
367
+	parent_fwspec.param[1]    = parent_hwirq;
368
+	parent_fwspec.param[2]    = type;
369
+
370
+	return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
371
+					    &parent_fwspec);
372
+}
373
+
374
+static int qcom_pdc_gpio_domain_select(struct irq_domain *d,
375
+				       struct irq_fwspec *fwspec,
376
+				       enum irq_domain_bus_token bus_token)
377
+{
378
+	return bus_token == DOMAIN_BUS_WAKEUP;
379
+}
380
+
381
+static const struct irq_domain_ops qcom_pdc_gpio_ops = {
382
+	.select		= qcom_pdc_gpio_domain_select,
383
+	.alloc		= qcom_pdc_gpio_alloc,
384
+	.free		= irq_domain_free_irqs_common,
385
+};
386
+
235
387
 static int pdc_setup_pin_mapping(struct device_node *np)
236
388
 {
237
-	int ret, n;
389
+	int ret, n, i;
390
+	u32 irq_index, reg_index, val;
238
391
 
239
392
 	n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32));
240
393
 	if (n <= 0 || n % 3)
..
..
@@ -263,6 +416,14 @@
263
416
 						 &pdc_region[n].cnt);
264
417
 		if (ret)
265
418
 			return ret;
419
+
420
+		for (i = 0; i < pdc_region[n].cnt; i++) {
421
+			reg_index = (i + pdc_region[n].pin_base) >> 5;
422
+			irq_index = (i + pdc_region[n].pin_base) & 0x1f;
423
+			val = pdc_reg_read(IRQ_ENABLE_BANK, reg_index);
424
+			val &= ~BIT(irq_index);
425
+			pdc_reg_write(IRQ_ENABLE_BANK, reg_index, val);
426
+		}
266
427
 	}
267
428
 
268
429
 	return 0;
..
..
@@ -270,7 +431,8 @@
270
431
 
271
432
 static int qcom_pdc_init(struct device_node *node, struct device_node *parent)
272
433
 {
273
-	struct irq_domain *parent_domain, *pdc_domain;
434
+	struct irq_domain *parent_domain, *pdc_domain, *pdc_gpio_domain;
435
+	struct resource res;
274
436
 	int ret;
275
437
 
276
438
 	pdc_base = of_iomap(node, 0);
..
..
@@ -301,12 +463,73 @@
301
463
 		goto fail;
302
464
 	}
303
465
 
466
+	ret = of_address_to_resource(node, 1, &res);
467
+	if (!ret) {
468
+		spi_cfg = kcalloc(1, sizeof(*spi_cfg), GFP_KERNEL);
469
+		if (!spi_cfg) {
470
+			ret = -ENOMEM;
471
+			goto remove;
472
+		}
473
+		spi_cfg->scm_io = of_find_property(node,
474
+						   "qcom,scm-spi-cfg", NULL);
475
+		spi_cfg->size = resource_size(&res);
476
+		if (spi_cfg->scm_io) {
477
+			spi_cfg->start = res.start;
478
+		} else {
479
+			spi_cfg->base = ioremap(res.start, spi_cfg->size);
480
+			if (!spi_cfg->base) {
481
+				ret = -ENOMEM;
482
+				goto remove;
483
+			}
484
+		}
485
+	}
486
+
487
+	pdc_gpio_domain = irq_domain_create_hierarchy(parent_domain,
488
+					IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP,
489
+					PDC_MAX_GPIO_IRQS,
490
+					of_fwnode_handle(node),
491
+					&qcom_pdc_gpio_ops, NULL);
492
+	if (!pdc_gpio_domain) {
493
+		pr_err("%pOF: PDC domain add failed for GPIO domain\n", node);
494
+		ret = -ENOMEM;
495
+		goto remove;
496
+	}
497
+
498
+	irq_domain_update_bus_token(pdc_gpio_domain, DOMAIN_BUS_WAKEUP);
499
+
304
500
 	return 0;
305
501
 
502
+remove:
503
+	irq_domain_remove(pdc_domain);
504
+	kfree(spi_cfg);
306
505
 fail:
307
506
 	kfree(pdc_region);
308
507
 	iounmap(pdc_base);
309
508
 	return ret;
310
509
 }
311
510
 
312
-IRQCHIP_DECLARE(pdc_sdm845, "qcom,sdm845-pdc", qcom_pdc_init);
511
+static int qcom_pdc_probe(struct platform_device *pdev)
512
+{
513
+	struct device_node *np = pdev->dev.of_node;
514
+	struct device_node *parent = of_irq_find_parent(np);
515
+
516
+	return qcom_pdc_init(np, parent);
517
+}
518
+
519
+static const struct of_device_id qcom_pdc_match_table[] = {
520
+	{ .compatible = "qcom,pdc" },
521
+	{}
522
+};
523
+MODULE_DEVICE_TABLE(of, qcom_pdc_match_table);
524
+
525
+static struct platform_driver qcom_pdc_driver = {
526
+	.probe = qcom_pdc_probe,
527
+	.driver = {
528
+		.name = "qcom-pdc",
529
+		.of_match_table = qcom_pdc_match_table,
530
+		.suppress_bind_attrs = true,
531
+	},
532
+};
533
+module_platform_driver(qcom_pdc_driver);
534
+MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Power Domain Controller");
535
+MODULE_LICENSE("GPL v2");