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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/irqchip/irq-sni-exiu.c
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..
@@ -1,15 +1,12 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Driver for Socionext External Interrupt Unit (EXIU)
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  *
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- * Copyright (c) 2017 Linaro, Ltd. <ard.biesheuvel@linaro.org>
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+ * Copyright (c) 2017-2019 Linaro, Ltd. <ard.biesheuvel@linaro.org>
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  *
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  * Based on irq-tegra.c:
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  *   Copyright (C) 2011 Google, Inc.
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  *   Copyright (C) 2010,2013, NVIDIA Corporation
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  */
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11
 
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 #include <linux/interrupt.h>
..
..
@@ -20,6 +17,7 @@
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 #include <linux/of.h>
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 #include <linux/of_address.h>
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 #include <linux/of_irq.h>
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+#include <linux/platform_device.h>
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21
 
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 #include <dt-bindings/interrupt-controller/arm-gic.h>
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23
 
..
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@@ -39,11 +37,26 @@
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 	u32		spi_base;
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 };
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39
 
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-static void exiu_irq_eoi(struct irq_data *d)
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+static void exiu_irq_ack(struct irq_data *d)
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 {
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 	struct exiu_irq_data *data = irq_data_get_irq_chip_data(d);
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 	writel(BIT(d->hwirq), data->base + EIREQCLR);
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+}
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+
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+static void exiu_irq_eoi(struct irq_data *d)
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+{
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+	struct exiu_irq_data *data = irq_data_get_irq_chip_data(d);
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+
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+	/*
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+	 * Level triggered interrupts are latched and must be cleared during
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+	 * EOI or the interrupt will be jammed on. Of course if a level
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+	 * triggered interrupt is still asserted then the write will not clear
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+	 * the interrupt.
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+	 */
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+	if (irqd_is_level_type(d))
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+		writel(BIT(d->hwirq), data->base + EIREQCLR);
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+
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 	irq_chip_eoi_parent(d);
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 }
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..
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@@ -93,10 +106,13 @@
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 	writel_relaxed(val, data->base + EILVL);
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 	val = readl_relaxed(data->base + EIEDG);
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-	if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
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+	if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH) {
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 		val &= ~BIT(d->hwirq);
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-	else
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+		irq_set_handler_locked(d, handle_fasteoi_irq);
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+	} else {
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 		val |= BIT(d->hwirq);
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+		irq_set_handler_locked(d, handle_fasteoi_ack_irq);
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+	}
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 	writel_relaxed(val, data->base + EIEDG);
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 	writel_relaxed(BIT(d->hwirq), data->base + EIREQCLR);
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@@ -106,6 +122,7 @@
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122
 
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 static struct irq_chip exiu_irq_chip = {
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 	.name			= "EXIU",
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+	.irq_ack		= exiu_irq_ack,
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 	.irq_eoi		= exiu_irq_eoi,
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 	.irq_enable		= exiu_irq_enable,
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 	.irq_mask		= exiu_irq_mask,
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@@ -134,9 +151,13 @@
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 		*hwirq = fwspec->param[1] - info->spi_base;
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 		*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
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-		return 0;
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+	} else {
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+		if (fwspec->param_count != 2)
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+			return -EINVAL;
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+		*hwirq = fwspec->param[0];
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+		*type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
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 	}
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-	return -EINVAL;
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+	return 0;
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 }
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 static int exiu_domain_alloc(struct irq_domain *dom, unsigned int virq,
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@@ -147,16 +168,21 @@
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 	struct exiu_irq_data *info = dom->host_data;
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 	irq_hw_number_t hwirq;
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170
 
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-	if (fwspec->param_count != 3)
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-		return -EINVAL;	/* Not GIC compliant */
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-	if (fwspec->param[0] != GIC_SPI)
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-		return -EINVAL;	/* No PPI should point to this domain */
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+	parent_fwspec = *fwspec;
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+	if (is_of_node(dom->parent->fwnode)) {
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+		if (fwspec->param_count != 3)
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+			return -EINVAL;	/* Not GIC compliant */
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+		if (fwspec->param[0] != GIC_SPI)
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+			return -EINVAL;	/* No PPI should point to this domain */
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+		hwirq = fwspec->param[1] - info->spi_base;
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+	} else {
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+		hwirq = fwspec->param[0];
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+		parent_fwspec.param[0] = hwirq + info->spi_base + 32;
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+	}
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 	WARN_ON(nr_irqs != 1);
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-	hwirq = fwspec->param[1] - info->spi_base;
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 	irq_domain_set_hwirq_and_chip(dom, virq, hwirq, &exiu_irq_chip, info);
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-	parent_fwspec = *fwspec;
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 	parent_fwspec.fwnode = dom->parent->fwnode;
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 	return irq_domain_alloc_irqs_parent(dom, virq, nr_irqs, &parent_fwspec);
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 }
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@@ -167,12 +193,45 @@
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 	.free		= irq_domain_free_irqs_common,
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 };
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-static int __init exiu_init(struct device_node *node,
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-			    struct device_node *parent)
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+static struct exiu_irq_data *exiu_init(const struct fwnode_handle *fwnode,
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+				       struct resource *res)
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+{
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+	struct exiu_irq_data *data;
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+	int err;
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+
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+	data = kzalloc(sizeof(*data), GFP_KERNEL);
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+	if (!data)
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+		return ERR_PTR(-ENOMEM);
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+
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+	if (fwnode_property_read_u32_array(fwnode, "socionext,spi-base",
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+					   &data->spi_base, 1)) {
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+		err = -ENODEV;
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+		goto out_free;
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+	}
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+
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+	data->base = ioremap(res->start, resource_size(res));
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+	if (!data->base) {
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+		err = -ENODEV;
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+		goto out_free;
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+	}
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+
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+	/* clear and mask all interrupts */
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+	writel_relaxed(0xFFFFFFFF, data->base + EIREQCLR);
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+	writel_relaxed(0xFFFFFFFF, data->base + EIMASK);
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+
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+	return data;
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+
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+out_free:
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+	kfree(data);
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+	return ERR_PTR(err);
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+}
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+
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+static int __init exiu_dt_init(struct device_node *node,
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+			       struct device_node *parent)
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 {
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 	struct irq_domain *parent_domain, *domain;
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 	struct exiu_irq_data *data;
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-	int err;
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+	struct resource res;
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 	if (!parent) {
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 		pr_err("%pOF: no parent, giving up\n", node);
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@@ -185,31 +244,19 @@
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 		return -ENXIO;
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 	}
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-	data = kzalloc(sizeof(*data), GFP_KERNEL);
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-	if (!data)
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-		return -ENOMEM;
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-
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-	if (of_property_read_u32(node, "socionext,spi-base", &data->spi_base)) {
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-		pr_err("%pOF: failed to parse 'spi-base' property\n", node);
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-		err = -ENODEV;
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-		goto out_free;
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+	if (of_address_to_resource(node, 0, &res)) {
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+		pr_err("%pOF: failed to parse memory resource\n", node);
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+		return -ENXIO;
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 	}
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-	data->base = of_iomap(node, 0);
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-	if (!data->base) {
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-		err = -ENODEV;
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-		goto out_free;
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-	}
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-
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-	/* clear and mask all interrupts */
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-	writel_relaxed(0xFFFFFFFF, data->base + EIREQCLR);
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-	writel_relaxed(0xFFFFFFFF, data->base + EIMASK);
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+	data = exiu_init(of_node_to_fwnode(node), &res);
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+	if (IS_ERR(data))
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+		return PTR_ERR(data);
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 	domain = irq_domain_add_hierarchy(parent_domain, 0, NUM_IRQS, node,
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 					  &exiu_domain_ops, data);
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 	if (!domain) {
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 		pr_err("%pOF: failed to allocate domain\n", node);
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-		err = -ENOMEM;
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 		goto out_unmap;
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 	}
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..
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@@ -220,8 +267,57 @@
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 out_unmap:
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 	iounmap(data->base);
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-out_free:
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 	kfree(data);
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-	return err;
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+	return -ENOMEM;
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 }
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-IRQCHIP_DECLARE(exiu, "socionext,synquacer-exiu", exiu_init);
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+IRQCHIP_DECLARE(exiu, "socionext,synquacer-exiu", exiu_dt_init);
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+
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+#ifdef CONFIG_ACPI
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+static int exiu_acpi_probe(struct platform_device *pdev)
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+{
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+	struct irq_domain *domain;
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+	struct exiu_irq_data *data;
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+	struct resource *res;
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+
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+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+	if (!res) {
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+		dev_err(&pdev->dev, "failed to parse memory resource\n");
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+		return -ENXIO;
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+	}
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+
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+	data = exiu_init(dev_fwnode(&pdev->dev), res);
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+	if (IS_ERR(data))
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+		return PTR_ERR(data);
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+
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+	domain = acpi_irq_create_hierarchy(0, NUM_IRQS, dev_fwnode(&pdev->dev),
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+					   &exiu_domain_ops, data);
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+	if (!domain) {
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+		dev_err(&pdev->dev, "failed to create IRQ domain\n");
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+		goto out_unmap;
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+	}
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+
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+	dev_info(&pdev->dev, "%d interrupts forwarded\n", NUM_IRQS);
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+
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+	return 0;
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+
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+out_unmap:
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+	iounmap(data->base);
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+	kfree(data);
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+	return -ENOMEM;
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+}
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+
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+static const struct acpi_device_id exiu_acpi_ids[] = {
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+	{ "SCX0008" },
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+	{ /* sentinel */ }
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+};
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+MODULE_DEVICE_TABLE(acpi, exiu_acpi_ids);
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+
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+static struct platform_driver exiu_driver = {
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+	.driver = {
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+		.name = "exiu",
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+		.acpi_match_table = exiu_acpi_ids,
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+	},
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+	.probe = exiu_acpi_probe,
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+};
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+builtin_platform_driver(exiu_driver);
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+#endif