add new system file

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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/irqchip/irq-mmp.c
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  *  linux/arch/arm/mach-mmp/irq.c
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  *
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@@ -6,16 +7,13 @@
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  *
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  *  Author:	Bin Yang <bin.yang@marvell.com>
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  *              Haojian Zhuang <haojian.zhuang@gmail.com>
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- *
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- *  This program is free software; you can redistribute it and/or modify
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- *  it under the terms of the GNU General Public License version 2 as
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- *  published by the Free Software Foundation.
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  */
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 #include <linux/module.h>
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 #include <linux/init.h>
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 #include <linux/irq.h>
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 #include <linux/irqchip.h>
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+#include <linux/irqchip/chained_irq.h>
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 #include <linux/irqdomain.h>
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 #include <linux/io.h>
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 #include <linux/ioport.h>
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@@ -46,6 +44,7 @@
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 	unsigned int		conf_enable;
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 	unsigned int		conf_disable;
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 	unsigned int		conf_mask;
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+	unsigned int		conf2_mask;
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 	unsigned int		clr_mfp_irq_base;
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 	unsigned int		clr_mfp_hwirq;
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 	struct irq_domain	*domain;
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@@ -55,9 +54,11 @@
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 	unsigned int	conf_enable;
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 	unsigned int	conf_disable;
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 	unsigned int	conf_mask;
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+	unsigned int	conf2_mask;
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 };
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 static void __iomem *mmp_icu_base;
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+static void __iomem *mmp_icu2_base;
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 static struct icu_chip_data icu_data[MAX_ICU_NR];
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 static int max_icu_nr;
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@@ -100,6 +101,16 @@
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 		r &= ~data->conf_mask;
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 		r |= data->conf_disable;
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 		writel_relaxed(r, mmp_icu_base + (hwirq << 2));
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+
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+		if (data->conf2_mask) {
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+			/*
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+			 * ICU1 (above) only controls PJ4 MP1; if using SMP,
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+			 * we need to also mask the MP2 and MM cores via ICU2.
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+			 */
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+			r = readl_relaxed(mmp_icu2_base + (hwirq << 2));
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+			r &= ~data->conf2_mask;
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+			writel_relaxed(r, mmp_icu2_base + (hwirq << 2));
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+		}
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 	} else {
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 		r = readl_relaxed(data->reg_mask) | (1 << hwirq);
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 		writel_relaxed(r, data->reg_mask);
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@@ -135,10 +146,13 @@
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 static void icu_mux_irq_demux(struct irq_desc *desc)
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 {
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 	unsigned int irq = irq_desc_get_irq(desc);
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+	struct irq_chip *chip = irq_desc_get_chip(desc);
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 	struct irq_domain *domain;
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 	struct icu_chip_data *data;
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 	int i;
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 	unsigned long mask, status, n;
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+
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+	chained_irq_enter(chip, desc);
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 	for (i = 1; i < max_icu_nr; i++) {
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 		if (irq == icu_data[i].cascade_irq) {
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@@ -149,7 +163,7 @@
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 	}
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 	if (i >= max_icu_nr) {
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 		pr_err("Spurious irq %d in MMP INTC\n", irq);
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-		return;
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+		goto out;
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 	}
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 	mask = readl_relaxed(data->reg_mask);
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@@ -161,6 +175,9 @@
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 			generic_handle_irq(icu_data[i].virq_base + n);
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 		}
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 	}
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+
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+out:
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+	chained_irq_exit(chip, desc);
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 }
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 static int mmp_irq_domain_map(struct irq_domain *d, unsigned int irq,
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@@ -179,7 +196,7 @@
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 	return 0;
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 }
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-const struct irq_domain_ops mmp_irq_domain_ops = {
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+static const struct irq_domain_ops mmp_irq_domain_ops = {
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 	.map		= mmp_irq_domain_map,
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 	.xlate		= mmp_irq_domain_xlate,
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 };
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@@ -195,6 +212,14 @@
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 	.conf_disable	= 0x0,
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 	.conf_mask	= MMP2_ICU_INT_ROUTE_PJ4_IRQ |
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 			  MMP2_ICU_INT_ROUTE_PJ4_FIQ,
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+};
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+
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+static struct mmp_intc_conf mmp3_conf = {
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+	.conf_enable	= 0x20,
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+	.conf_disable	= 0x0,
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+	.conf_mask	= MMP2_ICU_INT_ROUTE_PJ4_IRQ |
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+			  MMP2_ICU_INT_ROUTE_PJ4_FIQ,
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+	.conf2_mask	= 0xf0,
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 };
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 static void __exception_irq_entry mmp_handle_irq(struct pt_regs *regs)
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@@ -398,7 +423,6 @@
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 	icu_data[0].conf_enable = mmp_conf.conf_enable;
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 	icu_data[0].conf_disable = mmp_conf.conf_disable;
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 	icu_data[0].conf_mask = mmp_conf.conf_mask;
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-	irq_set_default_host(icu_data[0].domain);
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 	set_handle_irq(mmp_handle_irq);
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 	max_icu_nr = 1;
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 	return 0;
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@@ -417,19 +441,50 @@
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 	icu_data[0].conf_enable = mmp2_conf.conf_enable;
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 	icu_data[0].conf_disable = mmp2_conf.conf_disable;
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 	icu_data[0].conf_mask = mmp2_conf.conf_mask;
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-	irq_set_default_host(icu_data[0].domain);
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 	set_handle_irq(mmp2_handle_irq);
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 	max_icu_nr = 1;
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 	return 0;
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 }
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 IRQCHIP_DECLARE(mmp2_intc, "mrvl,mmp2-intc", mmp2_of_init);
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+static int __init mmp3_of_init(struct device_node *node,
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+			       struct device_node *parent)
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+{
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+	int ret;
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+
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+	mmp_icu2_base = of_iomap(node, 1);
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+	if (!mmp_icu2_base) {
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+		pr_err("Failed to get interrupt controller register #2\n");
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+		return -ENODEV;
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+	}
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+
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+	ret = mmp_init_bases(node);
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+	if (ret < 0) {
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+		iounmap(mmp_icu2_base);
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+		return ret;
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+	}
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+
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+	icu_data[0].conf_enable = mmp3_conf.conf_enable;
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+	icu_data[0].conf_disable = mmp3_conf.conf_disable;
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+	icu_data[0].conf_mask = mmp3_conf.conf_mask;
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+	icu_data[0].conf2_mask = mmp3_conf.conf2_mask;
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+
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+	if (!parent) {
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+		/* This is the main interrupt controller. */
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+		set_handle_irq(mmp2_handle_irq);
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+	}
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+
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+	max_icu_nr = 1;
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+	return 0;
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+}
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+IRQCHIP_DECLARE(mmp3_intc, "marvell,mmp3-intc", mmp3_of_init);
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+
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 static int __init mmp2_mux_of_init(struct device_node *node,
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 				   struct device_node *parent)
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 {
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-	struct resource res;
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 	int i, ret, irq, j = 0;
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 	u32 nr_irqs, mfp_irq;
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+	u32 reg[4];
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 	if (!parent)
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 		return -ENODEV;
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@@ -441,18 +496,22 @@
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 		pr_err("Not found mrvl,intc-nr-irqs property\n");
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 		return -EINVAL;
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 	}
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-	ret = of_address_to_resource(node, 0, &res);
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+
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+	/*
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+	 * For historical reasons, the "regs" property of the
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+	 * mrvl,mmp2-mux-intc is not a regular "regs" property containing
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+	 * addresses on the parent bus, but offsets from the intc's base.
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+	 * That is why we can't use of_address_to_resource() here.
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+	 */
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+	ret = of_property_read_variable_u32_array(node, "reg", reg,
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+						  ARRAY_SIZE(reg),
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+						  ARRAY_SIZE(reg));
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 	if (ret < 0) {
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 		pr_err("Not found reg property\n");
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 		return -EINVAL;
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 	}
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-	icu_data[i].reg_status = mmp_icu_base + res.start;
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-	ret = of_address_to_resource(node, 1, &res);
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-	if (ret < 0) {
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-		pr_err("Not found reg property\n");
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-		return -EINVAL;
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-	}
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-	icu_data[i].reg_mask = mmp_icu_base + res.start;
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+	icu_data[i].reg_status = mmp_icu_base + reg[0];
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+	icu_data[i].reg_mask = mmp_icu_base + reg[2];
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 	icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0);
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 	if (!icu_data[i].cascade_irq)
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 		return -EINVAL;