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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/irqchip/irq-mips-gic.c
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@@ -46,17 +46,19 @@
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46
 
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 void __iomem *mips_gic_base;
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48
 
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-DEFINE_PER_CPU_READ_MOSTLY(unsigned long[GIC_MAX_LONGS], pcpu_masks);
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+static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[GIC_MAX_LONGS], pcpu_masks);
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50
 
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-static DEFINE_SPINLOCK(gic_lock);
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+static DEFINE_RAW_SPINLOCK(gic_lock);
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 static struct irq_domain *gic_irq_domain;
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-static struct irq_domain *gic_ipi_domain;
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 static int gic_shared_intrs;
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 static unsigned int gic_cpu_pin;
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 static unsigned int timer_cpu_pin;
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 static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller;
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+
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+#ifdef CONFIG_GENERIC_IRQ_IPI
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 static DECLARE_BITMAP(ipi_resrv, GIC_MAX_INTRS);
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 static DECLARE_BITMAP(ipi_available, GIC_MAX_INTRS);
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+#endif /* CONFIG_GENERIC_IRQ_IPI */
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62
 
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 static struct gic_all_vpes_chip_data {
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 	u32	map;
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@@ -207,7 +209,7 @@
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 	irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
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-	spin_lock_irqsave(&gic_lock, flags);
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+	raw_spin_lock_irqsave(&gic_lock, flags);
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 	switch (type & IRQ_TYPE_SENSE_MASK) {
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 	case IRQ_TYPE_EDGE_FALLING:
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 		pol = GIC_POL_FALLING_EDGE;
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@@ -247,7 +249,7 @@
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 	else
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 		irq_set_chip_handler_name_locked(d, &gic_level_irq_controller,
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 						 handle_level_irq, NULL);
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-	spin_unlock_irqrestore(&gic_lock, flags);
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+	raw_spin_unlock_irqrestore(&gic_lock, flags);
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 	return 0;
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 }
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@@ -265,7 +267,7 @@
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 		return -EINVAL;
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 	/* Assumption : cpumask refers to a single CPU */
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-	spin_lock_irqsave(&gic_lock, flags);
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+	raw_spin_lock_irqsave(&gic_lock, flags);
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 	/* Re-route this IRQ */
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 	write_gic_map_vp(irq, BIT(mips_cm_vp_id(cpu)));
..
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@@ -276,7 +278,7 @@
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 		set_bit(irq, per_cpu_ptr(pcpu_masks, cpu));
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 	irq_data_update_effective_affinity(d, cpumask_of(cpu));
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-	spin_unlock_irqrestore(&gic_lock, flags);
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+	raw_spin_unlock_irqrestore(&gic_lock, flags);
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 	return IRQ_SET_MASK_OK;
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 }
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@@ -354,12 +356,12 @@
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 	cd = irq_data_get_irq_chip_data(d);
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 	cd->mask = false;
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-	spin_lock_irqsave(&gic_lock, flags);
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+	raw_spin_lock_irqsave(&gic_lock, flags);
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 	for_each_online_cpu(cpu) {
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 		write_gic_vl_other(mips_cm_vp_id(cpu));
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 		write_gic_vo_rmask(BIT(intr));
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 	}
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-	spin_unlock_irqrestore(&gic_lock, flags);
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+	raw_spin_unlock_irqrestore(&gic_lock, flags);
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 }
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 static void gic_unmask_local_irq_all_vpes(struct irq_data *d)
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@@ -372,32 +374,43 @@
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 	cd = irq_data_get_irq_chip_data(d);
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 	cd->mask = true;
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-	spin_lock_irqsave(&gic_lock, flags);
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+	raw_spin_lock_irqsave(&gic_lock, flags);
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 	for_each_online_cpu(cpu) {
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 		write_gic_vl_other(mips_cm_vp_id(cpu));
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 		write_gic_vo_smask(BIT(intr));
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 	}
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-	spin_unlock_irqrestore(&gic_lock, flags);
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+	raw_spin_unlock_irqrestore(&gic_lock, flags);
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 }
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-static void gic_all_vpes_irq_cpu_online(struct irq_data *d)
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+static void gic_all_vpes_irq_cpu_online(void)
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 {
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-	struct gic_all_vpes_chip_data *cd;
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-	unsigned int intr;
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+	static const unsigned int local_intrs[] = {
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+		GIC_LOCAL_INT_TIMER,
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+		GIC_LOCAL_INT_PERFCTR,
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+		GIC_LOCAL_INT_FDC,
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+	};
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+	unsigned long flags;
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+	int i;
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394
 
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-	intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
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-	cd = irq_data_get_irq_chip_data(d);
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+	raw_spin_lock_irqsave(&gic_lock, flags);
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-	write_gic_vl_map(mips_gic_vx_map_reg(intr), cd->map);
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-	if (cd->mask)
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-		write_gic_vl_smask(BIT(intr));
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+	for (i = 0; i < ARRAY_SIZE(local_intrs); i++) {
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+		unsigned int intr = local_intrs[i];
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+		struct gic_all_vpes_chip_data *cd;
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+
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+		cd = &gic_all_vpes_chip_data[intr];
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+		write_gic_vl_map(mips_gic_vx_map_reg(intr), cd->map);
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+		if (cd->mask)
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+			write_gic_vl_smask(BIT(intr));
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+	}
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+
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+	raw_spin_unlock_irqrestore(&gic_lock, flags);
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 }
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 static struct irq_chip gic_all_vpes_local_irq_controller = {
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 	.name			= "MIPS GIC Local",
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 	.irq_mask		= gic_mask_local_irq_all_vpes,
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 	.irq_unmask		= gic_unmask_local_irq_all_vpes,
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-	.irq_cpu_online		= gic_all_vpes_irq_cpu_online,
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 };
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 static void __gic_irq_dispatch(void)
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@@ -421,11 +434,11 @@
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 	data = irq_get_irq_data(virq);
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-	spin_lock_irqsave(&gic_lock, flags);
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+	raw_spin_lock_irqsave(&gic_lock, flags);
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 	write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin);
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 	write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu)));
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 	irq_data_update_effective_affinity(data, cpumask_of(cpu));
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-	spin_unlock_irqrestore(&gic_lock, flags);
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+	raw_spin_unlock_irqrestore(&gic_lock, flags);
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 	return 0;
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 }
..
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@@ -459,9 +472,11 @@
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 	u32 map;
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 	if (hwirq >= GIC_SHARED_HWIRQ_BASE) {
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+#ifdef CONFIG_GENERIC_IRQ_IPI
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 		/* verify that shared irqs don't conflict with an IPI irq */
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 		if (test_bit(GIC_HWIRQ_TO_SHARED(hwirq), ipi_resrv))
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 			return -EBUSY;
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+#endif /* CONFIG_GENERIC_IRQ_IPI */
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 		err = irq_domain_set_hwirq_and_chip(d, virq, hwirq,
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 						    &gic_level_irq_controller,
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@@ -476,11 +491,15 @@
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 	intr = GIC_HWIRQ_TO_LOCAL(hwirq);
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 	map = GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin;
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+	/*
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+	 * If adding support for more per-cpu interrupts, keep the the
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+	 * array in gic_all_vpes_irq_cpu_online() in sync.
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+	 */
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 	switch (intr) {
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 	case GIC_LOCAL_INT_TIMER:
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 		/* CONFIG_MIPS_CMP workaround (see __gic_init) */
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 		map = GIC_MAP_PIN_MAP_TO_PIN | timer_cpu_pin;
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-		/* fall-through */
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+		fallthrough;
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 	case GIC_LOCAL_INT_PERFCTR:
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 	case GIC_LOCAL_INT_FDC:
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 		/*
..
..
@@ -514,12 +533,12 @@
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 	if (!gic_local_irq_is_routable(intr))
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 		return -EPERM;
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-	spin_lock_irqsave(&gic_lock, flags);
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+	raw_spin_lock_irqsave(&gic_lock, flags);
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 	for_each_online_cpu(cpu) {
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 		write_gic_vl_other(mips_cm_vp_id(cpu));
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 		write_gic_vo_map(mips_gic_vx_map_reg(intr), map);
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 	}
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-	spin_unlock_irqrestore(&gic_lock, flags);
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+	raw_spin_unlock_irqrestore(&gic_lock, flags);
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 	return 0;
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 }
..
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@@ -549,6 +568,8 @@
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 	.free = gic_irq_domain_free,
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 	.map = gic_irq_domain_map,
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 };
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+
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+#ifdef CONFIG_GENERIC_IRQ_IPI
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573
 
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 static int gic_ipi_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
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 				const u32 *intspec, unsigned int intsize,
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@@ -617,8 +638,8 @@
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 	return ret;
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 }
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640
 
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-void gic_ipi_domain_free(struct irq_domain *d, unsigned int virq,
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-			 unsigned int nr_irqs)
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+static void gic_ipi_domain_free(struct irq_domain *d, unsigned int virq,
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+				unsigned int nr_irqs)
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 {
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 	irq_hw_number_t base_hwirq;
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 	struct irq_data *data;
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@@ -631,8 +652,8 @@
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 	bitmap_set(ipi_available, base_hwirq, nr_irqs);
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 }
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-int gic_ipi_domain_match(struct irq_domain *d, struct device_node *node,
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-			 enum irq_domain_bus_token bus_token)
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+static int gic_ipi_domain_match(struct irq_domain *d, struct device_node *node,
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+				enum irq_domain_bus_token bus_token)
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 {
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 	bool is_ipi;
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@@ -653,6 +674,48 @@
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 	.match = gic_ipi_domain_match,
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 };
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+static int gic_register_ipi_domain(struct device_node *node)
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+{
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+	struct irq_domain *gic_ipi_domain;
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+	unsigned int v[2], num_ipis;
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+
682
+	gic_ipi_domain = irq_domain_add_hierarchy(gic_irq_domain,
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+						  IRQ_DOMAIN_FLAG_IPI_PER_CPU,
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+						  GIC_NUM_LOCAL_INTRS + gic_shared_intrs,
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+						  node, &gic_ipi_domain_ops, NULL);
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+	if (!gic_ipi_domain) {
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+		pr_err("Failed to add IPI domain");
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+		return -ENXIO;
689
+	}
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+
691
+	irq_domain_update_bus_token(gic_ipi_domain, DOMAIN_BUS_IPI);
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+
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+	if (node &&
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+	    !of_property_read_u32_array(node, "mti,reserved-ipi-vectors", v, 2)) {
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+		bitmap_set(ipi_resrv, v[0], v[1]);
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+	} else {
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+		/*
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+		 * Reserve 2 interrupts per possible CPU/VP for use as IPIs,
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+		 * meeting the requirements of arch/mips SMP.
700
+		 */
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+		num_ipis = 2 * num_possible_cpus();
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+		bitmap_set(ipi_resrv, gic_shared_intrs - num_ipis, num_ipis);
703
+	}
704
+
705
+	bitmap_copy(ipi_available, ipi_resrv, GIC_MAX_INTRS);
706
+
707
+	return 0;
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+}
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+
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+#else /* !CONFIG_GENERIC_IRQ_IPI */
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+
712
+static inline int gic_register_ipi_domain(struct device_node *node)
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+{
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+	return 0;
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+}
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+
717
+#endif /* !CONFIG_GENERIC_IRQ_IPI */
718
+
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 static int gic_cpu_startup(unsigned int cpu)
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 {
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 	/* Enable or disable EIC */
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@@ -662,8 +725,8 @@
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 	/* Clear all local IRQ masks (ie. disable all local interrupts) */
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 	write_gic_vl_rmask(~0);
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-	/* Invoke irq_cpu_online callbacks to enable desired interrupts */
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-	irq_cpu_online();
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+	/* Enable desired interrupts */
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+	gic_all_vpes_irq_cpu_online();
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730
 
668
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 	return 0;
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 }
..
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@@ -671,11 +734,12 @@
671
734
 static int __init gic_of_init(struct device_node *node,
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735
 			      struct device_node *parent)
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 {
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-	unsigned int cpu_vec, i, gicconfig, v[2], num_ipis;
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+	unsigned int cpu_vec, i, gicconfig;
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738
 	unsigned long reserved;
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 	phys_addr_t gic_base;
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 	struct resource res;
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 	size_t gic_len;
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+	int ret;
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743
 
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 	/* Find the first available CPU vector. */
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 	i = 0;
..
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@@ -716,7 +780,11 @@
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 		__sync();
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 	}
718
782
 
719
-	mips_gic_base = ioremap_nocache(gic_base, gic_len);
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+	mips_gic_base = ioremap(gic_base, gic_len);
784
+	if (!mips_gic_base) {
785
+		pr_err("Failed to ioremap gic_base\n");
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+		return -ENOMEM;
787
+	}
720
788
 
721
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 	gicconfig = read_gic_config();
722
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 	gic_shared_intrs = gicconfig & GIC_CONFIG_NUMINTERRUPTS;
..
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@@ -764,30 +832,9 @@
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 		return -ENXIO;
765
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 	}
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834
 
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-	gic_ipi_domain = irq_domain_add_hierarchy(gic_irq_domain,
768
-						  IRQ_DOMAIN_FLAG_IPI_PER_CPU,
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-						  GIC_NUM_LOCAL_INTRS + gic_shared_intrs,
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-						  node, &gic_ipi_domain_ops, NULL);
771
-	if (!gic_ipi_domain) {
772
-		pr_err("Failed to add IPI domain");
773
-		return -ENXIO;
774
-	}
775
-
776
-	irq_domain_update_bus_token(gic_ipi_domain, DOMAIN_BUS_IPI);
777
-
778
-	if (node &&
779
-	    !of_property_read_u32_array(node, "mti,reserved-ipi-vectors", v, 2)) {
780
-		bitmap_set(ipi_resrv, v[0], v[1]);
781
-	} else {
782
-		/*
783
-		 * Reserve 2 interrupts per possible CPU/VP for use as IPIs,
784
-		 * meeting the requirements of arch/mips SMP.
785
-		 */
786
-		num_ipis = 2 * num_possible_cpus();
787
-		bitmap_set(ipi_resrv, gic_shared_intrs - num_ipis, num_ipis);
788
-	}
789
-
790
-	bitmap_copy(ipi_available, ipi_resrv, GIC_MAX_INTRS);
835
+	ret = gic_register_ipi_domain(node);
836
+	if (ret)
837
+		return ret;
791
838
 
792
839
 	board_bind_eic_interrupt = &gic_bind_eic_interrupt;
793
840