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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/irqchip/irq-imx-gpcv2.c
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@@ -1,9 +1,6 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (C) 2015 Freescale Semiconductor, Inc.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  */
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5
 
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 #include <linux/of_address.h>
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@@ -17,6 +14,9 @@
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14
 
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 #define GPC_IMR1_CORE0		0x30
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 #define GPC_IMR1_CORE1		0x40
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+#define GPC_IMR1_CORE2		0x1c0
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+#define GPC_IMR1_CORE3		0x1d0
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+
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 struct gpcv2_irqchip_data {
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 	struct raw_spinlock	rlock;
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@@ -27,6 +27,11 @@
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 };
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 static struct gpcv2_irqchip_data *imx_gpcv2_instance;
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+
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+static void __iomem *gpcv2_idx_to_reg(struct gpcv2_irqchip_data *cd, int i)
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+{
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+	return cd->gpc_base + cd->cpu2wakeup + i * 4;
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+}
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 static int gpcv2_wakeup_source_save(void)
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 {
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@@ -39,7 +44,7 @@
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 		return 0;
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 	for (i = 0; i < IMR_NUM; i++) {
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-		reg = cd->gpc_base + cd->cpu2wakeup + i * 4;
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+		reg = gpcv2_idx_to_reg(cd, i);
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 		cd->saved_irq_mask[i] = readl_relaxed(reg);
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 		writel_relaxed(cd->wakeup_sources[i], reg);
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 	}
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@@ -50,17 +55,14 @@
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 static void gpcv2_wakeup_source_restore(void)
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 {
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 	struct gpcv2_irqchip_data *cd;
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-	void __iomem *reg;
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 	int i;
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 	cd = imx_gpcv2_instance;
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 	if (!cd)
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 		return;
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-	for (i = 0; i < IMR_NUM; i++) {
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-		reg = cd->gpc_base + cd->cpu2wakeup + i * 4;
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-		writel_relaxed(cd->saved_irq_mask[i], reg);
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-	}
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+	for (i = 0; i < IMR_NUM; i++)
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+		writel_relaxed(cd->saved_irq_mask[i], gpcv2_idx_to_reg(cd, i));
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 }
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 static struct syscore_ops imx_gpcv2_syscore_ops = {
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@@ -73,12 +75,10 @@
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 	struct gpcv2_irqchip_data *cd = d->chip_data;
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 	unsigned int idx = d->hwirq / 32;
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 	unsigned long flags;
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-	void __iomem *reg;
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 	u32 mask, val;
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 	raw_spin_lock_irqsave(&cd->rlock, flags);
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-	reg = cd->gpc_base + cd->cpu2wakeup + idx * 4;
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-	mask = 1 << d->hwirq % 32;
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+	mask = BIT(d->hwirq % 32);
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 	val = cd->wakeup_sources[idx];
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 	cd->wakeup_sources[idx] = on ? (val & ~mask) : (val | mask);
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@@ -99,9 +99,9 @@
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 	u32 val;
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 	raw_spin_lock(&cd->rlock);
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-	reg = cd->gpc_base + cd->cpu2wakeup + d->hwirq / 32 * 4;
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+	reg = gpcv2_idx_to_reg(cd, d->hwirq / 32);
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 	val = readl_relaxed(reg);
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-	val &= ~(1 << d->hwirq % 32);
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+	val &= ~BIT(d->hwirq % 32);
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 	writel_relaxed(val, reg);
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 	raw_spin_unlock(&cd->rlock);
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@@ -115,9 +115,9 @@
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 	u32 val;
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 	raw_spin_lock(&cd->rlock);
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-	reg = cd->gpc_base + cd->cpu2wakeup + d->hwirq / 32 * 4;
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+	reg = gpcv2_idx_to_reg(cd, d->hwirq / 32);
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 	val = readl_relaxed(reg);
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-	val |= 1 << (d->hwirq % 32);
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+	val |= BIT(d->hwirq % 32);
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 	writel_relaxed(val, reg);
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 	raw_spin_unlock(&cd->rlock);
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@@ -193,17 +193,33 @@
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 	.free		= irq_domain_free_irqs_common,
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 };
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+static const struct of_device_id gpcv2_of_match[] = {
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+	{ .compatible = "fsl,imx7d-gpc",  .data = (const void *) 2 },
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+	{ .compatible = "fsl,imx8mq-gpc", .data = (const void *) 4 },
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+	{ /* END */ }
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+};
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+
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 static int __init imx_gpcv2_irqchip_init(struct device_node *node,
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 			       struct device_node *parent)
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 {
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 	struct irq_domain *parent_domain, *domain;
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 	struct gpcv2_irqchip_data *cd;
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+	const struct of_device_id *id;
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+	unsigned long core_num;
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 	int i;
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 	if (!parent) {
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 		pr_err("%pOF: no parent, giving up\n", node);
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 		return -ENODEV;
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 	}
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+
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+	id = of_match_node(gpcv2_of_match, node);
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+	if (!id) {
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+		pr_err("%pOF: unknown compatibility string\n", node);
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+		return -ENODEV;
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+	}
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+
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+	core_num = (unsigned long)id->data;
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 	parent_domain = irq_find_host(parent);
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 	if (!parent_domain) {
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@@ -213,7 +229,7 @@
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 	cd = kzalloc(sizeof(struct gpcv2_irqchip_data), GFP_KERNEL);
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 	if (!cd) {
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-		pr_err("kzalloc failed!\n");
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+		pr_err("%pOF: kzalloc failed!\n", node);
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 		return -ENOMEM;
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 	}
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@@ -221,7 +237,7 @@
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 	cd->gpc_base = of_iomap(node, 0);
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 	if (!cd->gpc_base) {
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-		pr_err("fsl-gpcv2: unable to map gpc registers\n");
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+		pr_err("%pOF: unable to map gpc registers\n", node);
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 		kfree(cd);
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 		return -ENOMEM;
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 	}
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@@ -237,8 +253,17 @@
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 	/* Initially mask all interrupts */
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 	for (i = 0; i < IMR_NUM; i++) {
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-		writel_relaxed(~0, cd->gpc_base + GPC_IMR1_CORE0 + i * 4);
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-		writel_relaxed(~0, cd->gpc_base + GPC_IMR1_CORE1 + i * 4);
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+		void __iomem *reg = cd->gpc_base + i * 4;
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+
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+		switch (core_num) {
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+		case 4:
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+			writel_relaxed(~0, reg + GPC_IMR1_CORE2);
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+			writel_relaxed(~0, reg + GPC_IMR1_CORE3);
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+			fallthrough;
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+		case 2:
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+			writel_relaxed(~0, reg + GPC_IMR1_CORE0);
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+			writel_relaxed(~0, reg + GPC_IMR1_CORE1);
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+		}
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 		cd->wakeup_sources[i] = ~0;
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 	}
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@@ -263,4 +288,5 @@
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 	return 0;
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 }
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-IRQCHIP_DECLARE(imx_gpcv2, "fsl,imx7d-gpc", imx_gpcv2_irqchip_init);
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+IRQCHIP_DECLARE(imx_gpcv2_imx7d, "fsl,imx7d-gpc", imx_gpcv2_irqchip_init);
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+IRQCHIP_DECLARE(imx_gpcv2_imx8mq, "fsl,imx8mq-gpc", imx_gpcv2_irqchip_init);