add new system file

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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/irqchip/irq-hip04.c
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@@ -1,13 +1,10 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Hisilicon HiP04 INTC
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  *
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  * Copyright (C) 2002-2014 ARM Limited.
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  * Copyright (c) 2013-2014 Hisilicon Ltd.
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  * Copyright (c) 2013-2014 Linaro Ltd.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  *
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  * Interrupt architecture for the HIP04 INTC:
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  *
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@@ -133,7 +130,12 @@
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 	raw_spin_lock(&irq_controller_lock);
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-	ret = gic_configure_irq(irq, type, base, NULL);
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+	ret = gic_configure_irq(irq, type, base + GIC_DIST_CONFIG, NULL);
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+	if (ret && irq < 32) {
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+		/* Misconfigured PPIs are usually not fatal */
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+		pr_warn("GIC: PPI%d is secure or misconfigured\n", irq - 16);
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+		ret = 0;
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+	}
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 	raw_spin_unlock(&irq_controller_lock);
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@@ -169,6 +171,29 @@
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 	return IRQ_SET_MASK_OK;
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 }
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+
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+static void hip04_ipi_send_mask(struct irq_data *d, const struct cpumask *mask)
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+{
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+	int cpu;
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+	unsigned long flags, map = 0;
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+
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+	raw_spin_lock_irqsave(&irq_controller_lock, flags);
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+
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+	/* Convert our logical CPU mask into a physical one. */
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+	for_each_cpu(cpu, mask)
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+		map |= hip04_cpu_map[cpu];
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+
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+	/*
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+	 * Ensure that stores to Normal memory are visible to the
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+	 * other CPUs before they observe us issuing the IPI.
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+	 */
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+	dmb(ishst);
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+
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+	/* this always happens on GIC0 */
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+	writel_relaxed(map << 8 | d->hwirq, hip04_data.dist_base + GIC_DIST_SOFTINT);
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+
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+	raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
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+}
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 #endif
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 static void __exception_irq_entry hip04_handle_irq(struct pt_regs *regs)
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@@ -180,19 +205,9 @@
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 		irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
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 		irqnr = irqstat & GICC_IAR_INT_ID_MASK;
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-		if (likely(irqnr > 15 && irqnr <= HIP04_MAX_IRQS)) {
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+		if (irqnr <= HIP04_MAX_IRQS)
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 			handle_domain_irq(hip04_data.domain, irqnr, regs);
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-			continue;
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-		}
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-		if (irqnr < 16) {
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-			writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
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-#ifdef CONFIG_SMP
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-			handle_IPI(irqnr, regs);
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-#endif
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-			continue;
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-		}
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-		break;
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-	} while (1);
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+	} while (irqnr > HIP04_MAX_IRQS);
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 }
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 static struct irq_chip hip04_irq_chip = {
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@@ -203,6 +218,7 @@
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 	.irq_set_type		= hip04_irq_set_type,
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 #ifdef CONFIG_SMP
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 	.irq_set_affinity	= hip04_irq_set_affinity,
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+	.ipi_send_mask		= hip04_ipi_send_mask,
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 #endif
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 	.flags			= IRQCHIP_SET_TYPE_MASKED |
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 				  IRQCHIP_SKIP_SET_WAKE |
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@@ -271,45 +287,23 @@
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 		if (i != cpu)
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 			hip04_cpu_map[i] &= ~cpu_mask;
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-	gic_cpu_config(dist_base, NULL);
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+	gic_cpu_config(dist_base, 32, NULL);
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 	writel_relaxed(0xf0, base + GIC_CPU_PRIMASK);
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 	writel_relaxed(1, base + GIC_CPU_CTRL);
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 }
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-#ifdef CONFIG_SMP
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-static void hip04_raise_softirq(const struct cpumask *mask, unsigned int irq)
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-{
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-	int cpu;
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-	unsigned long flags, map = 0;
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-
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-	raw_spin_lock_irqsave(&irq_controller_lock, flags);
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-
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-	/* Convert our logical CPU mask into a physical one. */
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-	for_each_cpu(cpu, mask)
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-		map |= hip04_cpu_map[cpu];
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-
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-	/*
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-	 * Ensure that stores to Normal memory are visible to the
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-	 * other CPUs before they observe us issuing the IPI.
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-	 */
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-	dmb(ishst);
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-
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-	/* this always happens on GIC0 */
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-	writel_relaxed(map << 8 | irq, hip04_data.dist_base + GIC_DIST_SOFTINT);
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-
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-	raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
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-}
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-#endif
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-
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 static int hip04_irq_domain_map(struct irq_domain *d, unsigned int irq,
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 				irq_hw_number_t hw)
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 {
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-	if (hw < 32) {
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+	if (hw < 16) {
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+		irq_set_percpu_devid(irq);
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+		irq_set_chip_and_handler(irq, &hip04_irq_chip,
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+					 handle_percpu_devid_fasteoi_ipi);
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+	} else if (hw < 32) {
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 		irq_set_percpu_devid(irq);
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 		irq_set_chip_and_handler(irq, &hip04_irq_chip,
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 					 handle_percpu_devid_irq);
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-		irq_set_status_flags(irq, IRQ_NOAUTOEN);
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 	} else {
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 		irq_set_chip_and_handler(irq, &hip04_irq_chip,
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 					 handle_fasteoi_irq);
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@@ -326,10 +320,13 @@
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 				  unsigned long *out_hwirq,
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 				  unsigned int *out_type)
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 {
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-	unsigned long ret = 0;
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-
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 	if (irq_domain_get_of_node(d) != controller)
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 		return -EINVAL;
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+	if (intsize == 1 && intspec[0] < 16) {
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+		*out_hwirq = intspec[0];
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+		*out_type = IRQ_TYPE_EDGE_RISING;
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+		return 0;
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+	}
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 	if (intsize < 3)
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 		return -EINVAL;
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@@ -342,7 +339,7 @@
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 	*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
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-	return ret;
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+	return 0;
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 }
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 static int hip04_irq_starting_cpu(unsigned int cpu)
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@@ -359,7 +356,6 @@
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 static int __init
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 hip04_of_init(struct device_node *node, struct device_node *parent)
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 {
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-	irq_hw_number_t hwirq_base = 16;
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 	int nr_irqs, irq_base, i;
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 	if (WARN_ON(!node))
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@@ -388,24 +384,21 @@
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 		nr_irqs = HIP04_MAX_IRQS;
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 	hip04_data.nr_irqs = nr_irqs;
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-	nr_irqs -= hwirq_base; /* calculate # of irqs to allocate */
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-
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-	irq_base = irq_alloc_descs(-1, hwirq_base, nr_irqs, numa_node_id());
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+	irq_base = irq_alloc_descs(-1, 0, nr_irqs, numa_node_id());
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 	if (irq_base < 0) {
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 		pr_err("failed to allocate IRQ numbers\n");
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 		return -EINVAL;
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 	}
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 	hip04_data.domain = irq_domain_add_legacy(node, nr_irqs, irq_base,
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-						  hwirq_base,
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+						  0,
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 						  &hip04_irq_domain_ops,
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 						  &hip04_data);
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-
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 	if (WARN_ON(!hip04_data.domain))
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 		return -EINVAL;
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 #ifdef CONFIG_SMP
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-	set_smp_cross_call(hip04_raise_softirq);
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+	set_smp_ipi_range(irq_base, 16);
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 #endif
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 	set_handle_irq(hip04_handle_irq);
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