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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/irqchip/irq-gic-v2m.c
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * ARM GIC v2m MSI(-X) support
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  * Support for Message Signaled Interrupts for systems that
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@@ -7,10 +8,6 @@
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  * Authors: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
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  *	    Harish Kasiviswanathan <harish.kasiviswanathan@amd.com>
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  *	    Brandon Anderson <brandon.anderson@amd.com>
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms of the GNU General Public License version 2 as published
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- * by the Free Software Foundation.
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  */
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12
 
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 #define pr_fmt(fmt) "GICv2m: " fmt
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@@ -20,6 +17,7 @@
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 #include <linux/irq.h>
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 #include <linux/irqdomain.h>
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 #include <linux/kernel.h>
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+#include <linux/pci.h>
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 #include <linux/msi.h>
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 #include <linux/of_address.h>
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 #include <linux/of_pci.h>
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@@ -56,6 +54,7 @@
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 /* List of flags for specific v2m implementation */
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 #define GICV2M_NEEDS_SPI_OFFSET		0x00000001
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+#define GICV2M_GRAVITON_ADDRESS_ONLY	0x00000002
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 static LIST_HEAD(v2m_nodes);
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 static DEFINE_SPINLOCK(v2m_lock);
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@@ -98,19 +97,30 @@
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 	.chip	= &gicv2m_msi_irq_chip,
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 };
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+static phys_addr_t gicv2m_get_msi_addr(struct v2m_data *v2m, int hwirq)
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+{
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+	if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY)
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+		return v2m->res.start | ((hwirq - 32) << 3);
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+	else
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+		return v2m->res.start + V2M_MSI_SETSPI_NS;
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+}
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+
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 static void gicv2m_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
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 {
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 	struct v2m_data *v2m = irq_data_get_irq_chip_data(data);
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-	phys_addr_t addr = v2m->res.start + V2M_MSI_SETSPI_NS;
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+	phys_addr_t addr = gicv2m_get_msi_addr(v2m, data->hwirq);
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 	msg->address_hi = upper_32_bits(addr);
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 	msg->address_lo = lower_32_bits(addr);
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-	msg->data = data->hwirq;
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+	if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY)
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+		msg->data = 0;
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+	else
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+		msg->data = data->hwirq;
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 	if (v2m->flags & GICV2M_NEEDS_SPI_OFFSET)
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 		msg->data -= v2m->spi_offset;
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-	iommu_dma_map_msi_msg(data->irq, msg);
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+	iommu_dma_compose_msi_msg(irq_data_get_msi_desc(data), msg);
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 }
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 static struct irq_chip gicv2m_irq_chip = {
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@@ -167,6 +177,7 @@
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 static int gicv2m_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
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 				   unsigned int nr_irqs, void *args)
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 {
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+	msi_alloc_info_t *info = args;
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 	struct v2m_data *v2m = NULL, *tmp;
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 	int hwirq, offset, i, err = 0;
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@@ -185,6 +196,11 @@
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 		return -ENOSPC;
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 	hwirq = v2m->spi_start + offset;
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+
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+	err = iommu_dma_prepare_msi(info->desc,
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+				    gicv2m_get_msi_addr(v2m, hwirq));
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+	if (err)
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+		return err;
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 	for (i = 0; i < nr_irqs; i++) {
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 		err = gicv2m_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
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@@ -301,7 +317,7 @@
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 static int __init gicv2m_init_one(struct fwnode_handle *fwnode,
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 				  u32 spi_start, u32 nr_spis,
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-				  struct resource *res)
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+				  struct resource *res, u32 flags)
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 {
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 	int ret;
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 	struct v2m_data *v2m;
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@@ -314,6 +330,7 @@
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 	INIT_LIST_HEAD(&v2m->entry);
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 	v2m->fwnode = fwnode;
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+	v2m->flags = flags;
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 	memcpy(&v2m->res, res, sizeof(struct resource));
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@@ -328,7 +345,14 @@
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 		v2m->spi_start = spi_start;
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 		v2m->nr_spis = nr_spis;
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 	} else {
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-		u32 typer = readl_relaxed(v2m->base + V2M_MSI_TYPER);
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+		u32 typer;
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+
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+		/* Graviton should always have explicit spi_start/nr_spis */
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+		if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY) {
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+			ret = -EINVAL;
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+			goto err_iounmap;
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+		}
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+		typer = readl_relaxed(v2m->base + V2M_MSI_TYPER);
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 		v2m->spi_start = V2M_MSI_TYPER_BASE_SPI(typer);
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 		v2m->nr_spis = V2M_MSI_TYPER_NUM_SPI(typer);
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@@ -347,20 +371,23 @@
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 	 * the MSI data is the absolute value within the range from
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 	 * spi_start to (spi_start + num_spis).
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 	 *
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-	 * Broadom NS2 GICv2m implementation has an erratum where the MSI data
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+	 * Broadcom NS2 GICv2m implementation has an erratum where the MSI data
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 	 * is 'spi_number - 32'
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+	 *
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+	 * Reading that register fails on the Graviton implementation
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 	 */
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-	switch (readl_relaxed(v2m->base + V2M_MSI_IIDR)) {
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-	case XGENE_GICV2M_MSI_IIDR:
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-		v2m->flags |= GICV2M_NEEDS_SPI_OFFSET;
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-		v2m->spi_offset = v2m->spi_start;
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-		break;
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-	case BCM_NS2_GICV2M_MSI_IIDR:
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-		v2m->flags |= GICV2M_NEEDS_SPI_OFFSET;
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-		v2m->spi_offset = 32;
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-		break;
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+	if (!(v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY)) {
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+		switch (readl_relaxed(v2m->base + V2M_MSI_IIDR)) {
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+		case XGENE_GICV2M_MSI_IIDR:
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+			v2m->flags |= GICV2M_NEEDS_SPI_OFFSET;
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+			v2m->spi_offset = v2m->spi_start;
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+			break;
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+		case BCM_NS2_GICV2M_MSI_IIDR:
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+			v2m->flags |= GICV2M_NEEDS_SPI_OFFSET;
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+			v2m->spi_offset = 32;
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+			break;
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+		}
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 	}
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-
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 	v2m->bm = kcalloc(BITS_TO_LONGS(v2m->nr_spis), sizeof(long),
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 			  GFP_KERNEL);
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 	if (!v2m->bm) {
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@@ -413,7 +440,8 @@
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 			pr_info("DT overriding V2M MSI_TYPER (base:%u, num:%u)\n",
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 				spi_start, nr_spis);
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-		ret = gicv2m_init_one(&child->fwnode, spi_start, nr_spis, &res);
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+		ret = gicv2m_init_one(&child->fwnode, spi_start, nr_spis,
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+				      &res, 0);
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 		if (ret) {
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 			of_node_put(child);
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 			break;
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@@ -445,8 +473,27 @@
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 	return data->fwnode;
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 }
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+static bool acpi_check_amazon_graviton_quirks(void)
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+{
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+	static struct acpi_table_madt *madt;
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+	acpi_status status;
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+	bool rc = false;
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+
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+#define ACPI_AMZN_OEM_ID		"AMAZON"
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+
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+	status = acpi_get_table(ACPI_SIG_MADT, 0,
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+				(struct acpi_table_header **)&madt);
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+
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+	if (ACPI_FAILURE(status) || !madt)
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+		return rc;
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+	rc = !memcmp(madt->header.oem_id, ACPI_AMZN_OEM_ID, ACPI_OEM_ID_SIZE);
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+	acpi_put_table((struct acpi_table_header *)madt);
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+
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+	return rc;
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+}
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+
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 static int __init
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-acpi_parse_madt_msi(struct acpi_subtable_header *header,
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+acpi_parse_madt_msi(union acpi_subtable_headers *header,
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 		    const unsigned long end)
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 {
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 	int ret;
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@@ -454,6 +501,7 @@
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 	u32 spi_start = 0, nr_spis = 0;
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 	struct acpi_madt_generic_msi_frame *m;
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 	struct fwnode_handle *fwnode;
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+	u32 flags = 0;
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 	m = (struct acpi_madt_generic_msi_frame *)header;
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 	if (BAD_MADT_ENTRY(m, end))
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@@ -463,6 +511,13 @@
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 	res.end = m->base_address + SZ_4K - 1;
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 	res.flags = IORESOURCE_MEM;
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+	if (acpi_check_amazon_graviton_quirks()) {
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+		pr_info("applying Amazon Graviton quirk\n");
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+		res.end = res.start + SZ_8K - 1;
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+		flags |= GICV2M_GRAVITON_ADDRESS_ONLY;
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+		gicv2m_msi_domain_info.flags &= ~MSI_FLAG_MULTI_PCI_MSI;
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+	}
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+
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 	if (m->flags & ACPI_MADT_OVERRIDE_SPI_VALUES) {
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 		spi_start = m->spi_base;
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 		nr_spis = m->spi_count;
..
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@@ -471,13 +526,13 @@
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 			spi_start, nr_spis);
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 	}
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-	fwnode = irq_domain_alloc_fwnode((void *)m->base_address);
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+	fwnode = irq_domain_alloc_fwnode(&res.start);
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 	if (!fwnode) {
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 		pr_err("Unable to allocate GICv2m domain token\n");
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 		return -EINVAL;
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 	}
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-	ret = gicv2m_init_one(fwnode, spi_start, nr_spis, &res);
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+	ret = gicv2m_init_one(fwnode, spi_start, nr_spis, &res, flags);
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 	if (ret)
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 		irq_domain_free_fwnode(fwnode);
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