add new system file

hc

2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/irqchip/irq-gic-common.c
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@@ -10,6 +10,10 @@
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 #include "irq-gic-common.h"
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+#ifdef CONFIG_ROCKCHIP_AMP
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+#include <soc/rockchip/rockchip_amp.h>
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+#endif
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+
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 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
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 static const struct gic_kvm_info *gic_kvm_info;
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@@ -29,7 +33,13 @@
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 			  const struct gic_quirk *quirks, void *data)
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 {
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 	for (; quirks->desc; quirks++) {
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-		if (!of_device_is_compatible(np, quirks->compatible))
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+		if (!quirks->compatible && !quirks->property)
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+			continue;
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+		if (quirks->compatible &&
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+		    !of_device_is_compatible(np, quirks->compatible))
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+			continue;
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+		if (quirks->property &&
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+		    !of_property_read_bool(np, quirks->property))
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 			continue;
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 		if (quirks->init(data))
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 			pr_info("GIC: enabling workaround for %s\n",
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@@ -41,7 +51,7 @@
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 		void *data)
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 {
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 	for (; quirks->desc; quirks++) {
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-		if (quirks->compatible)
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+		if (quirks->compatible || quirks->property)
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 			continue;
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 		if (quirks->iidr != (quirks->mask & iidr))
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 			continue;
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@@ -112,8 +122,25 @@
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 	/*
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 	 * Set priority on all global interrupts.
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 	 */
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+#ifdef CONFIG_ROCKCHIP_AMP
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+	for (i = 32; i < gic_irqs; i += 4) {
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+		u32 amp_pri, j;
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+
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+		amp_pri = 0;
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+		for (j = 0; j < 4; j++) {
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+			if (rockchip_amp_need_init_amp_irq(i + j)) {
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+				amp_pri |= rockchip_amp_get_irq_prio(i + j) <<
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+					   (j * 8);
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+			} else {
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+				amp_pri |= GICD_INT_DEF_PRI << (j * 8);
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+			}
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+		}
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+		writel_relaxed(amp_pri, base + GIC_DIST_PRI + i);
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+	}
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+#else
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 	for (i = 32; i < gic_irqs; i += 4)
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 		writel_relaxed(GICD_INT_DEF_PRI_X4, base + GIC_DIST_PRI + i);
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+#endif
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 	/*
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 	 * Deactivate and disable all SPIs. Leave the PPI and SGIs