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hc

2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/irqchip/irq-armada-370-xp.c
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@@ -306,7 +306,143 @@
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 }
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 #endif
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+static void armada_xp_mpic_perf_init(void)
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+{
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+	unsigned long cpuid;
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+
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+	/*
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+	 * This Performance Counter Overflow interrupt is specific for
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+	 * Armada 370 and XP. It is not available on Armada 375, 38x and 39x.
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+	 */
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+	if (!of_machine_is_compatible("marvell,armada-370-xp"))
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+		return;
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+
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+	cpuid = cpu_logical_map(smp_processor_id());
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+
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+	/* Enable Performance Counter Overflow interrupts */
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+	writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),
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+	       per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK_OFFS);
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+}
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+
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 #ifdef CONFIG_SMP
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+static struct irq_domain *ipi_domain;
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+
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+static void armada_370_xp_ipi_mask(struct irq_data *d)
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+{
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+	u32 reg;
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+	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
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+	reg &= ~BIT(d->hwirq);
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+	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
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+}
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+
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+static void armada_370_xp_ipi_unmask(struct irq_data *d)
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+{
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+	u32 reg;
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+	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
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+	reg |= BIT(d->hwirq);
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+	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
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+}
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+
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+static void armada_370_xp_ipi_send_mask(struct irq_data *d,
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+					const struct cpumask *mask)
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+{
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+	unsigned long map = 0;
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+	int cpu;
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+
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+	/* Convert our logical CPU mask into a physical one. */
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+	for_each_cpu(cpu, mask)
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+		map |= 1 << cpu_logical_map(cpu);
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+
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+	/*
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+	 * Ensure that stores to Normal memory are visible to the
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+	 * other CPUs before issuing the IPI.
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+	 */
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+	dsb();
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+
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+	/* submit softirq */
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+	writel((map << 8) | d->hwirq, main_int_base +
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+		ARMADA_370_XP_SW_TRIG_INT_OFFS);
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+}
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+
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+static void armada_370_xp_ipi_eoi(struct irq_data *d)
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+{
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+	writel(~BIT(d->hwirq), per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
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+}
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+
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+static struct irq_chip ipi_irqchip = {
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+	.name		= "IPI",
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+	.irq_mask	= armada_370_xp_ipi_mask,
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+	.irq_unmask	= armada_370_xp_ipi_unmask,
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+	.irq_eoi	= armada_370_xp_ipi_eoi,
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+	.ipi_send_mask	= armada_370_xp_ipi_send_mask,
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+};
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+
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+static int armada_370_xp_ipi_alloc(struct irq_domain *d,
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+					 unsigned int virq,
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+					 unsigned int nr_irqs, void *args)
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+{
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+	int i;
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+
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+	for (i = 0; i < nr_irqs; i++) {
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+		irq_set_percpu_devid(virq + i);
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+		irq_domain_set_info(d, virq + i, i, &ipi_irqchip,
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+				    d->host_data,
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+				    handle_percpu_devid_fasteoi_ipi,
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+				    NULL, NULL);
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+	}
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+
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+	return 0;
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+}
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+
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+static void armada_370_xp_ipi_free(struct irq_domain *d,
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+					 unsigned int virq,
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+					 unsigned int nr_irqs)
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+{
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+	/* Not freeing IPIs */
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+}
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+
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+static const struct irq_domain_ops ipi_domain_ops = {
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+	.alloc	= armada_370_xp_ipi_alloc,
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+	.free	= armada_370_xp_ipi_free,
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+};
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+
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+static void ipi_resume(void)
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+{
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+	int i;
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+
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+	for (i = 0; i < IPI_DOORBELL_END; i++) {
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+		int irq;
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+
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+		irq = irq_find_mapping(ipi_domain, i);
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+		if (irq <= 0)
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+			continue;
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+		if (irq_percpu_is_enabled(irq)) {
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+			struct irq_data *d;
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+			d = irq_domain_get_irq_data(ipi_domain, irq);
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+			armada_370_xp_ipi_unmask(d);
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+		}
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+	}
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+}
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+
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+static __init void armada_xp_ipi_init(struct device_node *node)
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+{
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+	int base_ipi;
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+
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+	ipi_domain = irq_domain_create_linear(of_node_to_fwnode(node),
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+					      IPI_DOORBELL_END,
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+					      &ipi_domain_ops, NULL);
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+	if (WARN_ON(!ipi_domain))
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+		return;
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+
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+	irq_domain_update_bus_token(ipi_domain, DOMAIN_BUS_IPI);
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+	base_ipi = __irq_domain_alloc_irqs(ipi_domain, -1, IPI_DOORBELL_END,
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+					   NUMA_NO_NODE, NULL, false, NULL);
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+	if (WARN_ON(!base_ipi))
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+		return;
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+
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+	set_smp_ipi_range(base_ipi, IPI_DOORBELL_END);
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+}
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+
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 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
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447
 
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 static int armada_xp_set_affinity(struct irq_data *d,
..
..
@@ -330,6 +466,70 @@
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 	return IRQ_SET_MASK_OK;
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 }
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+
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+static void armada_xp_mpic_smp_cpu_init(void)
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+{
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+	u32 control;
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+	int nr_irqs, i;
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+
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+	control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
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+	nr_irqs = (control >> 2) & 0x3ff;
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+
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+	for (i = 0; i < nr_irqs; i++)
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+		writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
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+
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+	/* Disable all IPIs */
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+	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
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+
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+	/* Clear pending IPIs */
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+	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
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+
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+	/* Unmask IPI interrupt */
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+	writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
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+}
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+
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+static void armada_xp_mpic_reenable_percpu(void)
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+{
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+	unsigned int irq;
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+
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+	/* Re-enable per-CPU interrupts that were enabled before suspend */
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+	for (irq = 0; irq < ARMADA_370_XP_MAX_PER_CPU_IRQS; irq++) {
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+		struct irq_data *data;
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+		int virq;
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+
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+		virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq);
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+		if (virq == 0)
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+			continue;
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+
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+		data = irq_get_irq_data(virq);
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+
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+		if (!irq_percpu_is_enabled(virq))
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+			continue;
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+
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+		armada_370_xp_irq_unmask(data);
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+	}
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+
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+	ipi_resume();
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+}
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+
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+static int armada_xp_mpic_starting_cpu(unsigned int cpu)
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+{
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+	armada_xp_mpic_perf_init();
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+	armada_xp_mpic_smp_cpu_init();
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+	armada_xp_mpic_reenable_percpu();
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+	return 0;
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+}
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+
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+static int mpic_cascaded_starting_cpu(unsigned int cpu)
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+{
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+	armada_xp_mpic_perf_init();
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+	armada_xp_mpic_reenable_percpu();
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+	enable_percpu_irq(parent_irq, IRQ_TYPE_NONE);
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+	return 0;
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+}
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+#else
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+static void armada_xp_mpic_smp_cpu_init(void) {}
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+static void ipi_resume(void) {}
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 #endif
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 static struct irq_chip armada_370_xp_irq_chip = {
..
..
@@ -367,98 +567,6 @@
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 	return 0;
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 }
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-
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-static void armada_xp_mpic_smp_cpu_init(void)
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-{
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-	u32 control;
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-	int nr_irqs, i;
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-
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-	control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
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-	nr_irqs = (control >> 2) & 0x3ff;
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-
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-	for (i = 0; i < nr_irqs; i++)
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-		writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
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-
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-	/* Clear pending IPIs */
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-	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
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-
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-	/* Enable first 8 IPIs */
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-	writel(IPI_DOORBELL_MASK, per_cpu_int_base +
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-		ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
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-
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-	/* Unmask IPI interrupt */
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-	writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
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-}
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-
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-static void armada_xp_mpic_perf_init(void)
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-{
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-	unsigned long cpuid = cpu_logical_map(smp_processor_id());
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-
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-	/* Enable Performance Counter Overflow interrupts */
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-	writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),
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-	       per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK_OFFS);
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-}
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-
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-#ifdef CONFIG_SMP
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-static void armada_mpic_send_doorbell(const struct cpumask *mask,
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-				      unsigned int irq)
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-{
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-	int cpu;
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-	unsigned long map = 0;
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-
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-	/* Convert our logical CPU mask into a physical one. */
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-	for_each_cpu(cpu, mask)
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-		map |= 1 << cpu_logical_map(cpu);
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-
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-	/*
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-	 * Ensure that stores to Normal memory are visible to the
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-	 * other CPUs before issuing the IPI.
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-	 */
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-	dsb();
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-
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-	/* submit softirq */
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-	writel((map << 8) | irq, main_int_base +
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-		ARMADA_370_XP_SW_TRIG_INT_OFFS);
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-}
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-
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-static void armada_xp_mpic_reenable_percpu(void)
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-{
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-	unsigned int irq;
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-
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-	/* Re-enable per-CPU interrupts that were enabled before suspend */
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-	for (irq = 0; irq < ARMADA_370_XP_MAX_PER_CPU_IRQS; irq++) {
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-		struct irq_data *data;
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-		int virq;
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-
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-		virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq);
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-		if (virq == 0)
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-			continue;
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-
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-		data = irq_get_irq_data(virq);
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-
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-		if (!irq_percpu_is_enabled(virq))
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-			continue;
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-
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-		armada_370_xp_irq_unmask(data);
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-	}
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-}
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-
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-static int armada_xp_mpic_starting_cpu(unsigned int cpu)
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-{
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-	armada_xp_mpic_perf_init();
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-	armada_xp_mpic_smp_cpu_init();
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-	armada_xp_mpic_reenable_percpu();
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-	return 0;
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-}
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-
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-static int mpic_cascaded_starting_cpu(unsigned int cpu)
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-{
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-	armada_xp_mpic_perf_init();
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-	armada_xp_mpic_reenable_percpu();
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-	enable_percpu_irq(parent_irq, IRQ_TYPE_NONE);
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-	return 0;
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-}
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-#endif
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570
 
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 static const struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
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 	.map = armada_370_xp_mpic_irq_map,
..
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@@ -558,22 +666,15 @@
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 #ifdef CONFIG_SMP
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 		/* IPI Handling */
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 		if (irqnr == 0) {
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-			u32 ipimask, ipinr;
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+			unsigned long ipimask;
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+			int ipi;
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671
 
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 			ipimask = readl_relaxed(per_cpu_int_base +
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 						ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
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 				& IPI_DOORBELL_MASK;
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675
 
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-			writel(~ipimask, per_cpu_int_base +
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-				ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
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-
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-			/* Handle all pending doorbells */
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-			for (ipinr = IPI_DOORBELL_START;
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-			     ipinr < IPI_DOORBELL_END; ipinr++) {
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-				if (ipimask & (0x1 << ipinr))
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-					handle_IPI(ipinr, regs);
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-			}
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-			continue;
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+			for_each_set_bit(ipi, &ipimask, IPI_DOORBELL_END)
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+				handle_domain_irq(ipi_domain, ipi, regs);
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 		}
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 #endif
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680
 
..
..
@@ -632,6 +733,8 @@
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 		writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
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734
 	if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK)
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735
 		writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
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+
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+	ipi_resume();
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738
 }
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739
 
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 static struct syscore_ops armada_370_xp_mpic_syscore_ops = {
..
..
@@ -687,7 +790,7 @@
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 		irq_set_default_host(armada_370_xp_mpic_domain);
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 		set_handle_irq(armada_370_xp_handle_irq);
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 #ifdef CONFIG_SMP
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-		set_smp_cross_call(armada_mpic_send_doorbell);
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+		armada_xp_ipi_init(node);
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 		cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_ARMADA_XP_STARTING,
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 					  "irqchip/armada/ipi:starting",
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796
 					  armada_xp_mpic_starting_cpu, NULL);