forked from ~ljy/RK356X_SDK_RELEASE

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hc
2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/iio/adc/stm32-adc.c
....@@ -22,6 +22,7 @@
2222 #include <linux/iopoll.h>
2323 #include <linux/module.h>
2424 #include <linux/platform_device.h>
25
+#include <linux/pm_runtime.h>
2526 #include <linux/of.h>
2627 #include <linux/of_device.h>
2728 
....@@ -39,6 +40,7 @@
3940 #define STM32_ADC_MAX_SMP		7	/* SMPx range is [0..7] */
4041 #define STM32_ADC_TIMEOUT_US		100000
4142 #define STM32_ADC_TIMEOUT	(msecs_to_jiffies(STM32_ADC_TIMEOUT_US / 1000))
43
+#define STM32_ADC_HW_STOP_DELAY_MS	100
4244 
4345 #define STM32_DMA_BUFFER_SIZE		PAGE_SIZE
4446 
....@@ -90,15 +92,17 @@
9092  * @calfact_s: Calibration offset for single ended channels
9193  * @calfact_d: Calibration offset in differential
9294  * @lincalfact: Linearity calibration factor
95
+ * @calibrated: Indicates calibration status
9396  */
9497 struct stm32_adc_calib {
9598 	u32			calfact_s;
9699 	u32			calfact_d;
97100 	u32			lincalfact[STM32H7_LINCALFACT_NUM];
101
+	bool			calibrated;
98102 };
99103 
100104 /**
101
- * stm32_adc_regs - stm32 ADC misc registers & bitfield desc
105
+ * struct stm32_adc_regs - stm32 ADC misc registers & bitfield desc
102106  * @reg:		register offset
103107  * @mask:		bitfield mask
104108  * @shift:		left shift
....@@ -110,10 +114,12 @@
110114 };
111115 
112116 /**
113
- * stm32_adc_regspec - stm32 registers definition, compatible dependent data
117
+ * struct stm32_adc_regspec - stm32 registers definition
114118  * @dr:			data register offset
115119  * @ier_eoc:		interrupt enable register & eocie bitfield
120
+ * @ier_ovr:		interrupt enable register & overrun bitfield
116121  * @isr_eoc:		interrupt status register & eoc bitfield
122
+ * @isr_ovr:		interrupt status register & overrun bitfield
117123  * @sqr:		reference to sequence registers array
118124  * @exten:		trigger control register & bitfield
119125  * @extsel:		trigger selection register & bitfield
....@@ -124,7 +130,9 @@
124130 struct stm32_adc_regspec {
125131 	const u32 dr;
126132 	const struct stm32_adc_regs ier_eoc;
133
+	const struct stm32_adc_regs ier_ovr;
127134 	const struct stm32_adc_regs isr_eoc;
135
+	const struct stm32_adc_regs isr_ovr;
128136 	const struct stm32_adc_regs *sqr;
129137 	const struct stm32_adc_regs exten;
130138 	const struct stm32_adc_regs extsel;
....@@ -136,17 +144,17 @@
136144 struct stm32_adc;
137145 
138146 /**
139
- * stm32_adc_cfg - stm32 compatible configuration data
147
+ * struct stm32_adc_cfg - stm32 compatible configuration data
140148  * @regs:		registers descriptions
141149  * @adc_info:		per instance input channels definitions
142150  * @trigs:		external trigger sources
143151  * @clk_required:	clock is required
144152  * @has_vregready:	vregready status flag presence
145
- * @selfcalib:		optional routine for self-calibration
146153  * @prepare:		optional prepare routine (power-up, enable)
147154  * @start_conv:		routine to start conversions
148155  * @stop_conv:		routine to stop conversions
149156  * @unprepare:		optional unprepare routine (disable, power-down)
157
+ * @irq_clear:		routine to clear irqs
150158  * @smp_cycles:		programmable sampling time (ADC clock cycles)
151159  */
152160 struct stm32_adc_cfg {
....@@ -155,11 +163,11 @@
155163 	struct stm32_adc_trig_info	*trigs;
156164 	bool clk_required;
157165 	bool has_vregready;
158
-	int (*selfcalib)(struct stm32_adc *);
159
-	int (*prepare)(struct stm32_adc *);
160
-	void (*start_conv)(struct stm32_adc *, bool dma);
161
-	void (*stop_conv)(struct stm32_adc *);
162
-	void (*unprepare)(struct stm32_adc *);
166
+	int (*prepare)(struct iio_dev *);
167
+	void (*start_conv)(struct iio_dev *, bool dma);
168
+	void (*stop_conv)(struct iio_dev *);
169
+	void (*unprepare)(struct iio_dev *);
170
+	void (*irq_clear)(struct iio_dev *indio_dev, u32 msk);
163171 	const unsigned int *smp_cycles;
164172 };
165173 
....@@ -181,8 +189,8 @@
181189  * @rx_buf:		dma rx buffer cpu address
182190  * @rx_dma_buf:		dma rx buffer bus address
183191  * @rx_buf_sz:		dma rx buffer size
184
- * @difsel		bitmask to set single-ended/differential channel
185
- * @pcsel		bitmask to preselect channels on some devices
192
+ * @difsel:		bitmask to set single-ended/differential channel
193
+ * @pcsel:		bitmask to preselect channels on some devices
186194  * @smpr_val:		sampling time settings (e.g. smpr1 / smpr2)
187195  * @cal:		optional calibration data on some devices
188196  * @chan_name:		channel name array
....@@ -252,7 +260,7 @@
252260 	.num_res = ARRAY_SIZE(stm32h7_adc_resolutions),
253261 };
254262 
255
-/**
263
+/*
256264  * stm32f4_sq - describe regular sequence registers
257265  * - L: sequence len (register & bit field)
258266  * - SQ1..SQ16: sequence entries (register & bit field)
....@@ -299,7 +307,7 @@
299307 	{}, /* sentinel */
300308 };
301309 
302
-/**
310
+/*
303311  * stm32f4_smp_bits[] - describe sampling time register index & bit fields
304312  * Sorted so it can be indexed by channel number.
305313  */
....@@ -335,7 +343,9 @@
335343 static const struct stm32_adc_regspec stm32f4_adc_regspec = {
336344 	.dr = STM32F4_ADC_DR,
337345 	.ier_eoc = { STM32F4_ADC_CR1, STM32F4_EOCIE },
346
+	.ier_ovr = { STM32F4_ADC_CR1, STM32F4_OVRIE },
338347 	.isr_eoc = { STM32F4_ADC_SR, STM32F4_EOC },
348
+	.isr_ovr = { STM32F4_ADC_SR, STM32F4_OVR },
339349 	.sqr = stm32f4_sq,
340350 	.exten = { STM32F4_ADC_CR2, STM32F4_EXTEN_MASK, STM32F4_EXTEN_SHIFT },
341351 	.extsel = { STM32F4_ADC_CR2, STM32F4_EXTSEL_MASK,
....@@ -390,7 +400,7 @@
390400 	{},
391401 };
392402 
393
-/**
403
+/*
394404  * stm32h7_smp_bits - describe sampling time register index & bit fields
395405  * Sorted so it can be indexed by channel number.
396406  */
....@@ -427,7 +437,9 @@
427437 static const struct stm32_adc_regspec stm32h7_adc_regspec = {
428438 	.dr = STM32H7_ADC_DR,
429439 	.ier_eoc = { STM32H7_ADC_IER, STM32H7_EOCIE },
440
+	.ier_ovr = { STM32H7_ADC_IER, STM32H7_OVRIE },
430441 	.isr_eoc = { STM32H7_ADC_ISR, STM32H7_EOC },
442
+	.isr_ovr = { STM32H7_ADC_ISR, STM32H7_OVR },
431443 	.sqr = stm32h7_sq,
432444 	.exten = { STM32H7_ADC_CFGR, STM32H7_EXTEN_MASK, STM32H7_EXTEN_SHIFT },
433445 	.extsel = { STM32H7_ADC_CFGR, STM32H7_EXTSEL_MASK,
....@@ -504,6 +516,18 @@
504516 			   adc->cfg->regs->ier_eoc.mask);
505517 }
506518 
519
+static void stm32_adc_ovr_irq_enable(struct stm32_adc *adc)
520
+{
521
+	stm32_adc_set_bits(adc, adc->cfg->regs->ier_ovr.reg,
522
+			   adc->cfg->regs->ier_ovr.mask);
523
+}
524
+
525
+static void stm32_adc_ovr_irq_disable(struct stm32_adc *adc)
526
+{
527
+	stm32_adc_clr_bits(adc, adc->cfg->regs->ier_ovr.reg,
528
+			   adc->cfg->regs->ier_ovr.mask);
529
+}
530
+
507531 static void stm32_adc_set_res(struct stm32_adc *adc)
508532 {
509533 	const struct stm32_adc_regs *res = &adc->cfg->regs->res;
....@@ -514,9 +538,52 @@
514538 	stm32_adc_writel(adc, res->reg, val);
515539 }
516540 
541
+static int stm32_adc_hw_stop(struct device *dev)
542
+{
543
+	struct iio_dev *indio_dev = dev_get_drvdata(dev);
544
+	struct stm32_adc *adc = iio_priv(indio_dev);
545
+
546
+	if (adc->cfg->unprepare)
547
+		adc->cfg->unprepare(indio_dev);
548
+
549
+	if (adc->clk)
550
+		clk_disable_unprepare(adc->clk);
551
+
552
+	return 0;
553
+}
554
+
555
+static int stm32_adc_hw_start(struct device *dev)
556
+{
557
+	struct iio_dev *indio_dev = dev_get_drvdata(dev);
558
+	struct stm32_adc *adc = iio_priv(indio_dev);
559
+	int ret;
560
+
561
+	if (adc->clk) {
562
+		ret = clk_prepare_enable(adc->clk);
563
+		if (ret)
564
+			return ret;
565
+	}
566
+
567
+	stm32_adc_set_res(adc);
568
+
569
+	if (adc->cfg->prepare) {
570
+		ret = adc->cfg->prepare(indio_dev);
571
+		if (ret)
572
+			goto err_clk_dis;
573
+	}
574
+
575
+	return 0;
576
+
577
+err_clk_dis:
578
+	if (adc->clk)
579
+		clk_disable_unprepare(adc->clk);
580
+
581
+	return ret;
582
+}
583
+
517584 /**
518585  * stm32f4_adc_start_conv() - Start conversions for regular channels.
519
- * @adc: stm32 adc instance
586
+ * @indio_dev: IIO device instance
520587  * @dma: use dma to transfer conversion result
521588  *
522589  * Start conversions for regular channels.
....@@ -524,8 +591,10 @@
524591  * conversions, in IIO buffer modes. Otherwise, use ADC interrupt with direct
525592  * DR read instead (e.g. read_raw, or triggered buffer mode without DMA).
526593  */
527
-static void stm32f4_adc_start_conv(struct stm32_adc *adc, bool dma)
594
+static void stm32f4_adc_start_conv(struct iio_dev *indio_dev, bool dma)
528595 {
596
+	struct stm32_adc *adc = iio_priv(indio_dev);
597
+
529598 	stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN);
530599 
531600 	if (dma)
....@@ -542,8 +611,10 @@
542611 		stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_SWSTART);
543612 }
544613 
545
-static void stm32f4_adc_stop_conv(struct stm32_adc *adc)
614
+static void stm32f4_adc_stop_conv(struct iio_dev *indio_dev)
546615 {
616
+	struct stm32_adc *adc = iio_priv(indio_dev);
617
+
547618 	stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK);
548619 	stm32_adc_clr_bits(adc, STM32F4_ADC_SR, STM32F4_STRT);
549620 
....@@ -552,8 +623,16 @@
552623 			   STM32F4_ADON | STM32F4_DMA | STM32F4_DDS);
553624 }
554625 
555
-static void stm32h7_adc_start_conv(struct stm32_adc *adc, bool dma)
626
+static void stm32f4_adc_irq_clear(struct iio_dev *indio_dev, u32 msk)
556627 {
628
+	struct stm32_adc *adc = iio_priv(indio_dev);
629
+
630
+	stm32_adc_clr_bits(adc, adc->cfg->regs->isr_eoc.reg, msk);
631
+}
632
+
633
+static void stm32h7_adc_start_conv(struct iio_dev *indio_dev, bool dma)
634
+{
635
+	struct stm32_adc *adc = iio_priv(indio_dev);
557636 	enum stm32h7_adc_dmngt dmngt;
558637 	unsigned long flags;
559638 	u32 val;
....@@ -572,9 +651,9 @@
572651 	stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTART);
573652 }
574653 
575
-static void stm32h7_adc_stop_conv(struct stm32_adc *adc)
654
+static void stm32h7_adc_stop_conv(struct iio_dev *indio_dev)
576655 {
577
-	struct iio_dev *indio_dev = iio_priv_to_dev(adc);
656
+	struct stm32_adc *adc = iio_priv(indio_dev);
578657 	int ret;
579658 	u32 val;
580659 
....@@ -589,9 +668,16 @@
589668 	stm32_adc_clr_bits(adc, STM32H7_ADC_CFGR, STM32H7_DMNGT_MASK);
590669 }
591670 
592
-static int stm32h7_adc_exit_pwr_down(struct stm32_adc *adc)
671
+static void stm32h7_adc_irq_clear(struct iio_dev *indio_dev, u32 msk)
593672 {
594
-	struct iio_dev *indio_dev = iio_priv_to_dev(adc);
673
+	struct stm32_adc *adc = iio_priv(indio_dev);
674
+	/* On STM32H7 IRQs are cleared by writing 1 into ISR register */
675
+	stm32_adc_set_bits(adc, adc->cfg->regs->isr_eoc.reg, msk);
676
+}
677
+
678
+static int stm32h7_adc_exit_pwr_down(struct iio_dev *indio_dev)
679
+{
680
+	struct stm32_adc *adc = iio_priv(indio_dev);
595681 	int ret;
596682 	u32 val;
597683 
....@@ -627,9 +713,9 @@
627713 	stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD);
628714 }
629715 
630
-static int stm32h7_adc_enable(struct stm32_adc *adc)
716
+static int stm32h7_adc_enable(struct iio_dev *indio_dev)
631717 {
632
-	struct iio_dev *indio_dev = iio_priv_to_dev(adc);
718
+	struct stm32_adc *adc = iio_priv(indio_dev);
633719 	int ret;
634720 	u32 val;
635721 
....@@ -650,9 +736,9 @@
650736 	return ret;
651737 }
652738 
653
-static void stm32h7_adc_disable(struct stm32_adc *adc)
739
+static void stm32h7_adc_disable(struct iio_dev *indio_dev)
654740 {
655
-	struct iio_dev *indio_dev = iio_priv_to_dev(adc);
741
+	struct stm32_adc *adc = iio_priv(indio_dev);
656742 	int ret;
657743 	u32 val;
658744 
....@@ -667,18 +753,14 @@
667753 
668754 /**
669755  * stm32h7_adc_read_selfcalib() - read calibration shadow regs, save result
670
- * @adc: stm32 adc instance
756
+ * @indio_dev: IIO device instance
757
+ * Note: Must be called once ADC is enabled, so LINCALRDYW[1..6] are writable
671758  */
672
-static int stm32h7_adc_read_selfcalib(struct stm32_adc *adc)
759
+static int stm32h7_adc_read_selfcalib(struct iio_dev *indio_dev)
673760 {
674
-	struct iio_dev *indio_dev = iio_priv_to_dev(adc);
761
+	struct stm32_adc *adc = iio_priv(indio_dev);
675762 	int i, ret;
676763 	u32 lincalrdyw_mask, val;
677
-
678
-	/* Enable adc so LINCALRDYW1..6 bits are writable */
679
-	ret = stm32h7_adc_enable(adc);
680
-	if (ret)
681
-		return ret;
682764 
683765 	/* Read linearity calibration */
684766 	lincalrdyw_mask = STM32H7_LINCALRDYW6;
....@@ -692,7 +774,7 @@
692774 						   100, STM32_ADC_TIMEOUT_US);
693775 		if (ret) {
694776 			dev_err(&indio_dev->dev, "Failed to read calfact\n");
695
-			goto disable;
777
+			return ret;
696778 		}
697779 
698780 		val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2);
....@@ -708,21 +790,19 @@
708790 	adc->cal.calfact_s >>= STM32H7_CALFACT_S_SHIFT;
709791 	adc->cal.calfact_d = (val & STM32H7_CALFACT_D_MASK);
710792 	adc->cal.calfact_d >>= STM32H7_CALFACT_D_SHIFT;
793
+	adc->cal.calibrated = true;
711794 
712
-disable:
713
-	stm32h7_adc_disable(adc);
714
-
715
-	return ret;
795
+	return 0;
716796 }
717797 
718798 /**
719799  * stm32h7_adc_restore_selfcalib() - Restore saved self-calibration result
720
- * @adc: stm32 adc instance
800
+ * @indio_dev: IIO device instance
721801  * Note: ADC must be enabled, with no on-going conversions.
722802  */
723
-static int stm32h7_adc_restore_selfcalib(struct stm32_adc *adc)
803
+static int stm32h7_adc_restore_selfcalib(struct iio_dev *indio_dev)
724804 {
725
-	struct iio_dev *indio_dev = iio_priv_to_dev(adc);
805
+	struct stm32_adc *adc = iio_priv(indio_dev);
726806 	int i, ret;
727807 	u32 lincalrdyw_mask, val;
728808 
....@@ -789,19 +869,18 @@
789869 #define STM32H7_ADC_CALIB_TIMEOUT_US		100000
790870 
791871 /**
792
- * stm32h7_adc_selfcalib() - Procedure to calibrate ADC (from power down)
793
- * @adc: stm32 adc instance
794
- * Exit from power down, calibrate ADC, then return to power down.
872
+ * stm32h7_adc_selfcalib() - Procedure to calibrate ADC
873
+ * @indio_dev: IIO device instance
874
+ * Note: Must be called once ADC is out of power down.
795875  */
796
-static int stm32h7_adc_selfcalib(struct stm32_adc *adc)
876
+static int stm32h7_adc_selfcalib(struct iio_dev *indio_dev)
797877 {
798
-	struct iio_dev *indio_dev = iio_priv_to_dev(adc);
878
+	struct stm32_adc *adc = iio_priv(indio_dev);
799879 	int ret;
800880 	u32 val;
801881 
802
-	ret = stm32h7_adc_exit_pwr_down(adc);
803
-	if (ret)
804
-		return ret;
882
+	if (adc->cal.calibrated)
883
+		return true;
805884 
806885 	/*
807886 	 * Select calibration mode:
....@@ -818,7 +897,7 @@
818897 					   STM32H7_ADC_CALIB_TIMEOUT_US);
819898 	if (ret) {
820899 		dev_err(&indio_dev->dev, "calibration failed\n");
821
-		goto pwr_dwn;
900
+		goto out;
822901 	}
823902 
824903 	/*
....@@ -835,24 +914,19 @@
835914 					   STM32H7_ADC_CALIB_TIMEOUT_US);
836915 	if (ret) {
837916 		dev_err(&indio_dev->dev, "calibration failed\n");
838
-		goto pwr_dwn;
917
+		goto out;
839918 	}
840919 
920
+out:
841921 	stm32_adc_clr_bits(adc, STM32H7_ADC_CR,
842922 			   STM32H7_ADCALDIF | STM32H7_ADCALLIN);
843
-
844
-	/* Read calibration result for future reference */
845
-	ret = stm32h7_adc_read_selfcalib(adc);
846
-
847
-pwr_dwn:
848
-	stm32h7_adc_enter_pwr_down(adc);
849923 
850924 	return ret;
851925 }
852926 
853927 /**
854928  * stm32h7_adc_prepare() - Leave power down mode to enable ADC.
855
- * @adc: stm32 adc instance
929
+ * @indio_dev: IIO device instance
856930  * Leave power down mode.
857931  * Configure channels as single ended or differential before enabling ADC.
858932  * Enable ADC.
....@@ -861,21 +935,31 @@
861935  * - Only one input is selected for single ended (e.g. 'vinp')
862936  * - Two inputs are selected for differential channels (e.g. 'vinp' & 'vinn')
863937  */
864
-static int stm32h7_adc_prepare(struct stm32_adc *adc)
938
+static int stm32h7_adc_prepare(struct iio_dev *indio_dev)
865939 {
866
-	int ret;
940
+	struct stm32_adc *adc = iio_priv(indio_dev);
941
+	int calib, ret;
867942 
868
-	ret = stm32h7_adc_exit_pwr_down(adc);
943
+	ret = stm32h7_adc_exit_pwr_down(indio_dev);
869944 	if (ret)
870945 		return ret;
871946 
947
+	ret = stm32h7_adc_selfcalib(indio_dev);
948
+	if (ret < 0)
949
+		goto pwr_dwn;
950
+	calib = ret;
951
+
872952 	stm32_adc_writel(adc, STM32H7_ADC_DIFSEL, adc->difsel);
873953 
874
-	ret = stm32h7_adc_enable(adc);
954
+	ret = stm32h7_adc_enable(indio_dev);
875955 	if (ret)
876956 		goto pwr_dwn;
877957 
878
-	ret = stm32h7_adc_restore_selfcalib(adc);
958
+	/* Either restore or read calibration result for future reference */
959
+	if (calib)
960
+		ret = stm32h7_adc_restore_selfcalib(indio_dev);
961
+	else
962
+		ret = stm32h7_adc_read_selfcalib(indio_dev);
879963 	if (ret)
880964 		goto disable;
881965 
....@@ -884,16 +968,19 @@
884968 	return 0;
885969 
886970 disable:
887
-	stm32h7_adc_disable(adc);
971
+	stm32h7_adc_disable(indio_dev);
888972 pwr_dwn:
889973 	stm32h7_adc_enter_pwr_down(adc);
890974 
891975 	return ret;
892976 }
893977 
894
-static void stm32h7_adc_unprepare(struct stm32_adc *adc)
978
+static void stm32h7_adc_unprepare(struct iio_dev *indio_dev)
895979 {
896
-	stm32h7_adc_disable(adc);
980
+	struct stm32_adc *adc = iio_priv(indio_dev);
981
+
982
+	stm32_adc_writel(adc, STM32H7_ADC_PCSEL, 0);
983
+	stm32h7_adc_disable(indio_dev);
897984 	stm32h7_adc_enter_pwr_down(adc);
898985 }
899986 
....@@ -954,6 +1041,7 @@
9541041 
9551042 /**
9561043  * stm32_adc_get_trig_extsel() - Get external trigger selection
1044
+ * @indio_dev: IIO device structure
9571045  * @trig: trigger
9581046  *
9591047  * Returns trigger extsel value, if trig matches, -EINVAL otherwise.
....@@ -1065,6 +1153,7 @@
10651153 				 int *res)
10661154 {
10671155 	struct stm32_adc *adc = iio_priv(indio_dev);
1156
+	struct device *dev = indio_dev->dev.parent;
10681157 	const struct stm32_adc_regspec *regs = adc->cfg->regs;
10691158 	long timeout;
10701159 	u32 val;
....@@ -1074,10 +1163,10 @@
10741163 
10751164 	adc->bufi = 0;
10761165 
1077
-	if (adc->cfg->prepare) {
1078
-		ret = adc->cfg->prepare(adc);
1079
-		if (ret)
1080
-			return ret;
1166
+	ret = pm_runtime_get_sync(dev);
1167
+	if (ret < 0) {
1168
+		pm_runtime_put_noidle(dev);
1169
+		return ret;
10811170 	}
10821171 
10831172 	/* Apply sampling time settings */
....@@ -1098,7 +1187,7 @@
10981187 
10991188 	stm32_adc_conv_irq_enable(adc);
11001189 
1101
-	adc->cfg->start_conv(adc, false);
1190
+	adc->cfg->start_conv(indio_dev, false);
11021191 
11031192 	timeout = wait_for_completion_interruptible_timeout(
11041193 					&adc->completion, STM32_ADC_TIMEOUT);
....@@ -1111,12 +1200,12 @@
11111200 		ret = IIO_VAL_INT;
11121201 	}
11131202 
1114
-	adc->cfg->stop_conv(adc);
1203
+	adc->cfg->stop_conv(indio_dev);
11151204 
11161205 	stm32_adc_conv_irq_disable(adc);
11171206 
1118
-	if (adc->cfg->unprepare)
1119
-		adc->cfg->unprepare(adc);
1207
+	pm_runtime_mark_last_busy(dev);
1208
+	pm_runtime_put_autosuspend(dev);
11201209 
11211210 	return ret;
11221211 }
....@@ -1163,12 +1252,55 @@
11631252 	}
11641253 }
11651254 
1166
-static irqreturn_t stm32_adc_isr(int irq, void *data)
1255
+static void stm32_adc_irq_clear(struct iio_dev *indio_dev, u32 msk)
11671256 {
1168
-	struct stm32_adc *adc = data;
1169
-	struct iio_dev *indio_dev = iio_priv_to_dev(adc);
1257
+	struct stm32_adc *adc = iio_priv(indio_dev);
1258
+
1259
+	adc->cfg->irq_clear(indio_dev, msk);
1260
+}
1261
+
1262
+static irqreturn_t stm32_adc_threaded_isr(int irq, void *data)
1263
+{
1264
+	struct iio_dev *indio_dev = data;
1265
+	struct stm32_adc *adc = iio_priv(indio_dev);
11701266 	const struct stm32_adc_regspec *regs = adc->cfg->regs;
11711267 	u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg);
1268
+
1269
+	/* Check ovr status right now, as ovr mask should be already disabled */
1270
+	if (status & regs->isr_ovr.mask) {
1271
+		/*
1272
+		 * Clear ovr bit to avoid subsequent calls to IRQ handler.
1273
+		 * This requires to stop ADC first. OVR bit state in ISR,
1274
+		 * is propaged to CSR register by hardware.
1275
+		 */
1276
+		adc->cfg->stop_conv(indio_dev);
1277
+		stm32_adc_irq_clear(indio_dev, regs->isr_ovr.mask);
1278
+		dev_err(&indio_dev->dev, "Overrun, stopping: restart needed\n");
1279
+		return IRQ_HANDLED;
1280
+	}
1281
+
1282
+	return IRQ_NONE;
1283
+}
1284
+
1285
+static irqreturn_t stm32_adc_isr(int irq, void *data)
1286
+{
1287
+	struct iio_dev *indio_dev = data;
1288
+	struct stm32_adc *adc = iio_priv(indio_dev);
1289
+	const struct stm32_adc_regspec *regs = adc->cfg->regs;
1290
+	u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg);
1291
+
1292
+	if (status & regs->isr_ovr.mask) {
1293
+		/*
1294
+		 * Overrun occurred on regular conversions: data for wrong
1295
+		 * channel may be read. Unconditionally disable interrupts
1296
+		 * to stop processing data and print error message.
1297
+		 * Restarting the capture can be done by disabling, then
1298
+		 * re-enabling it (e.g. write 0, then 1 to buffer/enable).
1299
+		 */
1300
+		stm32_adc_ovr_irq_disable(adc);
1301
+		stm32_adc_conv_irq_disable(adc);
1302
+		return IRQ_WAKE_THREAD;
1303
+	}
11721304 
11731305 	if (status & regs->isr_eoc.mask) {
11741306 		/* Reading DR also clears EOC status flag */
....@@ -1224,15 +1356,22 @@
12241356 				      const unsigned long *scan_mask)
12251357 {
12261358 	struct stm32_adc *adc = iio_priv(indio_dev);
1359
+	struct device *dev = indio_dev->dev.parent;
12271360 	int ret;
1361
+
1362
+	ret = pm_runtime_get_sync(dev);
1363
+	if (ret < 0) {
1364
+		pm_runtime_put_noidle(dev);
1365
+		return ret;
1366
+	}
12281367 
12291368 	adc->num_conv = bitmap_weight(scan_mask, indio_dev->masklength);
12301369 
12311370 	ret = stm32_adc_conf_scan_seq(indio_dev, scan_mask);
1232
-	if (ret)
1233
-		return ret;
1371
+	pm_runtime_mark_last_busy(dev);
1372
+	pm_runtime_put_autosuspend(dev);
12341373 
1235
-	return 0;
1374
+	return ret;
12361375 }
12371376 
12381377 static int stm32_adc_of_xlate(struct iio_dev *indio_dev,
....@@ -1249,6 +1388,10 @@
12491388 
12501389 /**
12511390  * stm32_adc_debugfs_reg_access - read or write register value
1391
+ * @indio_dev: IIO device structure
1392
+ * @reg: register offset
1393
+ * @writeval: value to write
1394
+ * @readval: value to read
12521395  *
12531396  * To read a value from an ADC register:
12541397  *   echo [ADC reg offset] > direct_reg_access
....@@ -1262,11 +1405,22 @@
12621405 					unsigned *readval)
12631406 {
12641407 	struct stm32_adc *adc = iio_priv(indio_dev);
1408
+	struct device *dev = indio_dev->dev.parent;
1409
+	int ret;
1410
+
1411
+	ret = pm_runtime_get_sync(dev);
1412
+	if (ret < 0) {
1413
+		pm_runtime_put_noidle(dev);
1414
+		return ret;
1415
+	}
12651416 
12661417 	if (!readval)
12671418 		stm32_adc_writel(adc, reg, writeval);
12681419 	else
12691420 		*readval = stm32_adc_readl(adc, reg);
1421
+
1422
+	pm_runtime_mark_last_busy(dev);
1423
+	pm_runtime_put_autosuspend(dev);
12701424 
12711425 	return 0;
12721426 }
....@@ -1375,18 +1529,19 @@
13751529 static int stm32_adc_buffer_postenable(struct iio_dev *indio_dev)
13761530 {
13771531 	struct stm32_adc *adc = iio_priv(indio_dev);
1532
+	struct device *dev = indio_dev->dev.parent;
13781533 	int ret;
13791534 
1380
-	if (adc->cfg->prepare) {
1381
-		ret = adc->cfg->prepare(adc);
1382
-		if (ret)
1383
-			return ret;
1535
+	ret = pm_runtime_get_sync(dev);
1536
+	if (ret < 0) {
1537
+		pm_runtime_put_noidle(dev);
1538
+		return ret;
13841539 	}
13851540 
13861541 	ret = stm32_adc_set_trig(indio_dev, indio_dev->trig);
13871542 	if (ret) {
13881543 		dev_err(&indio_dev->dev, "Can't set trigger\n");
1389
-		goto err_unprepare;
1544
+		goto err_pm_put;
13901545 	}
13911546 
13921547 	ret = stm32_adc_dma_start(indio_dev);
....@@ -1395,28 +1550,23 @@
13951550 		goto err_clr_trig;
13961551 	}
13971552 
1398
-	ret = iio_triggered_buffer_postenable(indio_dev);
1399
-	if (ret < 0)
1400
-		goto err_stop_dma;
1401
-
14021553 	/* Reset adc buffer index */
14031554 	adc->bufi = 0;
1555
+
1556
+	stm32_adc_ovr_irq_enable(adc);
14041557 
14051558 	if (!adc->dma_chan)
14061559 		stm32_adc_conv_irq_enable(adc);
14071560 
1408
-	adc->cfg->start_conv(adc, !!adc->dma_chan);
1561
+	adc->cfg->start_conv(indio_dev, !!adc->dma_chan);
14091562 
14101563 	return 0;
14111564 
1412
-err_stop_dma:
1413
-	if (adc->dma_chan)
1414
-		dmaengine_terminate_all(adc->dma_chan);
14151565 err_clr_trig:
14161566 	stm32_adc_set_trig(indio_dev, NULL);
1417
-err_unprepare:
1418
-	if (adc->cfg->unprepare)
1419
-		adc->cfg->unprepare(adc);
1567
+err_pm_put:
1568
+	pm_runtime_mark_last_busy(dev);
1569
+	pm_runtime_put_autosuspend(dev);
14201570 
14211571 	return ret;
14221572 }
....@@ -1424,15 +1574,13 @@
14241574 static int stm32_adc_buffer_predisable(struct iio_dev *indio_dev)
14251575 {
14261576 	struct stm32_adc *adc = iio_priv(indio_dev);
1427
-	int ret;
1577
+	struct device *dev = indio_dev->dev.parent;
14281578 
1429
-	adc->cfg->stop_conv(adc);
1579
+	adc->cfg->stop_conv(indio_dev);
14301580 	if (!adc->dma_chan)
14311581 		stm32_adc_conv_irq_disable(adc);
14321582 
1433
-	ret = iio_triggered_buffer_predisable(indio_dev);
1434
-	if (ret < 0)
1435
-		dev_err(&indio_dev->dev, "predisable failed\n");
1583
+	stm32_adc_ovr_irq_disable(adc);
14361584 
14371585 	if (adc->dma_chan)
14381586 		dmaengine_terminate_sync(adc->dma_chan);
....@@ -1440,10 +1588,10 @@
14401588 	if (stm32_adc_set_trig(indio_dev, NULL))
14411589 		dev_err(&indio_dev->dev, "Can't clear trigger\n");
14421590 
1443
-	if (adc->cfg->unprepare)
1444
-		adc->cfg->unprepare(adc);
1591
+	pm_runtime_mark_last_busy(dev);
1592
+	pm_runtime_put_autosuspend(dev);
14451593 
1446
-	return ret;
1594
+	return 0;
14471595 }
14481596 
14491597 static const struct iio_buffer_setup_ops stm32_adc_buffer_setup_ops = {
....@@ -1691,13 +1839,9 @@
16911839 	adc->dma_chan = dma_request_chan(dev, "rx");
16921840 	if (IS_ERR(adc->dma_chan)) {
16931841 		ret = PTR_ERR(adc->dma_chan);
1694
-		if (ret != -ENODEV) {
1695
-			if (ret != -EPROBE_DEFER)
1696
-				dev_err(dev,
1697
-					"DMA channel request failed with %d\n",
1698
-					ret);
1699
-			return ret;
1700
-		}
1842
+		if (ret != -ENODEV)
1843
+			return dev_err_probe(dev, ret,
1844
+					     "DMA channel request failed with\n");
17011845 
17021846 		/* DMA is optional: fall back to IRQ mode */
17031847 		adc->dma_chan = NULL;
....@@ -1756,12 +1900,11 @@
17561900 		of_match_device(dev->driver->of_match_table, dev)->data;
17571901 
17581902 	indio_dev->name = dev_name(&pdev->dev);
1759
-	indio_dev->dev.parent = &pdev->dev;
17601903 	indio_dev->dev.of_node = pdev->dev.of_node;
17611904 	indio_dev->info = &stm32_adc_iio_info;
17621905 	indio_dev->modes = INDIO_DIRECT_MODE | INDIO_HARDWARE_TRIGGERED;
17631906 
1764
-	platform_set_drvdata(pdev, adc);
1907
+	platform_set_drvdata(pdev, indio_dev);
17651908 
17661909 	ret = of_property_read_u32(pdev->dev.of_node, "reg", &adc->offset);
17671910 	if (ret != 0) {
....@@ -1770,13 +1913,12 @@
17701913 	}
17711914 
17721915 	adc->irq = platform_get_irq(pdev, 0);
1773
-	if (adc->irq < 0) {
1774
-		dev_err(&pdev->dev, "failed to get irq\n");
1916
+	if (adc->irq < 0)
17751917 		return adc->irq;
1776
-	}
17771918 
1778
-	ret = devm_request_irq(&pdev->dev, adc->irq, stm32_adc_isr,
1779
-			       0, pdev->name, adc);
1919
+	ret = devm_request_threaded_irq(&pdev->dev, adc->irq, stm32_adc_isr,
1920
+					stm32_adc_threaded_isr,
1921
+					0, pdev->name, indio_dev);
17801922 	if (ret) {
17811923 		dev_err(&pdev->dev, "failed to request IRQ\n");
17821924 		return ret;
....@@ -1793,32 +1935,17 @@
17931935 		}
17941936 	}
17951937 
1796
-	if (adc->clk) {
1797
-		ret = clk_prepare_enable(adc->clk);
1798
-		if (ret < 0) {
1799
-			dev_err(&pdev->dev, "clk enable failed\n");
1800
-			return ret;
1801
-		}
1802
-	}
1803
-
18041938 	ret = stm32_adc_of_get_resolution(indio_dev);
18051939 	if (ret < 0)
1806
-		goto err_clk_disable;
1807
-	stm32_adc_set_res(adc);
1808
-
1809
-	if (adc->cfg->selfcalib) {
1810
-		ret = adc->cfg->selfcalib(adc);
1811
-		if (ret)
1812
-			goto err_clk_disable;
1813
-	}
1940
+		return ret;
18141941 
18151942 	ret = stm32_adc_chan_of_init(indio_dev);
18161943 	if (ret < 0)
1817
-		goto err_clk_disable;
1944
+		return ret;
18181945 
18191946 	ret = stm32_adc_dma_request(dev, indio_dev);
18201947 	if (ret < 0)
1821
-		goto err_clk_disable;
1948
+		return ret;
18221949 
18231950 	if (!adc->dma_chan)
18241951 		handler = &stm32_adc_trigger_handler;
....@@ -1831,15 +1958,35 @@
18311958 		goto err_dma_disable;
18321959 	}
18331960 
1961
+	/* Get stm32-adc-core PM online */
1962
+	pm_runtime_get_noresume(dev);
1963
+	pm_runtime_set_active(dev);
1964
+	pm_runtime_set_autosuspend_delay(dev, STM32_ADC_HW_STOP_DELAY_MS);
1965
+	pm_runtime_use_autosuspend(dev);
1966
+	pm_runtime_enable(dev);
1967
+
1968
+	ret = stm32_adc_hw_start(dev);
1969
+	if (ret)
1970
+		goto err_buffer_cleanup;
1971
+
18341972 	ret = iio_device_register(indio_dev);
18351973 	if (ret) {
18361974 		dev_err(&pdev->dev, "iio dev register failed\n");
1837
-		goto err_buffer_cleanup;
1975
+		goto err_hw_stop;
18381976 	}
1977
+
1978
+	pm_runtime_mark_last_busy(dev);
1979
+	pm_runtime_put_autosuspend(dev);
18391980 
18401981 	return 0;
18411982 
1983
+err_hw_stop:
1984
+	stm32_adc_hw_stop(dev);
1985
+
18421986 err_buffer_cleanup:
1987
+	pm_runtime_disable(dev);
1988
+	pm_runtime_set_suspended(dev);
1989
+	pm_runtime_put_noidle(dev);
18431990 	iio_triggered_buffer_cleanup(indio_dev);
18441991 
18451992 err_dma_disable:
....@@ -1849,19 +1996,21 @@
18491996 				  adc->rx_buf, adc->rx_dma_buf);
18501997 		dma_release_channel(adc->dma_chan);
18511998 	}
1852
-err_clk_disable:
1853
-	if (adc->clk)
1854
-		clk_disable_unprepare(adc->clk);
18551999 
18562000 	return ret;
18572001 }
18582002 
18592003 static int stm32_adc_remove(struct platform_device *pdev)
18602004 {
1861
-	struct stm32_adc *adc = platform_get_drvdata(pdev);
1862
-	struct iio_dev *indio_dev = iio_priv_to_dev(adc);
2005
+	struct iio_dev *indio_dev = platform_get_drvdata(pdev);
2006
+	struct stm32_adc *adc = iio_priv(indio_dev);
18632007 
2008
+	pm_runtime_get_sync(&pdev->dev);
18642009 	iio_device_unregister(indio_dev);
2010
+	stm32_adc_hw_stop(&pdev->dev);
2011
+	pm_runtime_disable(&pdev->dev);
2012
+	pm_runtime_set_suspended(&pdev->dev);
2013
+	pm_runtime_put_noidle(&pdev->dev);
18652014 	iio_triggered_buffer_cleanup(indio_dev);
18662015 	if (adc->dma_chan) {
18672016 		dma_free_coherent(adc->dma_chan->device->dev,
....@@ -1869,11 +2018,59 @@
18692018 				  adc->rx_buf, adc->rx_dma_buf);
18702019 		dma_release_channel(adc->dma_chan);
18712020 	}
1872
-	if (adc->clk)
1873
-		clk_disable_unprepare(adc->clk);
18742021 
18752022 	return 0;
18762023 }
2024
+
2025
+#if defined(CONFIG_PM_SLEEP)
2026
+static int stm32_adc_suspend(struct device *dev)
2027
+{
2028
+	struct iio_dev *indio_dev = dev_get_drvdata(dev);
2029
+
2030
+	if (iio_buffer_enabled(indio_dev))
2031
+		stm32_adc_buffer_predisable(indio_dev);
2032
+
2033
+	return pm_runtime_force_suspend(dev);
2034
+}
2035
+
2036
+static int stm32_adc_resume(struct device *dev)
2037
+{
2038
+	struct iio_dev *indio_dev = dev_get_drvdata(dev);
2039
+	int ret;
2040
+
2041
+	ret = pm_runtime_force_resume(dev);
2042
+	if (ret < 0)
2043
+		return ret;
2044
+
2045
+	if (!iio_buffer_enabled(indio_dev))
2046
+		return 0;
2047
+
2048
+	ret = stm32_adc_update_scan_mode(indio_dev,
2049
+					 indio_dev->active_scan_mask);
2050
+	if (ret < 0)
2051
+		return ret;
2052
+
2053
+	return stm32_adc_buffer_postenable(indio_dev);
2054
+}
2055
+#endif
2056
+
2057
+#if defined(CONFIG_PM)
2058
+static int stm32_adc_runtime_suspend(struct device *dev)
2059
+{
2060
+	return stm32_adc_hw_stop(dev);
2061
+}
2062
+
2063
+static int stm32_adc_runtime_resume(struct device *dev)
2064
+{
2065
+	return stm32_adc_hw_start(dev);
2066
+}
2067
+#endif
2068
+
2069
+static const struct dev_pm_ops stm32_adc_pm_ops = {
2070
+	SET_SYSTEM_SLEEP_PM_OPS(stm32_adc_suspend, stm32_adc_resume)
2071
+	SET_RUNTIME_PM_OPS(stm32_adc_runtime_suspend, stm32_adc_runtime_resume,
2072
+			   NULL)
2073
+};
18772074 
18782075 static const struct stm32_adc_cfg stm32f4_adc_cfg = {
18792076 	.regs = &stm32f4_adc_regspec,
....@@ -1883,18 +2080,19 @@
18832080 	.start_conv = stm32f4_adc_start_conv,
18842081 	.stop_conv = stm32f4_adc_stop_conv,
18852082 	.smp_cycles = stm32f4_adc_smp_cycles,
2083
+	.irq_clear = stm32f4_adc_irq_clear,
18862084 };
18872085 
18882086 static const struct stm32_adc_cfg stm32h7_adc_cfg = {
18892087 	.regs = &stm32h7_adc_regspec,
18902088 	.adc_info = &stm32h7_adc_info,
18912089 	.trigs = stm32h7_adc_trigs,
1892
-	.selfcalib = stm32h7_adc_selfcalib,
18932090 	.start_conv = stm32h7_adc_start_conv,
18942091 	.stop_conv = stm32h7_adc_stop_conv,
18952092 	.prepare = stm32h7_adc_prepare,
18962093 	.unprepare = stm32h7_adc_unprepare,
18972094 	.smp_cycles = stm32h7_adc_smp_cycles,
2095
+	.irq_clear = stm32h7_adc_irq_clear,
18982096 };
18992097 
19002098 static const struct stm32_adc_cfg stm32mp1_adc_cfg = {
....@@ -1902,12 +2100,12 @@
19022100 	.adc_info = &stm32h7_adc_info,
19032101 	.trigs = stm32h7_adc_trigs,
19042102 	.has_vregready = true,
1905
-	.selfcalib = stm32h7_adc_selfcalib,
19062103 	.start_conv = stm32h7_adc_start_conv,
19072104 	.stop_conv = stm32h7_adc_stop_conv,
19082105 	.prepare = stm32h7_adc_prepare,
19092106 	.unprepare = stm32h7_adc_unprepare,
19102107 	.smp_cycles = stm32h7_adc_smp_cycles,
2108
+	.irq_clear = stm32h7_adc_irq_clear,
19112109 };
19122110 
19132111 static const struct of_device_id stm32_adc_of_match[] = {
....@@ -1924,6 +2122,7 @@
19242122 	.driver = {
19252123 		.name = "stm32-adc",
19262124 		.of_match_table = stm32_adc_of_match,
2125
+		.pm = &stm32_adc_pm_ops,
19272126 	},
19282127 };
19292128 module_platform_driver(stm32_adc_driver);