add new system file

hc

2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/i2c/busses/i2c-stm32f4.c
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@@ -232,10 +232,10 @@
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 		 * In standard mode:
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 		 * t_scl_high = t_scl_low = CCR * I2C parent clk period
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 		 * So to reach 100 kHz, we have:
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-		 * CCR = I2C parent rate / 100 kHz >> 1
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+		 * CCR = I2C parent rate / (100 kHz * 2)
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 		 *
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 		 * For example with parent rate = 2 MHz:
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-		 * CCR = 2000000 / (100000 << 1) = 10
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+		 * CCR = 2000000 / (100000 * 2) = 10
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 		 * t_scl_high = t_scl_low = 10 * (1 / 2000000) = 5000 ns
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 		 * t_scl_high + t_scl_low = 10000 ns so 100 kHz is reached
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 		 *
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@@ -243,7 +243,7 @@
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 		 * parent rate is not higher than 46 MHz . As a result val
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 		 * is at most 8 bits wide and so fits into the CCR bits [11:0].
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 		 */
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-		val = i2c_dev->parent_rate / (100000 << 1);
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+		val = i2c_dev->parent_rate / (I2C_MAX_STANDARD_MODE_FREQ * 2);
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 	} else {
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 		/*
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 		 * In fast mode, we compute CCR with duty = 0 as with low
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@@ -263,7 +263,7 @@
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 		 * parent rate is not higher than 46 MHz . As a result val
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 		 * is at most 6 bits wide and so fits into the CCR bits [11:0].
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 		 */
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-		val = DIV_ROUND_UP(i2c_dev->parent_rate, 400000 * 3);
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+		val = DIV_ROUND_UP(i2c_dev->parent_rate, I2C_MAX_FAST_MODE_FREQ * 3);
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 		/* Select Fast mode */
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 		ccr |= STM32F4_I2C_CCR_FS;
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@@ -797,8 +797,8 @@
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 	rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
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 	if (IS_ERR(rst)) {
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-		dev_err(&pdev->dev, "Error: Missing controller reset\n");
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-		ret = PTR_ERR(rst);
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+		ret = dev_err_probe(&pdev->dev, PTR_ERR(rst),
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+				    "Error: Missing reset ctrl\n");
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 		goto clk_free;
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 	}
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 	reset_control_assert(rst);
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@@ -807,7 +807,7 @@
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 	i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
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 	ret = of_property_read_u32(np, "clock-frequency", &clk_rate);
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-	if (!ret && clk_rate >= 400000)
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+	if (!ret && clk_rate >= I2C_MAX_FAST_MODE_FREQ)
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 		i2c_dev->speed = STM32_I2C_SPEED_FAST;
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 	i2c_dev->dev = &pdev->dev;