forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/i2c/busses/i2c-designware-common.c
....@@ -8,17 +8,23 @@
88  * Copyright (C) 2007 MontaVista Software Inc.
99  * Copyright (C) 2009 Provigent Ltd.
1010  */
11
+#include <linux/acpi.h>
1112 #include <linux/clk.h>
1213 #include <linux/delay.h>
13
-#include <linux/export.h>
14
-#include <linux/errno.h>
14
+#include <linux/device.h>
1515 #include <linux/err.h>
16
+#include <linux/errno.h>
17
+#include <linux/export.h>
1618 #include <linux/i2c.h>
1719 #include <linux/interrupt.h>
1820 #include <linux/io.h>
21
+#include <linux/kernel.h>
1922 #include <linux/module.h>
2023 #include <linux/pm_runtime.h>
24
+#include <linux/regmap.h>
2125 #include <linux/swab.h>
26
+#include <linux/types.h>
27
+#include <linux/units.h>
2228 
2329 #include "i2c-designware-core.h"
2430 
....@@ -53,68 +59,275 @@
5359 		"incorrect slave-transmitter mode configuration",
5460 };
5561 
56
-u32 dw_readl(struct dw_i2c_dev *dev, int offset)
62
+static int dw_reg_read(void *context, unsigned int reg, unsigned int *val)
5763 {
58
-	u32 value;
64
+	struct dw_i2c_dev *dev = context;
5965 
60
-	if (dev->flags & ACCESS_16BIT)
61
-		value = readw_relaxed(dev->base + offset) |
62
-			(readw_relaxed(dev->base + offset + 2) << 16);
63
-	else
64
-		value = readl_relaxed(dev->base + offset);
66
+	*val = readl_relaxed(dev->base + reg);
6567 
66
-	if (dev->flags & ACCESS_SWAP)
67
-		return swab32(value);
68
-	else
69
-		return value;
68
+	return 0;
7069 }
7170 
72
-void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset)
71
+static int dw_reg_write(void *context, unsigned int reg, unsigned int val)
7372 {
74
-	if (dev->flags & ACCESS_SWAP)
75
-		b = swab32(b);
73
+	struct dw_i2c_dev *dev = context;
7674 
77
-	if (dev->flags & ACCESS_16BIT) {
78
-		writew_relaxed((u16)b, dev->base + offset);
79
-		writew_relaxed((u16)(b >> 16), dev->base + offset + 2);
80
-	} else {
81
-		writel_relaxed(b, dev->base + offset);
82
-	}
75
+	writel_relaxed(val, dev->base + reg);
76
+
77
+	return 0;
78
+}
79
+
80
+static int dw_reg_read_swab(void *context, unsigned int reg, unsigned int *val)
81
+{
82
+	struct dw_i2c_dev *dev = context;
83
+
84
+	*val = swab32(readl_relaxed(dev->base + reg));
85
+
86
+	return 0;
87
+}
88
+
89
+static int dw_reg_write_swab(void *context, unsigned int reg, unsigned int val)
90
+{
91
+	struct dw_i2c_dev *dev = context;
92
+
93
+	writel_relaxed(swab32(val), dev->base + reg);
94
+
95
+	return 0;
96
+}
97
+
98
+static int dw_reg_read_word(void *context, unsigned int reg, unsigned int *val)
99
+{
100
+	struct dw_i2c_dev *dev = context;
101
+
102
+	*val = readw_relaxed(dev->base + reg) |
103
+		(readw_relaxed(dev->base + reg + 2) << 16);
104
+
105
+	return 0;
106
+}
107
+
108
+static int dw_reg_write_word(void *context, unsigned int reg, unsigned int val)
109
+{
110
+	struct dw_i2c_dev *dev = context;
111
+
112
+	writew_relaxed(val, dev->base + reg);
113
+	writew_relaxed(val >> 16, dev->base + reg + 2);
114
+
115
+	return 0;
83116 }
84117 
85118 /**
86
- * i2c_dw_set_reg_access() - Set register access flags
119
+ * i2c_dw_init_regmap() - Initialize registers map
87120  * @dev: device private data
88121  *
89
- * Autodetects needed register access mode and sets access flags accordingly.
90
- * This must be called before doing any other register access.
122
+ * Autodetects needed register access mode and creates the regmap with
123
+ * corresponding read/write callbacks. This must be called before doing any
124
+ * other register access.
91125  */
92
-int i2c_dw_set_reg_access(struct dw_i2c_dev *dev)
126
+int i2c_dw_init_regmap(struct dw_i2c_dev *dev)
93127 {
128
+	struct regmap_config map_cfg = {
129
+		.reg_bits = 32,
130
+		.val_bits = 32,
131
+		.reg_stride = 4,
132
+		.disable_locking = true,
133
+		.reg_read = dw_reg_read,
134
+		.reg_write = dw_reg_write,
135
+		.max_register = DW_IC_COMP_TYPE,
136
+	};
94137 	u32 reg;
95138 	int ret;
139
+
140
+	/*
141
+	 * Skip detecting the registers map configuration if the regmap has
142
+	 * already been provided by a higher code.
143
+	 */
144
+	if (dev->map)
145
+		return 0;
96146 
97147 	ret = i2c_dw_acquire_lock(dev);
98148 	if (ret)
99149 		return ret;
100150 
101
-	reg = dw_readl(dev, DW_IC_COMP_TYPE);
151
+	reg = readl(dev->base + DW_IC_COMP_TYPE);
102152 	i2c_dw_release_lock(dev);
103153 
104154 	if (reg == swab32(DW_IC_COMP_TYPE_VALUE)) {
105
-		/* Configure register endianess access */
106
-		dev->flags |= ACCESS_SWAP;
155
+		map_cfg.reg_read = dw_reg_read_swab;
156
+		map_cfg.reg_write = dw_reg_write_swab;
107157 	} else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
108
-		/* Configure register access mode 16bit */
109
-		dev->flags |= ACCESS_16BIT;
158
+		map_cfg.reg_read = dw_reg_read_word;
159
+		map_cfg.reg_write = dw_reg_write_word;
110160 	} else if (reg != DW_IC_COMP_TYPE_VALUE) {
111161 		dev_err(dev->dev,
112162 			"Unknown Synopsys component type: 0x%08x\n", reg);
113163 		return -ENODEV;
114164 	}
115165 
166
+	/*
167
+	 * Note we'll check the return value of the regmap IO accessors only
168
+	 * at the probe stage. The rest of the code won't do this because
169
+	 * basically we have MMIO-based regmap so non of the read/write methods
170
+	 * can fail.
171
+	 */
172
+	dev->map = devm_regmap_init(dev->dev, NULL, dev, &map_cfg);
173
+	if (IS_ERR(dev->map)) {
174
+		dev_err(dev->dev, "Failed to init the registers map\n");
175
+		return PTR_ERR(dev->map);
176
+	}
177
+
116178 	return 0;
117179 }
180
+
181
+static const u32 supported_speeds[] = {
182
+	I2C_MAX_HIGH_SPEED_MODE_FREQ,
183
+	I2C_MAX_FAST_MODE_PLUS_FREQ,
184
+	I2C_MAX_FAST_MODE_FREQ,
185
+	I2C_MAX_STANDARD_MODE_FREQ,
186
+};
187
+
188
+int i2c_dw_validate_speed(struct dw_i2c_dev *dev)
189
+{
190
+	struct i2c_timings *t = &dev->timings;
191
+	unsigned int i;
192
+
193
+	/*
194
+	 * Only standard mode at 100kHz, fast mode at 400kHz,
195
+	 * fast mode plus at 1MHz and high speed mode at 3.4MHz are supported.
196
+	 */
197
+	for (i = 0; i < ARRAY_SIZE(supported_speeds); i++) {
198
+		if (t->bus_freq_hz == supported_speeds[i])
199
+			return 0;
200
+	}
201
+
202
+	dev_err(dev->dev,
203
+		"%d Hz is unsupported, only 100kHz, 400kHz, 1MHz and 3.4MHz are supported\n",
204
+		t->bus_freq_hz);
205
+
206
+	return -EINVAL;
207
+}
208
+EXPORT_SYMBOL_GPL(i2c_dw_validate_speed);
209
+
210
+#ifdef CONFIG_ACPI
211
+
212
+#include <linux/dmi.h>
213
+
214
+/*
215
+ * The HCNT/LCNT information coming from ACPI should be the most accurate
216
+ * for given platform. However, some systems get it wrong. On such systems
217
+ * we get better results by calculating those based on the input clock.
218
+ */
219
+static const struct dmi_system_id i2c_dw_no_acpi_params[] = {
220
+	{
221
+		.ident = "Dell Inspiron 7348",
222
+		.matches = {
223
+			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
224
+			DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 7348"),
225
+		},
226
+	},
227
+	{}
228
+};
229
+
230
+static void i2c_dw_acpi_params(struct device *device, char method[],
231
+			       u16 *hcnt, u16 *lcnt, u32 *sda_hold)
232
+{
233
+	struct acpi_buffer buf = { ACPI_ALLOCATE_BUFFER };
234
+	acpi_handle handle = ACPI_HANDLE(device);
235
+	union acpi_object *obj;
236
+
237
+	if (dmi_check_system(i2c_dw_no_acpi_params))
238
+		return;
239
+
240
+	if (ACPI_FAILURE(acpi_evaluate_object(handle, method, NULL, &buf)))
241
+		return;
242
+
243
+	obj = (union acpi_object *)buf.pointer;
244
+	if (obj->type == ACPI_TYPE_PACKAGE && obj->package.count == 3) {
245
+		const union acpi_object *objs = obj->package.elements;
246
+
247
+		*hcnt = (u16)objs[0].integer.value;
248
+		*lcnt = (u16)objs[1].integer.value;
249
+		*sda_hold = (u32)objs[2].integer.value;
250
+	}
251
+
252
+	kfree(buf.pointer);
253
+}
254
+
255
+int i2c_dw_acpi_configure(struct device *device)
256
+{
257
+	struct dw_i2c_dev *dev = dev_get_drvdata(device);
258
+	struct i2c_timings *t = &dev->timings;
259
+	u32 ss_ht = 0, fp_ht = 0, hs_ht = 0, fs_ht = 0;
260
+
261
+	/*
262
+	 * Try to get SDA hold time and *CNT values from an ACPI method for
263
+	 * selected speed modes.
264
+	 */
265
+	i2c_dw_acpi_params(device, "SSCN", &dev->ss_hcnt, &dev->ss_lcnt, &ss_ht);
266
+	i2c_dw_acpi_params(device, "FPCN", &dev->fp_hcnt, &dev->fp_lcnt, &fp_ht);
267
+	i2c_dw_acpi_params(device, "HSCN", &dev->hs_hcnt, &dev->hs_lcnt, &hs_ht);
268
+	i2c_dw_acpi_params(device, "FMCN", &dev->fs_hcnt, &dev->fs_lcnt, &fs_ht);
269
+
270
+	switch (t->bus_freq_hz) {
271
+	case I2C_MAX_STANDARD_MODE_FREQ:
272
+		dev->sda_hold_time = ss_ht;
273
+		break;
274
+	case I2C_MAX_FAST_MODE_PLUS_FREQ:
275
+		dev->sda_hold_time = fp_ht;
276
+		break;
277
+	case I2C_MAX_HIGH_SPEED_MODE_FREQ:
278
+		dev->sda_hold_time = hs_ht;
279
+		break;
280
+	case I2C_MAX_FAST_MODE_FREQ:
281
+	default:
282
+		dev->sda_hold_time = fs_ht;
283
+		break;
284
+	}
285
+
286
+	return 0;
287
+}
288
+EXPORT_SYMBOL_GPL(i2c_dw_acpi_configure);
289
+
290
+static u32 i2c_dw_acpi_round_bus_speed(struct device *device)
291
+{
292
+	u32 acpi_speed;
293
+	int i;
294
+
295
+	acpi_speed = i2c_acpi_find_bus_speed(device);
296
+	/*
297
+	 * Some DSTDs use a non standard speed, round down to the lowest
298
+	 * standard speed.
299
+	 */
300
+	for (i = 0; i < ARRAY_SIZE(supported_speeds); i++) {
301
+		if (acpi_speed >= supported_speeds[i])
302
+			return supported_speeds[i];
303
+	}
304
+
305
+	return 0;
306
+}
307
+
308
+#else	/* CONFIG_ACPI */
309
+
310
+static inline u32 i2c_dw_acpi_round_bus_speed(struct device *device) { return 0; }
311
+
312
+#endif	/* CONFIG_ACPI */
313
+
314
+void i2c_dw_adjust_bus_speed(struct dw_i2c_dev *dev)
315
+{
316
+	u32 acpi_speed = i2c_dw_acpi_round_bus_speed(dev->dev);
317
+	struct i2c_timings *t = &dev->timings;
318
+
319
+	/*
320
+	 * Find bus speed from the "clock-frequency" device property, ACPI
321
+	 * or by using fast mode if neither is set.
322
+	 */
323
+	if (acpi_speed && t->bus_freq_hz)
324
+		t->bus_freq_hz = min(t->bus_freq_hz, acpi_speed);
325
+	else if (acpi_speed || t->bus_freq_hz)
326
+		t->bus_freq_hz = max(t->bus_freq_hz, acpi_speed);
327
+	else
328
+		t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ;
329
+}
330
+EXPORT_SYMBOL_GPL(i2c_dw_adjust_bus_speed);
118331 
119332 u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
120333 {
....@@ -135,7 +348,8 @@
135348 		 *
136349 		 * If your hardware is free from tHD;STA issue, try this one.
137350 		 */
138
-		return (ic_clk * tSYMBOL + 500000) / 1000000 - 8 + offset;
351
+		return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * tSYMBOL, MICRO) -
352
+		       8 + offset;
139353 	else
140354 		/*
141355 		 * Conditional expression:
....@@ -151,8 +365,8 @@
151365 		 * The reason why we need to take into account "tf" here,
152366 		 * is the same as described in i2c_dw_scl_lcnt().
153367 		 */
154
-		return (ic_clk * (tSYMBOL + tf) + 500000) / 1000000
155
-			- 3 + offset;
368
+		return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * (tSYMBOL + tf), MICRO) -
369
+		       3 + offset;
156370 }
157371 
158372 u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
....@@ -168,7 +382,8 @@
168382 	 * account the fall time of SCL signal (tf).  Default tf value
169383 	 * should be 0.3 us, for safety.
170384 	 */
171
-	return ((ic_clk * (tLOW + tf) + 500000) / 1000000) - 1 + offset;
385
+	return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * (tLOW + tf), MICRO) -
386
+	       1 + offset;
172387 }
173388 
174389 int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev)
....@@ -181,19 +396,25 @@
181396 		return ret;
182397 
183398 	/* Configure SDA Hold Time if required */
184
-	reg = dw_readl(dev, DW_IC_COMP_VERSION);
399
+	ret = regmap_read(dev->map, DW_IC_COMP_VERSION, &reg);
400
+	if (ret)
401
+		goto err_release_lock;
402
+
185403 	if (reg >= DW_IC_SDA_HOLD_MIN_VERS) {
186404 		if (!dev->sda_hold_time) {
187405 			/* Keep previous hold time setting if no one set it */
188
-			dev->sda_hold_time = dw_readl(dev, DW_IC_SDA_HOLD);
406
+			ret = regmap_read(dev->map, DW_IC_SDA_HOLD,
407
+					  &dev->sda_hold_time);
408
+			if (ret)
409
+				goto err_release_lock;
189410 		}
190411 
191412 		/*
192413 		 * Workaround for avoiding TX arbitration lost in case I2C
193
-		 * slave pulls SDA down "too quickly" after falling egde of
414
+		 * slave pulls SDA down "too quickly" after falling edge of
194415 		 * SCL by enabling non-zero SDA RX hold. Specification says it
195416 		 * extends incoming SDA low to high transition while SCL is
196
-		 * high but it apprears to help also above issue.
417
+		 * high but it appears to help also above issue.
197418 		 */
198419 		if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK))
199420 			dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT;
....@@ -201,20 +422,24 @@
201422 		dev_dbg(dev->dev, "SDA Hold Time TX:RX = %d:%d\n",
202423 			dev->sda_hold_time & ~(u32)DW_IC_SDA_HOLD_RX_MASK,
203424 			dev->sda_hold_time >> DW_IC_SDA_HOLD_RX_SHIFT);
425
+	} else if (dev->set_sda_hold_time) {
426
+		dev->set_sda_hold_time(dev);
204427 	} else if (dev->sda_hold_time) {
205428 		dev_warn(dev->dev,
206429 			"Hardware too old to adjust SDA hold time.\n");
207430 		dev->sda_hold_time = 0;
208431 	}
209432 
433
+err_release_lock:
210434 	i2c_dw_release_lock(dev);
211435 
212
-	return 0;
436
+	return ret;
213437 }
214438 
215439 void __i2c_dw_disable(struct dw_i2c_dev *dev)
216440 {
217441 	int timeout = 100;
442
+	u32 status;
218443 
219444 	do {
220445 		__i2c_dw_disable_nowait(dev);
....@@ -222,7 +447,8 @@
222447 		 * The enable status register may be unimplemented, but
223448 		 * in that case this test reads zero and exits the loop.
224449 		 */
225
-		if ((dw_readl(dev, DW_IC_ENABLE_STATUS) & 1) == 0)
450
+		regmap_read(dev->map, DW_IC_ENABLE_STATUS, &status);
451
+		if ((status & 1) == 0)
226452 			return;
227453 
228454 		/*
....@@ -249,13 +475,24 @@
249475 
250476 int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare)
251477 {
252
-	if (IS_ERR(dev->clk))
253
-		return PTR_ERR(dev->clk);
478
+	int ret;
254479 
255
-	if (prepare)
256
-		return clk_prepare_enable(dev->clk);
480
+	if (prepare) {
481
+		/* Optional interface clock */
482
+		ret = clk_prepare_enable(dev->pclk);
483
+		if (ret)
484
+			return ret;
485
+
486
+		ret = clk_prepare_enable(dev->clk);
487
+		if (ret)
488
+			clk_disable_unprepare(dev->pclk);
489
+
490
+		return ret;
491
+	}
257492 
258493 	clk_disable_unprepare(dev->clk);
494
+	clk_disable_unprepare(dev->pclk);
495
+
259496 	return 0;
260497 }
261498 EXPORT_SYMBOL_GPL(i2c_dw_prepare_clk);
....@@ -267,7 +504,7 @@
267504 	if (!dev->acquire_lock)
268505 		return 0;
269506 
270
-	ret = dev->acquire_lock(dev);
507
+	ret = dev->acquire_lock();
271508 	if (!ret)
272509 		return 0;
273510 
....@@ -279,7 +516,7 @@
279516 void i2c_dw_release_lock(struct dw_i2c_dev *dev)
280517 {
281518 	if (dev->release_lock)
282
-		dev->release_lock(dev);
519
+		dev->release_lock();
283520 }
284521 
285522 /*
....@@ -287,22 +524,23 @@
287524  */
288525 int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
289526 {
290
-	int timeout = TIMEOUT;
527
+	u32 status;
528
+	int ret;
291529 
292
-	while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
293
-		if (timeout <= 0) {
294
-			dev_warn(dev->dev, "timeout waiting for bus ready\n");
295
-			i2c_recover_bus(&dev->adapter);
530
+	ret = regmap_read_poll_timeout(dev->map, DW_IC_STATUS, status,
531
+				       !(status & DW_IC_STATUS_ACTIVITY),
532
+				       1100, 20000);
533
+	if (ret) {
534
+		dev_warn(dev->dev, "timeout waiting for bus ready\n");
296535 
297
-			if (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY)
298
-				return -ETIMEDOUT;
299
-			return 0;
300
-		}
301
-		timeout--;
302
-		usleep_range(1000, 1100);
536
+		i2c_recover_bus(&dev->adapter);
537
+
538
+		regmap_read(dev->map, DW_IC_STATUS, &status);
539
+		if (!(status & DW_IC_STATUS_ACTIVITY))
540
+			ret = 0;
303541 	}
304542 
305
-	return 0;
543
+	return ret;
306544 }
307545 
308546 int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
....@@ -328,6 +566,34 @@
328566 		return -EIO;
329567 }
330568 
569
+int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev)
570
+{
571
+	u32 param, tx_fifo_depth, rx_fifo_depth;
572
+	int ret;
573
+
574
+	/*
575
+	 * Try to detect the FIFO depth if not set by interface driver,
576
+	 * the depth could be from 2 to 256 from HW spec.
577
+	 */
578
+	ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, &param);
579
+	if (ret)
580
+		return ret;
581
+
582
+	tx_fifo_depth = ((param >> 16) & 0xff) + 1;
583
+	rx_fifo_depth = ((param >> 8)  & 0xff) + 1;
584
+	if (!dev->tx_fifo_depth) {
585
+		dev->tx_fifo_depth = tx_fifo_depth;
586
+		dev->rx_fifo_depth = rx_fifo_depth;
587
+	} else if (tx_fifo_depth >= 2) {
588
+		dev->tx_fifo_depth = min_t(u32, dev->tx_fifo_depth,
589
+				tx_fifo_depth);
590
+		dev->rx_fifo_depth = min_t(u32, dev->rx_fifo_depth,
591
+				rx_fifo_depth);
592
+	}
593
+
594
+	return 0;
595
+}
596
+
331597 u32 i2c_dw_func(struct i2c_adapter *adap)
332598 {
333599 	struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
....@@ -337,24 +603,20 @@
337603 
338604 void i2c_dw_disable(struct dw_i2c_dev *dev)
339605 {
606
+	u32 dummy;
607
+
340608 	/* Disable controller */
341609 	__i2c_dw_disable(dev);
342610 
343
-	/* Disable all interupts */
344
-	dw_writel(dev, 0, DW_IC_INTR_MASK);
345
-	dw_readl(dev, DW_IC_CLR_INTR);
611
+	/* Disable all interrupts */
612
+	regmap_write(dev->map, DW_IC_INTR_MASK, 0);
613
+	regmap_read(dev->map, DW_IC_CLR_INTR, &dummy);
346614 }
347615 
348616 void i2c_dw_disable_int(struct dw_i2c_dev *dev)
349617 {
350
-	dw_writel(dev, 0, DW_IC_INTR_MASK);
618
+	regmap_write(dev->map, DW_IC_INTR_MASK, 0);
351619 }
352
-
353
-u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev)
354
-{
355
-	return dw_readl(dev, DW_IC_COMP_PARAM_1);
356
-}
357
-EXPORT_SYMBOL_GPL(i2c_dw_read_comp_param);
358620 
359621 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core");
360622 MODULE_LICENSE("GPL");