~hc/RK356X_SDK_RELEASE.git

..	..	@@ -447,7 +447,7 @@
447	447	if (etm4x_sspcicrn_present(drvdata, i))
448	448	etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i));
449	449	}
450		- for (i = 0; i < drvdata->nr_addr_cmp; i++) {
	450	+ for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
451	451	etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i));
452	452	etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i));
453	453	}
..	..	@@ -960,25 +960,21 @@
960	960	struct csdev_access *csa)
961	961	{
962	962	u32 devarch = readl_relaxed(drvdata->base + TRCDEVARCH);
963		- u32 idr1 = readl_relaxed(drvdata->base + TRCIDR1);
964	963
965	964	/*
966	965	* All ETMs must implement TRCDEVARCH to indicate that
967		- * the component is an ETMv4. To support any broken
968		- * implementations we fall back to TRCIDR1 check, which
969		- * is not really reliable.
	966	+ * the component is an ETMv4. Even though TRCIDR1 also
	967	+ * contains the information, it is part of the "Trace"
	968	+ * register and must be accessed with the OSLK cleared,
	969	+ * with MMIO. But we cannot touch the OSLK until we are
	970	+ * sure this is an ETM. So rely only on the TRCDEVARCH.
970	971	*/
971		- if ((devarch & ETM_DEVARCH_ID_MASK) == ETM_DEVARCH_ETMv4x_ARCH) {
972		- drvdata->arch = etm_devarch_to_arch(devarch);
973		- } else {
974		- pr_warn("CPU%d: ETM4x incompatible TRCDEVARCH: %x, falling back to TRCIDR1\n",
975		- smp_processor_id(), devarch);
976		-
977		- if (ETM_TRCIDR1_ARCH_MAJOR(idr1) != ETM_TRCIDR1_ARCH_ETMv4)
978		- return false;
979		- drvdata->arch = etm_trcidr_to_arch(idr1);
	972	+ if ((devarch & ETM_DEVARCH_ID_MASK) != ETM_DEVARCH_ETMv4x_ARCH) {
	973	+ pr_warn_once("TRCDEVARCH doesn't match ETMv4 architecture\n");
	974	+ return false;
980	975	}
981	976
	977	+ drvdata->arch = etm_devarch_to_arch(devarch);
982	978	*csa = CSDEV_ACCESS_IOMEM(drvdata->base);
983	979	return true;
984	980	}