add new system file

hc

2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c
..
..
@@ -22,9 +22,60 @@
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 #include "gf100.h"
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 #include "ctxgf100.h"
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+#include <core/firmware.h>
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+#include <subdev/acr.h>
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 #include <subdev/timer.h>
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+#include <nvfw/flcn.h>
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+
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 #include <nvif/class.h>
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+
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+void
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+gm20b_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust)
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+{
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+	struct flcn_bl_dmem_desc hdr;
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+	u64 addr;
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+
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+	nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr));
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+	addr = ((u64)hdr.code_dma_base1 << 40 | hdr.code_dma_base << 8);
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+	hdr.code_dma_base  = lower_32_bits((addr + adjust) >> 8);
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+	hdr.code_dma_base1 = upper_32_bits((addr + adjust) >> 8);
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+	addr = ((u64)hdr.data_dma_base1 << 40 | hdr.data_dma_base << 8);
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+	hdr.data_dma_base  = lower_32_bits((addr + adjust) >> 8);
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+	hdr.data_dma_base1 = upper_32_bits((addr + adjust) >> 8);
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+	nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
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+
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+	flcn_bl_dmem_desc_dump(&acr->subdev, &hdr);
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+}
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+
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+void
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+gm20b_gr_acr_bld_write(struct nvkm_acr *acr, u32 bld,
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+		       struct nvkm_acr_lsfw *lsfw)
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+{
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+	const u64 base = lsfw->offset.img + lsfw->app_start_offset;
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+	const u64 code = (base + lsfw->app_resident_code_offset) >> 8;
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+	const u64 data = (base + lsfw->app_resident_data_offset) >> 8;
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+	const struct flcn_bl_dmem_desc hdr = {
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+		.ctx_dma = FALCON_DMAIDX_UCODE,
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+		.code_dma_base = lower_32_bits(code),
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+		.non_sec_code_off = lsfw->app_resident_code_offset,
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+		.non_sec_code_size = lsfw->app_resident_code_size,
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+		.code_entry_point = lsfw->app_imem_entry,
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+		.data_dma_base = lower_32_bits(data),
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+		.data_size = lsfw->app_resident_data_size,
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+		.code_dma_base1 = upper_32_bits(code),
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+		.data_dma_base1 = upper_32_bits(data),
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+	};
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+
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+	nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
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+}
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+
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+const struct nvkm_acr_lsf_func
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+gm20b_gr_fecs_acr = {
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+	.bld_size = sizeof(struct flcn_bl_dmem_desc),
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+	.bld_write = gm20b_gr_acr_bld_write,
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+	.bld_patch = gm20b_gr_acr_bld_patch,
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+};
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 static void
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 gm20b_gr_init_gpc_mmu(struct gf100_gr *gr)
..
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@@ -33,7 +84,7 @@
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 	u32 val;
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 	/* Bypass MMU check for non-secure boot */
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-	if (!device->secboot) {
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+	if (!device->acr) {
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 		nvkm_wr32(device, 0x100ce4, 0xffffffff);
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 		if (nvkm_rd32(device, 0x100ce4) != 0xffffffff)
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@@ -85,8 +136,52 @@
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 	}
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 };
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+static int
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+gm20b_gr_load(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif)
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+{
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+	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
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+	int ret;
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+
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+	ret = nvkm_acr_lsfw_load_bl_inst_data_sig(subdev, &gr->fecs.falcon,
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+						  NVKM_ACR_LSF_FECS,
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+						  "gr/fecs_", ver, fwif->fecs);
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+	if (ret)
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+		return ret;
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+
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+
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+	if (nvkm_firmware_load_blob(subdev, "gr/", "gpccs_inst", ver,
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+				    &gr->gpccs.inst) ||
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+	    nvkm_firmware_load_blob(subdev, "gr/", "gpccs_data", ver,
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+				    &gr->gpccs.data))
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+		return -ENOENT;
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+
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+	gr->firmware = true;
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+
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+	return gk20a_gr_load_sw(gr, "gr/", ver);
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+}
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+
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+#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
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+MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_bl.bin");
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+MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_inst.bin");
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+MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_data.bin");
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+MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_sig.bin");
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+MODULE_FIRMWARE("nvidia/gm20b/gr/gpccs_inst.bin");
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+MODULE_FIRMWARE("nvidia/gm20b/gr/gpccs_data.bin");
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+MODULE_FIRMWARE("nvidia/gm20b/gr/sw_ctx.bin");
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+MODULE_FIRMWARE("nvidia/gm20b/gr/sw_nonctx.bin");
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+MODULE_FIRMWARE("nvidia/gm20b/gr/sw_bundle_init.bin");
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+MODULE_FIRMWARE("nvidia/gm20b/gr/sw_method_init.bin");
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+#endif
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+
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+static const struct gf100_gr_fwif
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+gm20b_gr_fwif[] = {
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+	{  0, gm20b_gr_load, &gm20b_gr, &gm20b_gr_fecs_acr },
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+	{ -1, gm200_gr_nofw },
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+	{}
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+};
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+
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 int
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 gm20b_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
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 {
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-	return gm200_gr_new_(&gm20b_gr, device, index, pgr);
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+	return gf100_gr_new_(gm20b_gr_fwif, device, index, pgr);
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 }