add new system file

hc

2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
..
..
@@ -1,14 +1,6 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
1
2
 /*
2
3
  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
3
- *
4
- * This program is free software; you can redistribute it and/or modify
5
- * it under the terms of the GNU General Public License version 2 and
6
- * only version 2 as published by the Free Software Foundation.
7
- *
8
- * This program is distributed in the hope that it will be useful,
9
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
10
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11
- * GNU General Public License for more details.
12
4
  */
13
5
 
14
6
 #ifndef __DSI_PHY_H__
..
..
@@ -20,6 +12,9 @@
20
12
 
21
13
 #define dsi_phy_read(offset) msm_readl((offset))
22
14
 #define dsi_phy_write(offset, data) msm_writel((data), (offset))
15
+
16
+/* v3.0.0 10nm implementation that requires the old timings settings */
17
+#define V3_0_0_10NM_OLD_TIMINGS_QUIRK	BIT(0)
23
18
 
24
19
 struct msm_dsi_phy_ops {
25
20
 	int (*init) (struct msm_dsi_phy *phy);
..
..
@@ -41,18 +36,22 @@
41
36
 	bool src_pll_truthtable[DSI_MAX][DSI_MAX];
42
37
 	const resource_size_t io_start[DSI_MAX];
43
38
 	const int num_dsi_phy;
39
+	const int quirks;
44
40
 };
45
41
 
46
42
 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs;
43
+extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs;
47
44
 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs;
48
45
 extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
49
46
 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs;
50
47
 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs;
48
+extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs;
51
49
 extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs;
50
+extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs;
51
+extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs;
52
+extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs;
52
53
 
53
54
 struct msm_dsi_dphy_timing {
54
-	u32 clk_pre;
55
-	u32 clk_post;
56
55
 	u32 clk_zero;
57
56
 	u32 clk_trail;
58
57
 	u32 clk_prepare;
..
..
@@ -103,6 +102,8 @@
103
102
 				struct msm_dsi_phy_clk_request *clk_req);
104
103
 int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
105
104
 				struct msm_dsi_phy_clk_request *clk_req);
105
+int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
106
+				struct msm_dsi_phy_clk_request *clk_req);
106
107
 void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
107
108
 				u32 bit_mask);
108
109
 int msm_dsi_phy_init_common(struct msm_dsi_phy *phy);