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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
..
..
@@ -1,25 +1,19 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
1
2
 /*
2
3
  * Copyright (C) 2014-2018 The Linux Foundation. All rights reserved.
3
4
  * Copyright (C) 2013 Red Hat
4
5
  * Author: Rob Clark <robdclark@gmail.com>
5
- *
6
- * This program is free software; you can redistribute it and/or modify it
7
- * under the terms of the GNU General Public License version 2 as published by
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- * the Free Software Foundation.
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- *
10
- * This program is distributed in the hope that it will be useful, but WITHOUT
11
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
- * more details.
14
- *
15
- * You should have received a copy of the GNU General Public License along with
16
- * this program.  If not, see <http://www.gnu.org/licenses/>.
17
6
  */
18
7
 
19
8
 #define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
20
9
 
21
10
 #include <linux/debugfs.h>
22
11
 #include <linux/dma-buf.h>
12
+
13
+#include <drm/drm_atomic_uapi.h>
14
+#include <drm/drm_damage_helper.h>
15
+#include <drm/drm_file.h>
16
+#include <drm/drm_gem_framebuffer_helper.h>
23
17
 
24
18
 #include "msm_drv.h"
25
19
 #include "dpu_kms.h"
..
..
@@ -59,8 +53,13 @@
59
53
 	R_MAX
60
54
 };
61
55
 
56
+/*
57
+ * Default Preload Values
58
+ */
62
59
 #define DPU_QSEED3_DEFAULT_PRELOAD_H 0x4
63
60
 #define DPU_QSEED3_DEFAULT_PRELOAD_V 0x3
61
+#define DPU_QSEED4_DEFAULT_PRELOAD_V 0x2
62
+#define DPU_QSEED4_DEFAULT_PRELOAD_H 0x4
64
63
 
65
64
 #define DEFAULT_REFRESH_RATE	60
66
65
 
..
..
@@ -93,8 +92,6 @@
93
92
 
94
93
 	enum dpu_sspp pipe;
95
94
 	uint32_t features;      /* capabilities from catalog */
96
-	uint32_t nformats;
97
-	uint32_t formats[64];
98
95
 
99
96
 	struct dpu_hw_pipe *pipe_hw;
100
97
 	struct dpu_hw_pipe_cfg pipe_cfg;
..
..
@@ -119,28 +116,99 @@
119
116
 	bool debugfs_default_scale;
120
117
 };
121
118
 
119
+static const uint64_t supported_format_modifiers[] = {
120
+	DRM_FORMAT_MOD_QCOM_COMPRESSED,
121
+	DRM_FORMAT_MOD_LINEAR,
122
+	DRM_FORMAT_MOD_INVALID
123
+};
124
+
122
125
 #define to_dpu_plane(x) container_of(x, struct dpu_plane, base)
123
126
 
124
127
 static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane)
125
128
 {
126
-	struct msm_drm_private *priv;
129
+	struct msm_drm_private *priv = plane->dev->dev_private;
127
130
 
128
-	if (!plane || !plane->dev)
129
-		return NULL;
130
-	priv = plane->dev->dev_private;
131
-	if (!priv)
132
-		return NULL;
133
131
 	return to_dpu_kms(priv->kms);
134
132
 }
135
133
 
136
-static bool dpu_plane_enabled(struct drm_plane_state *state)
134
+/**
135
+ * _dpu_plane_calc_bw - calculate bandwidth required for a plane
136
+ * @Plane: Pointer to drm plane.
137
+ * Result: Updates calculated bandwidth in the plane state.
138
+ * BW Equation: src_w * src_h * bpp * fps * (v_total / v_dest)
139
+ * Prefill BW Equation: line src bytes * line_time
140
+ */
141
+static void _dpu_plane_calc_bw(struct drm_plane *plane,
142
+	struct drm_framebuffer *fb)
137
143
 {
138
-	return state && state->fb && state->crtc;
144
+	struct dpu_plane *pdpu = to_dpu_plane(plane);
145
+	struct dpu_plane_state *pstate;
146
+	struct drm_display_mode *mode;
147
+	const struct dpu_format *fmt = NULL;
148
+	struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
149
+	int src_width, src_height, dst_height, fps;
150
+	u64 plane_prefill_bw;
151
+	u64 plane_bw;
152
+	u32 hw_latency_lines;
153
+	u64 scale_factor;
154
+	int vbp, vpw;
155
+
156
+	pstate = to_dpu_plane_state(plane->state);
157
+	mode = &plane->state->crtc->mode;
158
+
159
+	fmt = dpu_get_dpu_format_ext(fb->format->format, fb->modifier);
160
+
161
+	src_width = drm_rect_width(&pdpu->pipe_cfg.src_rect);
162
+	src_height = drm_rect_height(&pdpu->pipe_cfg.src_rect);
163
+	dst_height = drm_rect_height(&pdpu->pipe_cfg.dst_rect);
164
+	fps = drm_mode_vrefresh(mode);
165
+	vbp = mode->vtotal - mode->vsync_end;
166
+	vpw = mode->vsync_end - mode->vsync_start;
167
+	hw_latency_lines =  dpu_kms->catalog->perf.min_prefill_lines;
168
+	scale_factor = src_height > dst_height ?
169
+		mult_frac(src_height, 1, dst_height) : 1;
170
+
171
+	plane_bw =
172
+		src_width * mode->vtotal * fps * fmt->bpp *
173
+		scale_factor;
174
+
175
+	plane_prefill_bw =
176
+		src_width * hw_latency_lines * fps * fmt->bpp *
177
+		scale_factor * mode->vtotal;
178
+
179
+	do_div(plane_prefill_bw, (vbp+vpw));
180
+
181
+	pstate->plane_fetch_bw = max(plane_bw, plane_prefill_bw);
139
182
 }
140
183
 
141
-static bool dpu_plane_sspp_enabled(struct drm_plane_state *state)
184
+/**
185
+ * _dpu_plane_calc_clk - calculate clock required for a plane
186
+ * @Plane: Pointer to drm plane.
187
+ * Result: Updates calculated clock in the plane state.
188
+ * Clock equation: dst_w * v_total * fps * (src_h / dst_h)
189
+ */
190
+static void _dpu_plane_calc_clk(struct drm_plane *plane)
142
191
 {
143
-	return state && state->crtc;
192
+	struct dpu_plane *pdpu = to_dpu_plane(plane);
193
+	struct dpu_plane_state *pstate;
194
+	struct drm_display_mode *mode;
195
+	int dst_width, src_height, dst_height, fps;
196
+
197
+	pstate = to_dpu_plane_state(plane->state);
198
+	mode = &plane->state->crtc->mode;
199
+
200
+	src_height = drm_rect_height(&pdpu->pipe_cfg.src_rect);
201
+	dst_width = drm_rect_width(&pdpu->pipe_cfg.dst_rect);
202
+	dst_height = drm_rect_height(&pdpu->pipe_cfg.dst_rect);
203
+	fps = drm_mode_vrefresh(mode);
204
+
205
+	pstate->plane_clk =
206
+		dst_width * mode->vtotal * fps;
207
+
208
+	if (src_height > dst_height) {
209
+		pstate->plane_clk *= src_height;
210
+		do_div(pstate->plane_clk, dst_height);
211
+	}
144
212
 }
145
213
 
146
214
 /**
..
..
@@ -150,7 +218,7 @@
150
218
  * @src_wdith:		width of source buffer
151
219
  * Return: fill level corresponding to the source buffer/format or 0 if error
152
220
  */
153
-static inline int _dpu_plane_calc_fill_level(struct drm_plane *plane,
221
+static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
154
222
 		const struct dpu_format *fmt, u32 src_width)
155
223
 {
156
224
 	struct dpu_plane *pdpu, *tmp;
..
..
@@ -158,17 +226,17 @@
158
226
 	u32 fixed_buff_size;
159
227
 	u32 total_fl;
160
228
 
161
-	if (!plane || !fmt || !plane->state || !src_width || !fmt->bpp) {
229
+	if (!fmt || !plane->state || !src_width || !fmt->bpp) {
162
230
 		DPU_ERROR("invalid arguments\n");
163
231
 		return 0;
164
232
 	}
165
233
 
166
234
 	pdpu = to_dpu_plane(plane);
167
235
 	pstate = to_dpu_plane_state(plane->state);
168
-	fixed_buff_size = pdpu->pipe_sblk->common->pixel_ram_size;
236
+	fixed_buff_size = pdpu->catalog->caps->pixel_ram_size;
169
237
 
170
238
 	list_for_each_entry(tmp, &pdpu->mplane_list, mplane_list) {
171
-		if (!dpu_plane_enabled(tmp->base.state))
239
+		if (!tmp->base.state->visible)
172
240
 			continue;
173
241
 		DPU_DEBUG("plane%d/%d src_width:%d/%d\n",
174
242
 				pdpu->base.base.id, tmp->base.base.id,
..
..
@@ -239,25 +307,10 @@
239
307
 static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
240
308
 		struct drm_framebuffer *fb)
241
309
 {
242
-	struct dpu_plane *pdpu;
310
+	struct dpu_plane *pdpu = to_dpu_plane(plane);
243
311
 	const struct dpu_format *fmt = NULL;
244
312
 	u64 qos_lut;
245
313
 	u32 total_fl = 0, lut_usage;
246
-
247
-	if (!plane || !fb) {
248
-		DPU_ERROR("invalid arguments plane %d fb %d\n",
249
-				plane != 0, fb != 0);
250
-		return;
251
-	}
252
-
253
-	pdpu = to_dpu_plane(plane);
254
-
255
-	if (!pdpu->pipe_hw || !pdpu->pipe_sblk || !pdpu->catalog) {
256
-		DPU_ERROR("invalid arguments\n");
257
-		return;
258
-	} else if (!pdpu->pipe_hw->ops.setup_creq_lut) {
259
-		return;
260
-	}
261
314
 
262
315
 	if (!pdpu->is_rt_pipe) {
263
316
 		lut_usage = DPU_QOS_LUT_USAGE_NRT;
..
..
@@ -300,23 +353,9 @@
300
353
 static void _dpu_plane_set_danger_lut(struct drm_plane *plane,
301
354
 		struct drm_framebuffer *fb)
302
355
 {
303
-	struct dpu_plane *pdpu;
356
+	struct dpu_plane *pdpu = to_dpu_plane(plane);
304
357
 	const struct dpu_format *fmt = NULL;
305
358
 	u32 danger_lut, safe_lut;
306
-
307
-	if (!plane || !fb) {
308
-		DPU_ERROR("invalid arguments\n");
309
-		return;
310
-	}
311
-
312
-	pdpu = to_dpu_plane(plane);
313
-
314
-	if (!pdpu->pipe_hw || !pdpu->pipe_sblk || !pdpu->catalog) {
315
-		DPU_ERROR("invalid arguments\n");
316
-		return;
317
-	} else if (!pdpu->pipe_hw->ops.setup_danger_safe_lut) {
318
-		return;
319
-	}
320
359
 
321
360
 	if (!pdpu->is_rt_pipe) {
322
361
 		danger_lut = pdpu->catalog->perf.danger_lut_tbl
..
..
@@ -371,21 +410,7 @@
371
410
 static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
372
411
 	bool enable, u32 flags)
373
412
 {
374
-	struct dpu_plane *pdpu;
375
-
376
-	if (!plane) {
377
-		DPU_ERROR("invalid arguments\n");
378
-		return;
379
-	}
380
-
381
-	pdpu = to_dpu_plane(plane);
382
-
383
-	if (!pdpu->pipe_hw || !pdpu->pipe_sblk) {
384
-		DPU_ERROR("invalid arguments\n");
385
-		return;
386
-	} else if (!pdpu->pipe_hw->ops.setup_qos_ctrl) {
387
-		return;
388
-	}
413
+	struct dpu_plane *pdpu = to_dpu_plane(plane);
389
414
 
390
415
 	if (flags & DPU_PLANE_QOS_VBLANK_CTRL) {
391
416
 		pdpu->pipe_qos_cfg.creq_vblank = pdpu->pipe_sblk->creq_vblank;
..
..
@@ -421,37 +446,6 @@
421
446
 			&pdpu->pipe_qos_cfg);
422
447
 }
423
448
 
424
-int dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
425
-{
426
-	struct dpu_plane *pdpu;
427
-	struct msm_drm_private *priv;
428
-	struct dpu_kms *dpu_kms;
429
-
430
-	if (!plane || !plane->dev) {
431
-		DPU_ERROR("invalid arguments\n");
432
-		return -EINVAL;
433
-	}
434
-
435
-	priv = plane->dev->dev_private;
436
-	if (!priv || !priv->kms) {
437
-		DPU_ERROR("invalid KMS reference\n");
438
-		return -EINVAL;
439
-	}
440
-
441
-	dpu_kms = to_dpu_kms(priv->kms);
442
-	pdpu = to_dpu_plane(plane);
443
-
444
-	if (!pdpu->is_rt_pipe)
445
-		goto end;
446
-
447
-	pm_runtime_get_sync(&dpu_kms->pdev->dev);
448
-	_dpu_plane_set_qos_ctrl(plane, enable, DPU_PLANE_QOS_PANIC_CTRL);
449
-	pm_runtime_put_sync(&dpu_kms->pdev->dev);
450
-
451
-end:
452
-	return 0;
453
-}
454
-
455
449
 /**
456
450
  * _dpu_plane_set_ot_limit - set OT limit for the given plane
457
451
  * @plane:		Pointer to drm plane
..
..
@@ -460,29 +454,9 @@
460
454
 static void _dpu_plane_set_ot_limit(struct drm_plane *plane,
461
455
 		struct drm_crtc *crtc)
462
456
 {
463
-	struct dpu_plane *pdpu;
457
+	struct dpu_plane *pdpu = to_dpu_plane(plane);
464
458
 	struct dpu_vbif_set_ot_params ot_params;
465
-	struct msm_drm_private *priv;
466
-	struct dpu_kms *dpu_kms;
467
-
468
-	if (!plane || !plane->dev || !crtc) {
469
-		DPU_ERROR("invalid arguments plane %d crtc %d\n",
470
-				plane != 0, crtc != 0);
471
-		return;
472
-	}
473
-
474
-	priv = plane->dev->dev_private;
475
-	if (!priv || !priv->kms) {
476
-		DPU_ERROR("invalid KMS reference\n");
477
-		return;
478
-	}
479
-
480
-	dpu_kms = to_dpu_kms(priv->kms);
481
-	pdpu = to_dpu_plane(plane);
482
-	if (!pdpu->pipe_hw) {
483
-		DPU_ERROR("invalid pipe reference\n");
484
-		return;
485
-	}
459
+	struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
486
460
 
487
461
 	memset(&ot_params, 0, sizeof(ot_params));
488
462
 	ot_params.xin_id = pdpu->pipe_hw->cap->xin_id;
..
..
@@ -490,7 +464,7 @@
490
464
 	ot_params.width = drm_rect_width(&pdpu->pipe_cfg.src_rect);
491
465
 	ot_params.height = drm_rect_height(&pdpu->pipe_cfg.src_rect);
492
466
 	ot_params.is_wfd = !pdpu->is_rt_pipe;
493
-	ot_params.frame_rate = crtc->mode.vrefresh;
467
+	ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode);
494
468
 	ot_params.vbif_idx = VBIF_RT;
495
469
 	ot_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl;
496
470
 	ot_params.rd = true;
..
..
@@ -504,28 +478,9 @@
504
478
  */
505
479
 static void _dpu_plane_set_qos_remap(struct drm_plane *plane)
506
480
 {
507
-	struct dpu_plane *pdpu;
481
+	struct dpu_plane *pdpu = to_dpu_plane(plane);
508
482
 	struct dpu_vbif_set_qos_params qos_params;
509
-	struct msm_drm_private *priv;
510
-	struct dpu_kms *dpu_kms;
511
-
512
-	if (!plane || !plane->dev) {
513
-		DPU_ERROR("invalid arguments\n");
514
-		return;
515
-	}
516
-
517
-	priv = plane->dev->dev_private;
518
-	if (!priv || !priv->kms) {
519
-		DPU_ERROR("invalid KMS reference\n");
520
-		return;
521
-	}
522
-
523
-	dpu_kms = to_dpu_kms(priv->kms);
524
-	pdpu = to_dpu_plane(plane);
525
-	if (!pdpu->pipe_hw) {
526
-		DPU_ERROR("invalid pipe reference\n");
527
-		return;
528
-	}
483
+	struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
529
484
 
530
485
 	memset(&qos_params, 0, sizeof(qos_params));
531
486
 	qos_params.vbif_idx = VBIF_RT;
..
..
@@ -543,59 +498,15 @@
543
498
 	dpu_vbif_set_qos_remap(dpu_kms, &qos_params);
544
499
 }
545
500
 
546
-/**
547
- * _dpu_plane_get_aspace: gets the address space
548
- */
549
-static int _dpu_plane_get_aspace(
550
-		struct dpu_plane *pdpu,
551
-		struct dpu_plane_state *pstate,
552
-		struct msm_gem_address_space **aspace)
553
-{
554
-	struct dpu_kms *kms;
555
-
556
-	if (!pdpu || !pstate || !aspace) {
557
-		DPU_ERROR("invalid parameters\n");
558
-		return -EINVAL;
559
-	}
560
-
561
-	kms = _dpu_plane_get_kms(&pdpu->base);
562
-	if (!kms) {
563
-		DPU_ERROR("invalid kms\n");
564
-		return -EINVAL;
565
-	}
566
-
567
-	*aspace = kms->base.aspace;
568
-
569
-	return 0;
570
-}
571
-
572
-static inline void _dpu_plane_set_scanout(struct drm_plane *plane,
501
+static void _dpu_plane_set_scanout(struct drm_plane *plane,
573
502
 		struct dpu_plane_state *pstate,
574
503
 		struct dpu_hw_pipe_cfg *pipe_cfg,
575
504
 		struct drm_framebuffer *fb)
576
505
 {
577
-	struct dpu_plane *pdpu;
578
-	struct msm_gem_address_space *aspace = NULL;
506
+	struct dpu_plane *pdpu = to_dpu_plane(plane);
507
+	struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
508
+	struct msm_gem_address_space *aspace = kms->base.aspace;
579
509
 	int ret;
580
-
581
-	if (!plane || !pstate || !pipe_cfg || !fb) {
582
-		DPU_ERROR(
583
-			"invalid arg(s), plane %d state %d cfg %d fb %d\n",
584
-			plane != 0, pstate != 0, pipe_cfg != 0, fb != 0);
585
-		return;
586
-	}
587
-
588
-	pdpu = to_dpu_plane(plane);
589
-	if (!pdpu->pipe_hw) {
590
-		DPU_ERROR_PLANE(pdpu, "invalid pipe_hw\n");
591
-		return;
592
-	}
593
-
594
-	ret = _dpu_plane_get_aspace(pdpu, pstate, &aspace);
595
-	if (ret) {
596
-		DPU_ERROR_PLANE(pdpu, "Failed to get aspace %d\n", ret);
597
-		return;
598
-	}
599
510
 
600
511
 	ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout);
601
512
 	if (ret == -EAGAIN)
..
..
@@ -619,15 +530,6 @@
619
530
 		uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
620
531
 {
621
532
 	uint32_t i;
622
-
623
-	if (!pdpu || !pstate || !scale_cfg || !fmt || !chroma_subsmpl_h ||
624
-			!chroma_subsmpl_v) {
625
-		DPU_ERROR(
626
-			"pdpu %d pstate %d scale_cfg %d fmt %d smp_h %d smp_v %d\n",
627
-			!!pdpu, !!pstate, !!scale_cfg, !!fmt, chroma_subsmpl_h,
628
-			chroma_subsmpl_v);
629
-		return;
630
-	}
631
533
 
632
534
 	memset(scale_cfg, 0, sizeof(*scale_cfg));
633
535
 	memset(&pstate->pixel_ext, 0, sizeof(struct dpu_hw_pixel_ext));
..
..
@@ -660,8 +562,16 @@
660
562
 			scale_cfg->src_width[i] /= chroma_subsmpl_h;
661
563
 			scale_cfg->src_height[i] /= chroma_subsmpl_v;
662
564
 		}
663
-		scale_cfg->preload_x[i] = DPU_QSEED3_DEFAULT_PRELOAD_H;
664
-		scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V;
565
+
566
+		if (pdpu->pipe_hw->cap->features &
567
+			BIT(DPU_SSPP_SCALER_QSEED4)) {
568
+			scale_cfg->preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H;
569
+			scale_cfg->preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V;
570
+		} else {
571
+			scale_cfg->preload_x[i] = DPU_QSEED3_DEFAULT_PRELOAD_H;
572
+			scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V;
573
+		}
574
+
665
575
 		pstate->pixel_ext.num_ext_pxls_top[i] =
666
576
 			scale_cfg->src_height[i];
667
577
 		pstate->pixel_ext.num_ext_pxls_left[i] =
..
..
@@ -681,7 +591,7 @@
681
591
 	scale_cfg->enable = 1;
682
592
 }
683
593
 
684
-static inline void _dpu_plane_setup_csc(struct dpu_plane *pdpu)
594
+static void _dpu_plane_setup_csc(struct dpu_plane *pdpu)
685
595
 {
686
596
 	static const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L = {
687
597
 		{
..
..
@@ -732,23 +642,9 @@
732
642
 		struct dpu_plane_state *pstate,
733
643
 		const struct dpu_format *fmt, bool color_fill)
734
644
 {
735
-	struct dpu_hw_pixel_ext *pe;
736
-	uint32_t chroma_subsmpl_h, chroma_subsmpl_v;
737
-
738
-	if (!pdpu || !fmt || !pstate) {
739
-		DPU_ERROR("invalid arg(s), plane %d fmt %d state %d\n",
740
-				pdpu != 0, fmt != 0, pstate != 0);
741
-		return;
742
-	}
743
-
744
-	pe = &pstate->pixel_ext;
645
+	const struct drm_format_info *info = drm_format_info(fmt->base.pixel_format);
745
646
 
746
647
 	/* don't chroma subsample if decimating */
747
-	chroma_subsmpl_h =
748
-		drm_format_horz_chroma_subsampling(fmt->base.pixel_format);
749
-	chroma_subsmpl_v =
750
-		drm_format_vert_chroma_subsampling(fmt->base.pixel_format);
751
-
752
648
 	/* update scaler. calculate default config for QSEED3 */
753
649
 	_dpu_plane_setup_scaler3(pdpu, pstate,
754
650
 			drm_rect_width(&pdpu->pipe_cfg.src_rect),
..
..
@@ -756,7 +652,7 @@
756
652
 			drm_rect_width(&pdpu->pipe_cfg.dst_rect),
757
653
 			drm_rect_height(&pdpu->pipe_cfg.dst_rect),
758
654
 			&pstate->scaler3_cfg, fmt,
759
-			chroma_subsmpl_h, chroma_subsmpl_v);
655
+			info->hsub, info->vsub);
760
656
 }
761
657
 
762
658
 /**
..
..
@@ -770,21 +666,8 @@
770
666
 		uint32_t color, uint32_t alpha)
771
667
 {
772
668
 	const struct dpu_format *fmt;
773
-	const struct drm_plane *plane;
774
-	struct dpu_plane_state *pstate;
775
-
776
-	if (!pdpu || !pdpu->base.state) {
777
-		DPU_ERROR("invalid plane\n");
778
-		return -EINVAL;
779
-	}
780
-
781
-	if (!pdpu->pipe_hw) {
782
-		DPU_ERROR_PLANE(pdpu, "invalid plane h/w pointer\n");
783
-		return -EINVAL;
784
-	}
785
-
786
-	plane = &pdpu->base;
787
-	pstate = to_dpu_plane_state(plane->state);
669
+	const struct drm_plane *plane = &pdpu->base;
670
+	struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
788
671
 
789
672
 	DPU_DEBUG_PLANE(pdpu, "\n");
790
673
 
..
..
@@ -835,12 +718,7 @@
835
718
 
836
719
 void dpu_plane_clear_multirect(const struct drm_plane_state *drm_state)
837
720
 {
838
-	struct dpu_plane_state *pstate;
839
-
840
-	if (!drm_state)
841
-		return;
842
-
843
-	pstate = to_dpu_plane_state(drm_state);
721
+	struct dpu_plane_state *pstate = to_dpu_plane_state(drm_state);
844
722
 
845
723
 	pstate->multirect_index = DPU_SSPP_RECT_SOLO;
846
724
 	pstate->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
..
..
@@ -911,7 +789,7 @@
911
789
 		 * So we cannot support more than half of the supported SSPP
912
790
 		 * width for tiled formats.
913
791
 		 */
914
-		width_threshold = dpu_plane[i]->pipe_sblk->common->maxlinewidth;
792
+		width_threshold = dpu_plane[i]->catalog->caps->max_linewidth;
915
793
 		if (has_tiled_rect)
916
794
 			width_threshold /= 2;
917
795
 
..
..
@@ -953,7 +831,7 @@
953
831
 	} else {
954
832
 		pstate[R0]->multirect_index = DPU_SSPP_RECT_0;
955
833
 		pstate[R1]->multirect_index = DPU_SSPP_RECT_1;
956
-	};
834
+	}
957
835
 
958
836
 	DPU_DEBUG_PLANE(dpu_plane[R0], "R0: %d - %d\n",
959
837
 		pstate[R0]->multirect_mode, pstate[R0]->multirect_index);
..
..
@@ -971,15 +849,6 @@
971
849
 void dpu_plane_get_ctl_flush(struct drm_plane *plane, struct dpu_hw_ctl *ctl,
972
850
 		u32 *flush_sspp)
973
851
 {
974
-	struct dpu_plane_state *pstate;
975
-
976
-	if (!plane || !flush_sspp) {
977
-		DPU_ERROR("invalid parameters\n");
978
-		return;
979
-	}
980
-
981
-	pstate = to_dpu_plane_state(plane->state);
982
-
983
852
 	*flush_sspp = ctl->ops.get_bitmask_sspp(ctl, dpu_plane_pipe(plane));
984
853
 }
985
854
 
..
..
@@ -990,10 +859,7 @@
990
859
 	struct dpu_plane *pdpu = to_dpu_plane(plane);
991
860
 	struct dpu_plane_state *pstate = to_dpu_plane_state(new_state);
992
861
 	struct dpu_hw_fmt_layout layout;
993
-	struct drm_gem_object *obj;
994
-	struct msm_gem_object *msm_obj;
995
-	struct dma_fence *fence;
996
-	struct msm_gem_address_space *aspace;
862
+	struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
997
863
 	int ret;
998
864
 
999
865
 	if (!new_state->fb)
..
..
@@ -1001,25 +867,15 @@
1001
867
 
1002
868
 	DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", fb->base.id);
1003
869
 
1004
-	ret = _dpu_plane_get_aspace(pdpu, pstate, &aspace);
1005
-	if (ret) {
1006
-		DPU_ERROR_PLANE(pdpu, "Failed to get aspace\n");
1007
-		return ret;
1008
-	}
1009
-
1010
870
 	/* cache aspace */
1011
-	pstate->aspace = aspace;
871
+	pstate->aspace = kms->base.aspace;
1012
872
 
1013
873
 	/*
1014
874
 	 * TODO: Need to sort out the msm_framebuffer_prepare() call below so
1015
875
 	 *       we can use msm_atomic_prepare_fb() instead of doing the
1016
876
 	 *       implicit fence and fb prepare by hand here.
1017
877
 	 */
1018
-	obj = msm_framebuffer_bo(new_state->fb, 0);
1019
-	msm_obj = to_msm_bo(obj);
1020
-	fence = reservation_object_get_excl_rcu(msm_obj->resv);
1021
-	if (fence)
1022
-		drm_atomic_set_fence_for_plane(new_state, fence);
878
+	drm_gem_fb_prepare_fb(plane, new_state);
1023
879
 
1024
880
 	if (pstate->aspace) {
1025
881
 		ret = msm_framebuffer_prepare(new_state->fb,
..
..
@@ -1076,33 +932,30 @@
1076
932
 		drm_rect_equals(fb_rect, src);
1077
933
 }
1078
934
 
1079
-static int dpu_plane_sspp_atomic_check(struct drm_plane *plane,
1080
-		struct drm_plane_state *state)
935
+static int dpu_plane_atomic_check(struct drm_plane *plane,
936
+				  struct drm_plane_state *state)
1081
937
 {
1082
-	int ret = 0;
1083
-	struct dpu_plane *pdpu;
1084
-	struct dpu_plane_state *pstate;
938
+	int ret = 0, min_scale;
939
+	struct dpu_plane *pdpu = to_dpu_plane(plane);
940
+	const struct drm_crtc_state *crtc_state = NULL;
1085
941
 	const struct dpu_format *fmt;
1086
942
 	struct drm_rect src, dst, fb_rect = { 0 };
1087
-	uint32_t max_upscale = 1, max_downscale = 1;
1088
943
 	uint32_t min_src_size, max_linewidth;
1089
-	int hscale = 1, vscale = 1;
1090
944
 
1091
-	if (!plane || !state) {
1092
-		DPU_ERROR("invalid arg(s), plane %d state %d\n",
1093
-				plane != 0, state != 0);
1094
-		ret = -EINVAL;
1095
-		goto exit;
945
+	if (state->crtc)
946
+		crtc_state = drm_atomic_get_new_crtc_state(state->state,
947
+							   state->crtc);
948
+
949
+	min_scale = FRAC_16_16(1, pdpu->pipe_sblk->maxupscale);
950
+	ret = drm_atomic_helper_check_plane_state(state, crtc_state, min_scale,
951
+					  pdpu->pipe_sblk->maxdwnscale << 16,
952
+					  true, true);
953
+	if (ret) {
954
+		DPU_DEBUG_PLANE(pdpu, "Check plane state failed (%d)\n", ret);
955
+		return ret;
1096
956
 	}
1097
-
1098
-	pdpu = to_dpu_plane(plane);
1099
-	pstate = to_dpu_plane_state(state);
1100
-
1101
-	if (!pdpu->pipe_sblk) {
1102
-		DPU_ERROR_PLANE(pdpu, "invalid catalog\n");
1103
-		ret = -EINVAL;
1104
-		goto exit;
1105
-	}
957
+	if (!state->visible)
958
+		return 0;
1106
959
 
1107
960
 	src.x1 = state->src_x >> 16;
1108
961
 	src.y1 = state->src_y >> 16;
..
..
@@ -1114,26 +967,7 @@
1114
967
 	fb_rect.x2 = state->fb->width;
1115
968
 	fb_rect.y2 = state->fb->height;
1116
969
 
1117
-	max_linewidth = pdpu->pipe_sblk->common->maxlinewidth;
1118
-
1119
-	if (pdpu->features & DPU_SSPP_SCALER) {
1120
-		max_downscale = pdpu->pipe_sblk->maxdwnscale;
1121
-		max_upscale = pdpu->pipe_sblk->maxupscale;
1122
-	}
1123
-	if (drm_rect_width(&src) < drm_rect_width(&dst))
1124
-		hscale = drm_rect_calc_hscale(&src, &dst, 1, max_upscale);
1125
-	else
1126
-		hscale = drm_rect_calc_hscale(&dst, &src, 1, max_downscale);
1127
-	if (drm_rect_height(&src) < drm_rect_height(&dst))
1128
-		vscale = drm_rect_calc_vscale(&src, &dst, 1, max_upscale);
1129
-	else
1130
-		vscale = drm_rect_calc_vscale(&dst, &src, 1, max_downscale);
1131
-
1132
-	DPU_DEBUG_PLANE(pdpu, "check %d -> %d\n",
1133
-		dpu_plane_enabled(plane->state), dpu_plane_enabled(state));
1134
-
1135
-	if (!dpu_plane_enabled(state))
1136
-		goto exit;
970
+	max_linewidth = pdpu->catalog->caps->max_linewidth;
1137
971
 
1138
972
 	fmt = to_dpu_format(msm_framebuffer_format(state->fb));
1139
973
 
..
..
@@ -1143,58 +977,39 @@
1143
977
 		(!(pdpu->features & DPU_SSPP_SCALER) ||
1144
978
 		 !(pdpu->features & (BIT(DPU_SSPP_CSC)
1145
979
 		 | BIT(DPU_SSPP_CSC_10BIT))))) {
1146
-		DPU_ERROR_PLANE(pdpu,
980
+		DPU_DEBUG_PLANE(pdpu,
1147
981
 				"plane doesn't have scaler/csc for yuv\n");
1148
-		ret = -EINVAL;
982
+		return -EINVAL;
1149
983
 
1150
984
 	/* check src bounds */
1151
985
 	} else if (!dpu_plane_validate_src(&src, &fb_rect, min_src_size)) {
1152
-		DPU_ERROR_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n",
986
+		DPU_DEBUG_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n",
1153
987
 				DRM_RECT_ARG(&src));
1154
-		ret = -E2BIG;
988
+		return -E2BIG;
1155
989
 
1156
990
 	/* valid yuv image */
1157
991
 	} else if (DPU_FORMAT_IS_YUV(fmt) &&
1158
992
 		   (src.x1 & 0x1 || src.y1 & 0x1 ||
1159
993
 		    drm_rect_width(&src) & 0x1 ||
1160
994
 		    drm_rect_height(&src) & 0x1)) {
1161
-		DPU_ERROR_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n",
995
+		DPU_DEBUG_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n",
1162
996
 				DRM_RECT_ARG(&src));
1163
-		ret = -EINVAL;
997
+		return -EINVAL;
1164
998
 
1165
999
 	/* min dst support */
1166
1000
 	} else if (drm_rect_width(&dst) < 0x1 || drm_rect_height(&dst) < 0x1) {
1167
-		DPU_ERROR_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n",
1001
+		DPU_DEBUG_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n",
1168
1002
 				DRM_RECT_ARG(&dst));
1169
-		ret = -EINVAL;
1003
+		return -EINVAL;
1170
1004
 
1171
1005
 	/* check decimated source width */
1172
1006
 	} else if (drm_rect_width(&src) > max_linewidth) {
1173
-		DPU_ERROR_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n",
1007
+		DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n",
1174
1008
 				DRM_RECT_ARG(&src), max_linewidth);
1175
-		ret = -E2BIG;
1176
-
1177
-	/* check scaler capability */
1178
-	} else if (hscale < 0 || vscale < 0) {
1179
-		DPU_ERROR_PLANE(pdpu, "invalid scaling requested src="
1180
-				DRM_RECT_FMT " dst=" DRM_RECT_FMT "\n",
1181
-				DRM_RECT_ARG(&src), DRM_RECT_ARG(&dst));
1182
-		ret = -E2BIG;
1009
+		return -E2BIG;
1183
1010
 	}
1184
1011
 
1185
-exit:
1186
-	return ret;
1187
-}
1188
-
1189
-static int dpu_plane_atomic_check(struct drm_plane *plane,
1190
-		struct drm_plane_state *state)
1191
-{
1192
-	if (!state->fb)
1193
-		return 0;
1194
-
1195
-	DPU_DEBUG_PLANE(to_dpu_plane(plane), "\n");
1196
-
1197
-	return dpu_plane_sspp_atomic_check(plane, state);
1012
+	return 0;
1198
1013
 }
1199
1014
 
1200
1015
 void dpu_plane_flush(struct drm_plane *plane)
..
..
@@ -1243,46 +1058,16 @@
1243
1058
 	pdpu->is_error = error;
1244
1059
 }
1245
1060
 
1246
-static int dpu_plane_sspp_atomic_update(struct drm_plane *plane,
1247
-				struct drm_plane_state *old_state)
1061
+static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
1248
1062
 {
1249
-	uint32_t nplanes, src_flags;
1250
-	struct dpu_plane *pdpu;
1251
-	struct drm_plane_state *state;
1252
-	struct dpu_plane_state *pstate;
1253
-	struct dpu_plane_state *old_pstate;
1254
-	const struct dpu_format *fmt;
1255
-	struct drm_crtc *crtc;
1256
-	struct drm_framebuffer *fb;
1257
-	int ret, min_scale;
1258
-
1259
-	if (!plane) {
1260
-		DPU_ERROR("invalid plane\n");
1261
-		return -EINVAL;
1262
-	} else if (!plane->state) {
1263
-		DPU_ERROR("invalid plane state\n");
1264
-		return -EINVAL;
1265
-	} else if (!old_state) {
1266
-		DPU_ERROR("invalid old state\n");
1267
-		return -EINVAL;
1268
-	}
1269
-
1270
-	pdpu = to_dpu_plane(plane);
1271
-	state = plane->state;
1272
-
1273
-	pstate = to_dpu_plane_state(state);
1274
-
1275
-	old_pstate = to_dpu_plane_state(old_state);
1276
-
1277
-	crtc = state->crtc;
1278
-	fb = state->fb;
1279
-	if (!crtc || !fb) {
1280
-		DPU_ERROR_PLANE(pdpu, "invalid crtc %d or fb %d\n",
1281
-				crtc != 0, fb != 0);
1282
-		return -EINVAL;
1283
-	}
1284
-	fmt = to_dpu_format(msm_framebuffer_format(fb));
1285
-	nplanes = fmt->num_planes;
1063
+	uint32_t src_flags;
1064
+	struct dpu_plane *pdpu = to_dpu_plane(plane);
1065
+	struct drm_plane_state *state = plane->state;
1066
+	struct dpu_plane_state *pstate = to_dpu_plane_state(state);
1067
+	struct drm_crtc *crtc = state->crtc;
1068
+	struct drm_framebuffer *fb = state->fb;
1069
+	const struct dpu_format *fmt =
1070
+		to_dpu_format(msm_framebuffer_format(fb));
1286
1071
 
1287
1072
 	memset(&(pdpu->pipe_cfg), 0, sizeof(struct dpu_hw_pipe_cfg));
1288
1073
 
..
..
@@ -1292,15 +1077,6 @@
1292
1077
 
1293
1078
 	pdpu->is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT);
1294
1079
 	_dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL);
1295
-
1296
-	min_scale = FRAC_16_16(1, pdpu->pipe_sblk->maxdwnscale);
1297
-	ret = drm_atomic_helper_check_plane_state(state, crtc->state, min_scale,
1298
-					  pdpu->pipe_sblk->maxupscale << 16,
1299
-					  true, false);
1300
-	if (ret) {
1301
-		DPU_ERROR_PLANE(pdpu, "Check plane state failed (%d)\n", ret);
1302
-		return ret;
1303
-	}
1304
1080
 
1305
1081
 	DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT
1306
1082
 			", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src),
..
..
@@ -1322,7 +1098,7 @@
1322
1098
 	/* override for color fill */
1323
1099
 	if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) {
1324
1100
 		/* skip remaining processing on color fill */
1325
-		return 0;
1101
+		return;
1326
1102
 	}
1327
1103
 
1328
1104
 	if (pdpu->pipe_hw->ops.setup_rects) {
..
..
@@ -1354,7 +1130,20 @@
1354
1130
 				pstate->multirect_mode);
1355
1131
 
1356
1132
 	if (pdpu->pipe_hw->ops.setup_format) {
1133
+		unsigned int rotation;
1134
+
1357
1135
 		src_flags = 0x0;
1136
+
1137
+		rotation = drm_rotation_simplify(state->rotation,
1138
+						 DRM_MODE_ROTATE_0 |
1139
+						 DRM_MODE_REFLECT_X |
1140
+						 DRM_MODE_REFLECT_Y);
1141
+
1142
+		if (rotation & DRM_MODE_REFLECT_X)
1143
+			src_flags |= DPU_SSPP_FLIP_LR;
1144
+
1145
+		if (rotation & DRM_MODE_REFLECT_Y)
1146
+			src_flags |= DPU_SSPP_FLIP_UD;
1358
1147
 
1359
1148
 		/* update format */
1360
1149
 		pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, fmt, src_flags,
..
..
@@ -1393,30 +1182,17 @@
1393
1182
 	}
1394
1183
 
1395
1184
 	_dpu_plane_set_qos_remap(plane);
1396
-	return 0;
1185
+
1186
+	_dpu_plane_calc_bw(plane, fb);
1187
+
1188
+	_dpu_plane_calc_clk(plane);
1397
1189
 }
1398
1190
 
1399
-static void _dpu_plane_atomic_disable(struct drm_plane *plane,
1400
-				struct drm_plane_state *old_state)
1191
+static void _dpu_plane_atomic_disable(struct drm_plane *plane)
1401
1192
 {
1402
-	struct dpu_plane *pdpu;
1403
-	struct drm_plane_state *state;
1404
-	struct dpu_plane_state *pstate;
1405
-
1406
-	if (!plane) {
1407
-		DPU_ERROR("invalid plane\n");
1408
-		return;
1409
-	} else if (!plane->state) {
1410
-		DPU_ERROR("invalid plane state\n");
1411
-		return;
1412
-	} else if (!old_state) {
1413
-		DPU_ERROR("invalid old state\n");
1414
-		return;
1415
-	}
1416
-
1417
-	pdpu = to_dpu_plane(plane);
1418
-	state = plane->state;
1419
-	pstate = to_dpu_plane_state(state);
1193
+	struct dpu_plane *pdpu = to_dpu_plane(plane);
1194
+	struct drm_plane_state *state = plane->state;
1195
+	struct dpu_plane_state *pstate = to_dpu_plane_state(state);
1420
1196
 
1421
1197
 	trace_dpu_plane_disable(DRMID(plane), is_dpu_plane_virtual(plane),
1422
1198
 				pstate->multirect_mode);
..
..
@@ -1432,31 +1208,17 @@
1432
1208
 static void dpu_plane_atomic_update(struct drm_plane *plane,
1433
1209
 				struct drm_plane_state *old_state)
1434
1210
 {
1435
-	struct dpu_plane *pdpu;
1436
-	struct drm_plane_state *state;
1211
+	struct dpu_plane *pdpu = to_dpu_plane(plane);
1212
+	struct drm_plane_state *state = plane->state;
1437
1213
 
1438
-	if (!plane) {
1439
-		DPU_ERROR("invalid plane\n");
1440
-		return;
1441
-	} else if (!plane->state) {
1442
-		DPU_ERROR("invalid plane state\n");
1443
-		return;
1444
-	}
1445
-
1446
-	pdpu = to_dpu_plane(plane);
1447
1214
 	pdpu->is_error = false;
1448
-	state = plane->state;
1449
1215
 
1450
1216
 	DPU_DEBUG_PLANE(pdpu, "\n");
1451
1217
 
1452
-	if (!dpu_plane_sspp_enabled(state)) {
1453
-		_dpu_plane_atomic_disable(plane, old_state);
1218
+	if (!state->visible) {
1219
+		_dpu_plane_atomic_disable(plane);
1454
1220
 	} else {
1455
-		int ret;
1456
-
1457
-		ret = dpu_plane_sspp_atomic_update(plane, old_state);
1458
-		/* atomic_check should have ensured that this doesn't fail */
1459
-		WARN_ON(ret < 0);
1221
+		dpu_plane_sspp_atomic_update(plane);
1460
1222
 	}
1461
1223
 }
1462
1224
 
..
..
@@ -1488,13 +1250,10 @@
1488
1250
 
1489
1251
 		mutex_destroy(&pdpu->lock);
1490
1252
 
1491
-		drm_plane_helper_disable(plane, NULL);
1492
-
1493
1253
 		/* this will destroy the states as well */
1494
1254
 		drm_plane_cleanup(plane);
1495
1255
 
1496
-		if (pdpu->pipe_hw)
1497
-			dpu_hw_sspp_destroy(pdpu->pipe_hw);
1256
+		dpu_hw_sspp_destroy(pdpu->pipe_hw);
1498
1257
 
1499
1258
 		kfree(pdpu);
1500
1259
 	}
..
..
@@ -1503,21 +1262,8 @@
1503
1262
 static void dpu_plane_destroy_state(struct drm_plane *plane,
1504
1263
 		struct drm_plane_state *state)
1505
1264
 {
1506
-	struct dpu_plane_state *pstate;
1507
-
1508
-	if (!plane || !state) {
1509
-		DPU_ERROR("invalid arg(s), plane %d state %d\n",
1510
-				plane != 0, state != 0);
1511
-		return;
1512
-	}
1513
-
1514
-	pstate = to_dpu_plane_state(state);
1515
-
1516
-	/* remove ref count for frame buffers */
1517
-	if (state->fb)
1518
-		drm_framebuffer_put(state->fb);
1519
-
1520
-	kfree(pstate);
1265
+	__drm_atomic_helper_plane_destroy_state(state);
1266
+	kfree(to_dpu_plane_state(state));
1521
1267
 }
1522
1268
 
1523
1269
 static struct drm_plane_state *
..
..
@@ -1583,30 +1329,29 @@
1583
1329
 }
1584
1330
 
1585
1331
 #ifdef CONFIG_DEBUG_FS
1332
+static void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
1333
+{
1334
+	struct dpu_plane *pdpu = to_dpu_plane(plane);
1335
+	struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
1336
+
1337
+	if (!pdpu->is_rt_pipe)
1338
+		return;
1339
+
1340
+	pm_runtime_get_sync(&dpu_kms->pdev->dev);
1341
+	_dpu_plane_set_qos_ctrl(plane, enable, DPU_PLANE_QOS_PANIC_CTRL);
1342
+	pm_runtime_put_sync(&dpu_kms->pdev->dev);
1343
+}
1344
+
1586
1345
 static ssize_t _dpu_plane_danger_read(struct file *file,
1587
1346
 			char __user *buff, size_t count, loff_t *ppos)
1588
1347
 {
1589
1348
 	struct dpu_kms *kms = file->private_data;
1590
-	struct dpu_mdss_cfg *cfg = kms->catalog;
1591
-	int len = 0;
1592
-	char buf[40] = {'\0'};
1349
+	int len;
1350
+	char buf[40];
1593
1351
 
1594
-	if (!cfg)
1595
-		return -ENODEV;
1352
+	len = scnprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
1596
1353
 
1597
-	if (*ppos)
1598
-		return 0; /* the end */
1599
-
1600
-	len = snprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
1601
-	if (len < 0 || len >= sizeof(buf))
1602
-		return 0;
1603
-
1604
-	if ((count < sizeof(buf)) || copy_to_user(buff, buf, len))
1605
-		return -EFAULT;
1606
-
1607
-	*ppos += len;   /* increase offset */
1608
-
1609
-	return len;
1354
+	return simple_read_from_buffer(buff, count, ppos, buf, len);
1610
1355
 }
1611
1356
 
1612
1357
 static void _dpu_plane_set_danger_state(struct dpu_kms *kms, bool enable)
..
..
@@ -1636,23 +1381,12 @@
1636
1381
 		    const char __user *user_buf, size_t count, loff_t *ppos)
1637
1382
 {
1638
1383
 	struct dpu_kms *kms = file->private_data;
1639
-	struct dpu_mdss_cfg *cfg = kms->catalog;
1640
1384
 	int disable_panic;
1641
-	char buf[10];
1385
+	int ret;
1642
1386
 
1643
-	if (!cfg)
1644
-		return -EFAULT;
1645
-
1646
-	if (count >= sizeof(buf))
1647
-		return -EFAULT;
1648
-
1649
-	if (copy_from_user(buf, user_buf, count))
1650
-		return -EFAULT;
1651
-
1652
-	buf[count] = 0;	/* end of string */
1653
-
1654
-	if (kstrtoint(buf, 0, &disable_panic))
1655
-		return -EFAULT;
1387
+	ret = kstrtouint_from_user(user_buf, count, 0, &disable_panic);
1388
+	if (ret)
1389
+		return ret;
1656
1390
 
1657
1391
 	if (disable_panic) {
1658
1392
 		/* Disable panic signal for all active pipes */
..
..
@@ -1677,41 +1411,15 @@
1677
1411
 
1678
1412
 static int _dpu_plane_init_debugfs(struct drm_plane *plane)
1679
1413
 {
1680
-	struct dpu_plane *pdpu;
1681
-	struct dpu_kms *kms;
1682
-	struct msm_drm_private *priv;
1683
-	const struct dpu_sspp_sub_blks *sblk = 0;
1684
-	const struct dpu_sspp_cfg *cfg = 0;
1685
-
1686
-	if (!plane || !plane->dev) {
1687
-		DPU_ERROR("invalid arguments\n");
1688
-		return -EINVAL;
1689
-	}
1690
-
1691
-	priv = plane->dev->dev_private;
1692
-	if (!priv || !priv->kms) {
1693
-		DPU_ERROR("invalid KMS reference\n");
1694
-		return -EINVAL;
1695
-	}
1696
-
1697
-	kms = to_dpu_kms(priv->kms);
1698
-	pdpu = to_dpu_plane(plane);
1699
-
1700
-	if (pdpu && pdpu->pipe_hw)
1701
-		cfg = pdpu->pipe_hw->cap;
1702
-	if (cfg)
1703
-		sblk = cfg->sblk;
1704
-
1705
-	if (!sblk)
1706
-		return 0;
1414
+	struct dpu_plane *pdpu = to_dpu_plane(plane);
1415
+	struct dpu_kms *kms = _dpu_plane_get_kms(plane);
1416
+	const struct dpu_sspp_cfg *cfg = pdpu->pipe_hw->cap;
1417
+	const struct dpu_sspp_sub_blks *sblk = cfg->sblk;
1707
1418
 
1708
1419
 	/* create overall sub-directory for the pipe */
1709
1420
 	pdpu->debugfs_root =
1710
1421
 		debugfs_create_dir(pdpu->pipe_name,
1711
1422
 				plane->dev->primary->debugfs_root);
1712
-
1713
-	if (!pdpu->debugfs_root)
1714
-		return -ENOMEM;
1715
1423
 
1716
1424
 	/* don't error check these */
1717
1425
 	debugfs_create_x32("features", 0600,
..
..
@@ -1726,7 +1434,8 @@
1726
1434
 			pdpu->debugfs_root, &pdpu->debugfs_src);
1727
1435
 
1728
1436
 	if (cfg->features & BIT(DPU_SSPP_SCALER_QSEED3) ||
1729
-			cfg->features & BIT(DPU_SSPP_SCALER_QSEED2)) {
1437
+			cfg->features & BIT(DPU_SSPP_SCALER_QSEED2) ||
1438
+			cfg->features & BIT(DPU_SSPP_SCALER_QSEED4)) {
1730
1439
 		dpu_debugfs_setup_regset32(&pdpu->debugfs_scaler,
1731
1440
 				sblk->scaler_blk.base + cfg->base,
1732
1441
 				sblk->scaler_blk.len,
..
..
@@ -1774,24 +1483,10 @@
1774
1483
 
1775
1484
 	return 0;
1776
1485
 }
1777
-
1778
-static void _dpu_plane_destroy_debugfs(struct drm_plane *plane)
1779
-{
1780
-	struct dpu_plane *pdpu;
1781
-
1782
-	if (!plane)
1783
-		return;
1784
-	pdpu = to_dpu_plane(plane);
1785
-
1786
-	debugfs_remove_recursive(pdpu->debugfs_root);
1787
-}
1788
1486
 #else
1789
1487
 static int _dpu_plane_init_debugfs(struct drm_plane *plane)
1790
1488
 {
1791
1489
 	return 0;
1792
-}
1793
-static void _dpu_plane_destroy_debugfs(struct drm_plane *plane)
1794
-{
1795
1490
 }
1796
1491
 #endif
1797
1492
 
..
..
@@ -1802,7 +1497,26 @@
1802
1497
 
1803
1498
 static void dpu_plane_early_unregister(struct drm_plane *plane)
1804
1499
 {
1805
-	_dpu_plane_destroy_debugfs(plane);
1500
+	struct dpu_plane *pdpu = to_dpu_plane(plane);
1501
+
1502
+	debugfs_remove_recursive(pdpu->debugfs_root);
1503
+}
1504
+
1505
+static bool dpu_plane_format_mod_supported(struct drm_plane *plane,
1506
+		uint32_t format, uint64_t modifier)
1507
+{
1508
+	if (modifier == DRM_FORMAT_MOD_LINEAR)
1509
+		return true;
1510
+
1511
+	if (modifier == DRM_FORMAT_MOD_QCOM_COMPRESSED) {
1512
+		int i;
1513
+		for (i = 0; i < ARRAY_SIZE(qcom_compressed_supported_formats); i++) {
1514
+			if (format == qcom_compressed_supported_formats[i])
1515
+				return true;
1516
+		}
1517
+	}
1518
+
1519
+	return false;
1806
1520
 }
1807
1521
 
1808
1522
 static const struct drm_plane_funcs dpu_plane_funcs = {
..
..
@@ -1814,6 +1528,7 @@
1814
1528
 		.atomic_destroy_state = dpu_plane_destroy_state,
1815
1529
 		.late_register = dpu_plane_late_register,
1816
1530
 		.early_unregister = dpu_plane_early_unregister,
1531
+		.format_mod_supported = dpu_plane_format_mod_supported,
1817
1532
 };
1818
1533
 
1819
1534
 static const struct drm_plane_helper_funcs dpu_plane_helper_funcs = {
..
..
@@ -1835,46 +1550,24 @@
1835
1550
 
1836
1551
 /* initialize plane */
1837
1552
 struct drm_plane *dpu_plane_init(struct drm_device *dev,
1838
-		uint32_t pipe, bool primary_plane,
1553
+		uint32_t pipe, enum drm_plane_type type,
1839
1554
 		unsigned long possible_crtcs, u32 master_plane_id)
1840
1555
 {
1841
1556
 	struct drm_plane *plane = NULL, *master_plane = NULL;
1842
-	const struct dpu_format_extended *format_list;
1557
+	const uint32_t *format_list;
1843
1558
 	struct dpu_plane *pdpu;
1844
-	struct msm_drm_private *priv;
1845
-	struct dpu_kms *kms;
1846
-	enum drm_plane_type type;
1559
+	struct msm_drm_private *priv = dev->dev_private;
1560
+	struct dpu_kms *kms = to_dpu_kms(priv->kms);
1847
1561
 	int zpos_max = DPU_ZPOS_MAX;
1562
+	uint32_t num_formats;
1848
1563
 	int ret = -EINVAL;
1849
-
1850
-	if (!dev) {
1851
-		DPU_ERROR("[%u]device is NULL\n", pipe);
1852
-		goto exit;
1853
-	}
1854
-
1855
-	priv = dev->dev_private;
1856
-	if (!priv) {
1857
-		DPU_ERROR("[%u]private data is NULL\n", pipe);
1858
-		goto exit;
1859
-	}
1860
-
1861
-	if (!priv->kms) {
1862
-		DPU_ERROR("[%u]invalid KMS reference\n", pipe);
1863
-		goto exit;
1864
-	}
1865
-	kms = to_dpu_kms(priv->kms);
1866
-
1867
-	if (!kms->catalog) {
1868
-		DPU_ERROR("[%u]invalid catalog reference\n", pipe);
1869
-		goto exit;
1870
-	}
1871
1564
 
1872
1565
 	/* create and zero local structure */
1873
1566
 	pdpu = kzalloc(sizeof(*pdpu), GFP_KERNEL);
1874
1567
 	if (!pdpu) {
1875
1568
 		DPU_ERROR("[%u]failed to allocate local plane struct\n", pipe);
1876
1569
 		ret = -ENOMEM;
1877
-		goto exit;
1570
+		return ERR_PTR(ret);
1878
1571
 	}
1879
1572
 
1880
1573
 	/* cache local stuff for later */
..
..
@@ -1909,30 +1602,18 @@
1909
1602
 		goto clean_sspp;
1910
1603
 	}
1911
1604
 
1912
-	if (!master_plane_id)
1913
-		format_list = pdpu->pipe_sblk->format_list;
1914
-	else
1605
+	if (pdpu->is_virtual) {
1915
1606
 		format_list = pdpu->pipe_sblk->virt_format_list;
1916
-
1917
-	pdpu->nformats = dpu_populate_formats(format_list,
1918
-				pdpu->formats,
1919
-				0,
1920
-				ARRAY_SIZE(pdpu->formats));
1921
-
1922
-	if (!pdpu->nformats) {
1923
-		DPU_ERROR("[%u]no valid formats for plane\n", pipe);
1924
-		goto clean_sspp;
1607
+		num_formats = pdpu->pipe_sblk->virt_num_formats;
1608
+	}
1609
+	else {
1610
+		format_list = pdpu->pipe_sblk->format_list;
1611
+		num_formats = pdpu->pipe_sblk->num_formats;
1925
1612
 	}
1926
1613
 
1927
-	if (pdpu->features & BIT(DPU_SSPP_CURSOR))
1928
-		type = DRM_PLANE_TYPE_CURSOR;
1929
-	else if (primary_plane)
1930
-		type = DRM_PLANE_TYPE_PRIMARY;
1931
-	else
1932
-		type = DRM_PLANE_TYPE_OVERLAY;
1933
1614
 	ret = drm_universal_plane_init(dev, plane, 0xff, &dpu_plane_funcs,
1934
-				pdpu->formats, pdpu->nformats,
1935
-				NULL, type, NULL);
1615
+				format_list, num_formats,
1616
+				supported_format_modifiers, type, NULL);
1936
1617
 	if (ret)
1937
1618
 		goto clean_sspp;
1938
1619
 
..
..
@@ -1948,6 +1629,15 @@
1948
1629
 	ret = drm_plane_create_zpos_property(plane, 0, 0, zpos_max);
1949
1630
 	if (ret)
1950
1631
 		DPU_ERROR("failed to install zpos property, rc = %d\n", ret);
1632
+
1633
+	drm_plane_create_rotation_property(plane,
1634
+			DRM_MODE_ROTATE_0,
1635
+			DRM_MODE_ROTATE_0 |
1636
+			DRM_MODE_ROTATE_180 |
1637
+			DRM_MODE_REFLECT_X |
1638
+			DRM_MODE_REFLECT_Y);
1639
+
1640
+	drm_plane_enable_fb_damage_clips(plane);
1951
1641
 
1952
1642
 	/* success! finalize initialization */
1953
1643
 	drm_plane_helper_add(plane, &dpu_plane_helper_funcs);
..
..
@@ -1966,6 +1656,5 @@
1966
1656
 		dpu_hw_sspp_destroy(pdpu->pipe_hw);
1967
1657
 clean_plane:
1968
1658
 	kfree(pdpu);
1969
-exit:
1970
1659
 	return ERR_PTR(ret);
1971
1660
 }