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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
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@@ -3,25 +3,43 @@
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  * Copyright (c) 2018, The Linux Foundation
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  */
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+#include <linux/irq.h>
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+#include <linux/irqchip.h>
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+#include <linux/irqdesc.h>
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+#include <linux/irqchip/chained_irq.h>
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 #include "dpu_kms.h"
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 #define to_dpu_mdss(x) container_of(x, struct dpu_mdss, base)
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13
 
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+#define HW_REV				0x0
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 #define HW_INTR_STATUS			0x0010
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+
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+#define UBWC_STATIC			0x144
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+#define UBWC_CTRL_2			0x150
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+#define UBWC_PREDICTION_MODE		0x154
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+
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+/* Max BW defined in KBps */
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+#define MAX_BW				6800000
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+
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+struct dpu_irq_controller {
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+	unsigned long enabled_mask;
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+	struct irq_domain *domain;
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+};
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 struct dpu_mdss {
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 	struct msm_mdss base;
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 	void __iomem *mmio;
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-	unsigned long mmio_len;
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-	u32 hwversion;
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 	struct dss_module_power mp;
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 	struct dpu_irq_controller irq_controller;
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 };
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-static irqreturn_t dpu_mdss_irq(int irq, void *arg)
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+static void dpu_mdss_irq(struct irq_desc *desc)
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 {
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-	struct dpu_mdss *dpu_mdss = arg;
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+	struct dpu_mdss *dpu_mdss = irq_desc_get_handler_data(desc);
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+	struct irq_chip *chip = irq_desc_get_chip(desc);
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 	u32 interrupts;
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+
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+	chained_irq_enter(chip, desc);
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 	interrupts = readl_relaxed(dpu_mdss->mmio + HW_INTR_STATUS);
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..
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@@ -34,20 +52,20 @@
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 					   hwirq);
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 		if (mapping == 0) {
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 			DRM_ERROR("couldn't find irq mapping for %lu\n", hwirq);
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-			return IRQ_NONE;
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+			break;
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 		}
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 		rc = generic_handle_irq(mapping);
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 		if (rc < 0) {
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 			DRM_ERROR("handle irq fail: irq=%lu mapping=%u rc=%d\n",
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 				  hwirq, mapping, rc);
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-			return IRQ_NONE;
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+			break;
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 		}
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 		interrupts &= ~(1 << hwirq);
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 	}
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-	return IRQ_HANDLED;
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+	chained_irq_exit(chip, desc);
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 }
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 static void dpu_mdss_irq_mask(struct irq_data *irqd)
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@@ -78,16 +96,16 @@
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 	.irq_unmask = dpu_mdss_irq_unmask,
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 };
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+static struct lock_class_key dpu_mdss_lock_key, dpu_mdss_request_key;
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+
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 static int dpu_mdss_irqdomain_map(struct irq_domain *domain,
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 		unsigned int irq, irq_hw_number_t hwirq)
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 {
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 	struct dpu_mdss *dpu_mdss = domain->host_data;
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-	int ret;
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+	irq_set_lockdep_class(irq, &dpu_mdss_lock_key, &dpu_mdss_request_key);
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 	irq_set_chip_and_handler(irq, &dpu_mdss_irq_chip, handle_level_irq);
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-	ret = irq_set_chip_data(irq, dpu_mdss);
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-
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-	return ret;
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+	return irq_set_chip_data(irq, dpu_mdss);
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 }
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 static const struct irq_domain_ops dpu_mdss_irqdomain_ops = {
..
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@@ -115,13 +133,12 @@
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 	return 0;
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 }
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-static int _dpu_mdss_irq_domain_fini(struct dpu_mdss *dpu_mdss)
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+static void _dpu_mdss_irq_domain_fini(struct dpu_mdss *dpu_mdss)
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 {
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 	if (dpu_mdss->irq_controller.domain) {
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 		irq_domain_remove(dpu_mdss->irq_controller.domain);
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 		dpu_mdss->irq_controller.domain = NULL;
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 	}
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-	return 0;
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 }
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 static int dpu_mdss_enable(struct msm_mdss *mdss)
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 {
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@@ -130,8 +147,30 @@
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 	int ret;
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 	ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true);
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-	if (ret)
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+	if (ret) {
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 		DPU_ERROR("clock enable failed, ret:%d\n", ret);
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+		return ret;
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+	}
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+
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+	/*
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+	 * ubwc config is part of the "mdss" region which is not accessible
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+	 * from the rest of the driver. hardcode known configurations here
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+	 */
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+	switch (readl_relaxed(dpu_mdss->mmio + HW_REV)) {
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+	case DPU_HW_VER_500:
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+	case DPU_HW_VER_501:
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+		writel_relaxed(0x420, dpu_mdss->mmio + UBWC_STATIC);
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+		break;
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+	case DPU_HW_VER_600:
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+		/* TODO: 0x102e for LP_DDR4 */
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+		writel_relaxed(0x103e, dpu_mdss->mmio + UBWC_STATIC);
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+		writel_relaxed(2, dpu_mdss->mmio + UBWC_CTRL_2);
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+		writel_relaxed(1, dpu_mdss->mmio + UBWC_PREDICTION_MODE);
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+		break;
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+	case DPU_HW_VER_620:
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+		writel_relaxed(0x1e, dpu_mdss->mmio + UBWC_STATIC);
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+		break;
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+	}
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 	return ret;
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 }
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@@ -155,17 +194,19 @@
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 	struct msm_drm_private *priv = dev->dev_private;
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 	struct dpu_mdss *dpu_mdss = to_dpu_mdss(priv->mdss);
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 	struct dss_module_power *mp = &dpu_mdss->mp;
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+	int irq;
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+	pm_runtime_suspend(dev->dev);
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+	pm_runtime_disable(dev->dev);
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 	_dpu_mdss_irq_domain_fini(dpu_mdss);
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-
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+	irq = platform_get_irq(pdev, 0);
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+	irq_set_chained_handler_and_data(irq, NULL, NULL);
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 	msm_dss_put_clk(mp->clk_config, mp->num_clk);
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 	devm_kfree(&pdev->dev, mp->clk_config);
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 	if (dpu_mdss->mmio)
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 		devm_iounmap(&pdev->dev, dpu_mdss->mmio);
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 	dpu_mdss->mmio = NULL;
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-
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-	pm_runtime_disable(dev->dev);
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 	priv->mdss = NULL;
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 }
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@@ -179,10 +220,10 @@
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 {
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 	struct platform_device *pdev = to_platform_device(dev->dev);
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 	struct msm_drm_private *priv = dev->dev_private;
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-	struct resource *res;
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 	struct dpu_mdss *dpu_mdss;
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 	struct dss_module_power *mp;
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-	int ret = 0;
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+	int ret;
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+	int irq;
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 	dpu_mdss = devm_kzalloc(dev->dev, sizeof(*dpu_mdss), GFP_KERNEL);
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 	if (!dpu_mdss)
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@@ -193,13 +234,6 @@
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 		return PTR_ERR(dpu_mdss->mmio);
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 	DRM_DEBUG("mapped mdss address space @%pK\n", dpu_mdss->mmio);
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-
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-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mdss");
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-	if (!res) {
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-		DRM_ERROR("failed to get memory resource for mdss\n");
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-		return -ENOMEM;
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-	}
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-	dpu_mdss->mmio_len = resource_size(res);
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 	mp = &dpu_mdss->mp;
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 	ret = msm_dss_parse_clock(pdev, mp);
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@@ -215,22 +249,20 @@
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 	if (ret)
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 		goto irq_domain_error;
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-	ret = devm_request_irq(dev->dev, platform_get_irq(pdev, 0),
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-			dpu_mdss_irq, 0, "dpu_mdss_isr", dpu_mdss);
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-	if (ret) {
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-		DPU_ERROR("failed to init irq: %d\n", ret);
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+	irq = platform_get_irq(pdev, 0);
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+	if (irq < 0) {
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+		ret = irq;
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 		goto irq_error;
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 	}
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-	pm_runtime_enable(dev->dev);
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-
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-	pm_runtime_get_sync(dev->dev);
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-	dpu_mdss->hwversion = readl_relaxed(dpu_mdss->mmio);
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-	pm_runtime_put_sync(dev->dev);
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+	irq_set_chained_handler_and_data(irq, dpu_mdss_irq,
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+					 dpu_mdss);
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 	priv->mdss = &dpu_mdss->base;
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-	return ret;
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+	pm_runtime_enable(dev->dev);
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+
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+	return 0;
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 irq_error:
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 	_dpu_mdss_irq_domain_fini(dpu_mdss);