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hc

2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
..
..
@@ -1,13 +1,5 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 and
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- * only version 2 as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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  */
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 #include <linux/iopoll.h>
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@@ -16,7 +8,6 @@
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 #include "dpu_hwio.h"
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 #include "dpu_hw_catalog.h"
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 #include "dpu_hw_pingpong.h"
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-#include "dpu_dbg.h"
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 #include "dpu_kms.h"
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 #include "dpu_trace.h"
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13
 
..
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@@ -37,8 +28,18 @@
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 #define PP_FBC_BUDGET_CTL               0x038
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 #define PP_FBC_LOSSY_MODE               0x03C
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-static struct dpu_pingpong_cfg *_pingpong_offset(enum dpu_pingpong pp,
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-		struct dpu_mdss_cfg *m,
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+#define PP_DITHER_EN			0x000
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+#define PP_DITHER_BITDEPTH		0x004
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+#define PP_DITHER_MATRIX		0x008
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+
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+#define DITHER_DEPTH_MAP_INDEX 9
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+
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+static u32 dither_depth_map[DITHER_DEPTH_MAP_INDEX] = {
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+	0, 0, 0, 0, 0, 0, 0, 1, 2
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+};
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+
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+static const struct dpu_pingpong_cfg *_pingpong_offset(enum dpu_pingpong pp,
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+		const struct dpu_mdss_cfg *m,
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 		void __iomem *addr,
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 		struct dpu_hw_blk_reg_map *b)
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 {
..
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@@ -56,6 +57,37 @@
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 	}
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 	return ERR_PTR(-EINVAL);
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+}
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+
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+static void dpu_hw_pp_setup_dither(struct dpu_hw_pingpong *pp,
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+				    struct dpu_hw_dither_cfg *cfg)
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+{
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+	struct dpu_hw_blk_reg_map *c;
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+	u32 i, base, data = 0;
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+
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+	c = &pp->hw;
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+	base = pp->caps->sblk->dither.base;
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+	if (!cfg) {
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+		DPU_REG_WRITE(c, base + PP_DITHER_EN, 0);
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+		return;
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+	}
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+
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+	data = dither_depth_map[cfg->c0_bitdepth] & REG_MASK(2);
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+	data |= (dither_depth_map[cfg->c1_bitdepth] & REG_MASK(2)) << 2;
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+	data |= (dither_depth_map[cfg->c2_bitdepth] & REG_MASK(2)) << 4;
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+	data |= (dither_depth_map[cfg->c3_bitdepth] & REG_MASK(2)) << 6;
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+	data |= (cfg->temporal_en) ? (1 << 8) : 0;
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+
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+	DPU_REG_WRITE(c, base + PP_DITHER_BITDEPTH, data);
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+
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+	for (i = 0; i < DITHER_MATRIX_SZ - 3; i += 4) {
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+		data = (cfg->matrix[i] & REG_MASK(4)) |
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+			((cfg->matrix[i + 1] & REG_MASK(4)) << 4) |
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+			((cfg->matrix[i + 2] & REG_MASK(4)) << 8) |
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+			((cfg->matrix[i + 3] & REG_MASK(4)) << 12);
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+		DPU_REG_WRITE(c, base + PP_DITHER_MATRIX + i, data);
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+	}
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+	DPU_REG_WRITE(c, base + PP_DITHER_EN, 1);
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 }
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 static int dpu_hw_pp_setup_te_config(struct dpu_hw_pingpong *pp,
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@@ -177,7 +209,7 @@
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 	height = DPU_REG_READ(c, PP_SYNC_CONFIG_HEIGHT) & 0xFFFF;
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 	if (height < init)
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-		goto line_count_exit;
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+		return line;
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 	line = DPU_REG_READ(c, PP_INT_COUNT_VAL) & 0xFFFF;
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..
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@@ -186,33 +218,31 @@
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 	else
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 		line -= init;
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-line_count_exit:
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 	return line;
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 }
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-static void _setup_pingpong_ops(struct dpu_hw_pingpong_ops *ops,
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-	const struct dpu_pingpong_cfg *hw_cap)
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+static void _setup_pingpong_ops(struct dpu_hw_pingpong *c,
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+				unsigned long features)
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 {
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-	ops->setup_tearcheck = dpu_hw_pp_setup_te_config;
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-	ops->enable_tearcheck = dpu_hw_pp_enable_te;
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-	ops->connect_external_te = dpu_hw_pp_connect_external_te;
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-	ops->get_vsync_info = dpu_hw_pp_get_vsync_info;
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-	ops->poll_timeout_wr_ptr = dpu_hw_pp_poll_timeout_wr_ptr;
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-	ops->get_line_count = dpu_hw_pp_get_line_count;
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+	c->ops.setup_tearcheck = dpu_hw_pp_setup_te_config;
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+	c->ops.enable_tearcheck = dpu_hw_pp_enable_te;
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+	c->ops.connect_external_te = dpu_hw_pp_connect_external_te;
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+	c->ops.get_vsync_info = dpu_hw_pp_get_vsync_info;
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+	c->ops.poll_timeout_wr_ptr = dpu_hw_pp_poll_timeout_wr_ptr;
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+	c->ops.get_line_count = dpu_hw_pp_get_line_count;
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+
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+	if (test_bit(DPU_PINGPONG_DITHER, &features))
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+		c->ops.setup_dither = dpu_hw_pp_setup_dither;
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 };
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-static struct dpu_hw_blk_ops dpu_hw_ops = {
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-	.start = NULL,
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-	.stop = NULL,
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-};
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+static struct dpu_hw_blk_ops dpu_hw_ops;
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 struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx,
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 		void __iomem *addr,
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-		struct dpu_mdss_cfg *m)
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+		const struct dpu_mdss_cfg *m)
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 {
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 	struct dpu_hw_pingpong *c;
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-	struct dpu_pingpong_cfg *cfg;
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-	int rc;
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+	const struct dpu_pingpong_cfg *cfg;
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 	c = kzalloc(sizeof(*c), GFP_KERNEL);
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 	if (!c)
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@@ -226,20 +256,11 @@
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 	c->idx = idx;
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 	c->caps = cfg;
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-	_setup_pingpong_ops(&c->ops, c->caps);
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+	_setup_pingpong_ops(c, c->caps->features);
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-	rc = dpu_hw_blk_init(&c->base, DPU_HW_BLK_PINGPONG, idx, &dpu_hw_ops);
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-	if (rc) {
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-		DPU_ERROR("failed to init hw blk %d\n", rc);
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-		goto blk_init_error;
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-	}
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+	dpu_hw_blk_init(&c->base, DPU_HW_BLK_PINGPONG, idx, &dpu_hw_ops);
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 	return c;
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-
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-blk_init_error:
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-	kzfree(c);
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-
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-	return ERR_PTR(rc);
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 }
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 void dpu_hw_pingpong_destroy(struct dpu_hw_pingpong *pp)