add new system file

hc

2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
..
..
@@ -1,19 +1,10 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 and
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- * only version 2 as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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  */
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 #include "dpu_hwio.h"
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 #include "dpu_hw_catalog.h"
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 #include "dpu_hw_intf.h"
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-#include "dpu_dbg.h"
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 #include "dpu_kms.h"
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 #define INTF_TIMING_ENGINE_EN           0x000
..
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@@ -60,16 +51,10 @@
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 #define   INTF_TPG_RGB_MAPPING          0x11C
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 #define   INTF_PROG_FETCH_START         0x170
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 #define   INTF_PROG_ROT_START           0x174
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+#define   INTF_MUX                      0x25C
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-#define   INTF_FRAME_LINE_COUNT_EN      0x0A8
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-#define   INTF_FRAME_COUNT              0x0AC
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-#define   INTF_LINE_COUNT               0x0B0
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-
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-#define INTF_MISR_CTRL			0x180
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-#define INTF_MISR_SIGNATURE		0x184
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-
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-static struct dpu_intf_cfg *_intf_offset(enum dpu_intf intf,
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-		struct dpu_mdss_cfg *m,
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+static const struct dpu_intf_cfg *_intf_offset(enum dpu_intf intf,
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+		const struct dpu_mdss_cfg *m,
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 		void __iomem *addr,
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 		struct dpu_hw_blk_reg_map *b)
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 {
..
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@@ -117,11 +102,6 @@
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 	display_v_end = ((vsync_period - p->v_front_porch) * hsync_period) +
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 	p->hsync_skew - 1;
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-	if (ctx->cap->type == INTF_EDP || ctx->cap->type == INTF_DP) {
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-		display_v_start += p->hsync_pulse_width + p->h_back_porch;
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-		display_v_end -= p->h_front_porch;
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-	}
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-
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 	hsync_start_x = p->h_back_porch + p->hsync_pulse_width;
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 	hsync_end_x = hsync_period - p->h_front_porch - 1;
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@@ -154,10 +134,26 @@
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 	hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width;
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 	display_hctl = (hsync_end_x << 16) | hsync_start_x;
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+	if (ctx->cap->type == INTF_EDP || ctx->cap->type == INTF_DP) {
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+		active_h_start = hsync_start_x;
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+		active_h_end = active_h_start + p->xres - 1;
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+		active_v_start = display_v_start;
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+		active_v_end = active_v_start + (p->yres * hsync_period) - 1;
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+
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+		display_v_start += p->hsync_pulse_width + p->h_back_porch;
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+		display_v_end   -= p->h_front_porch; 
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+
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+		active_hctl = (active_h_end << 16) | active_h_start;
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+		display_hctl = active_hctl;
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+	}
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+
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 	den_polarity = 0;
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 	if (ctx->cap->type == INTF_HDMI) {
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 		hsync_polarity = p->yres >= 720 ? 0 : 1;
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 		vsync_polarity = p->yres >= 720 ? 0 : 1;
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+	} else if (ctx->cap->type == INTF_DP) {
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+		hsync_polarity = p->hsync_polarity;
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+		vsync_polarity = p->vsync_polarity;
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 	} else {
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 		hsync_polarity = 0;
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 		vsync_polarity = 0;
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@@ -230,6 +226,25 @@
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 	DPU_REG_WRITE(c, INTF_CONFIG, fetch_enable);
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 }
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+static void dpu_hw_intf_bind_pingpong_blk(
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+		struct dpu_hw_intf *intf,
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+		bool enable,
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+		const enum dpu_pingpong pp)
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+{
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+	struct dpu_hw_blk_reg_map *c = &intf->hw;
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+	u32 mux_cfg;
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+
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+	mux_cfg = DPU_REG_READ(c, INTF_MUX);
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+	mux_cfg &= ~0xf;
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+
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+	if (enable)
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+		mux_cfg |= (pp - PINGPONG_0) & 0x7;
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+	else
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+		mux_cfg |= 0xf;
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+
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+	DPU_REG_WRITE(c, INTF_MUX, mux_cfg);
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+}
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+
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 static void dpu_hw_intf_get_status(
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 		struct dpu_hw_intf *intf,
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 		struct intf_status *s)
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@@ -244,30 +259,6 @@
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 		s->line_count = 0;
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 		s->frame_count = 0;
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 	}
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-}
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-
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-static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf,
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-						bool enable, u32 frame_count)
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-{
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-	struct dpu_hw_blk_reg_map *c = &intf->hw;
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-	u32 config = 0;
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-
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-	DPU_REG_WRITE(c, INTF_MISR_CTRL, MISR_CTRL_STATUS_CLEAR);
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-	/* clear misr data */
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-	wmb();
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-
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-	if (enable)
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-		config = (frame_count & MISR_FRAME_COUNT_MASK) |
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-			MISR_CTRL_ENABLE | INTF_MISR_CTRL_FREE_RUN_MASK;
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-
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-	DPU_REG_WRITE(c, INTF_MISR_CTRL, config);
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-}
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-
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-static u32 dpu_hw_intf_collect_misr(struct dpu_hw_intf *intf)
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-{
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-	struct dpu_hw_blk_reg_map *c = &intf->hw;
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-
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-	return DPU_REG_READ(c, INTF_MISR_SIGNATURE);
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 }
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 static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf)
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@@ -289,23 +280,19 @@
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 	ops->setup_prg_fetch  = dpu_hw_intf_setup_prg_fetch;
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 	ops->get_status = dpu_hw_intf_get_status;
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 	ops->enable_timing = dpu_hw_intf_enable_timing_engine;
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-	ops->setup_misr = dpu_hw_intf_setup_misr;
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-	ops->collect_misr = dpu_hw_intf_collect_misr;
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 	ops->get_line_count = dpu_hw_intf_get_line_count;
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+	if (cap & BIT(DPU_INTF_INPUT_CTRL))
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+		ops->bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk;
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 }
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-static struct dpu_hw_blk_ops dpu_hw_ops = {
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-	.start = NULL,
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-	.stop = NULL,
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-};
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+static struct dpu_hw_blk_ops dpu_hw_ops;
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 struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx,
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 		void __iomem *addr,
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-		struct dpu_mdss_cfg *m)
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+		const struct dpu_mdss_cfg *m)
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 {
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 	struct dpu_hw_intf *c;
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-	struct dpu_intf_cfg *cfg;
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-	int rc;
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+	const struct dpu_intf_cfg *cfg;
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 	c = kzalloc(sizeof(*c), GFP_KERNEL);
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 	if (!c)
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@@ -326,18 +313,9 @@
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 	c->mdss = m;
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 	_setup_intf_ops(&c->ops, c->cap->features);
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-	rc = dpu_hw_blk_init(&c->base, DPU_HW_BLK_INTF, idx, &dpu_hw_ops);
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-	if (rc) {
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-		DPU_ERROR("failed to init hw blk %d\n", rc);
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-		goto blk_init_error;
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-	}
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+	dpu_hw_blk_init(&c->base, DPU_HW_BLK_INTF, idx, &dpu_hw_ops);
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 	return c;
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-
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-blk_init_error:
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-	kzfree(c);
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-
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-	return ERR_PTR(rc);
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 }
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 void dpu_hw_intf_destroy(struct dpu_hw_intf *intf)