forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
....@@ -1,20 +1,12 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
2
- *
3
- * This program is free software; you can redistribute it and/or modify
4
- * it under the terms of the GNU General Public License version 2 and
5
- * only version 2 as published by the Free Software Foundation.
6
- *
7
- * This program is distributed in the hope that it will be useful,
8
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
9
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
10
- * GNU General Public License for more details.
113  */
124 
135 #include <linux/delay.h>
146 #include "dpu_hwio.h"
157 #include "dpu_hw_ctl.h"
16
-#include "dpu_dbg.h"
178 #include "dpu_kms.h"
9
+#include "dpu_trace.h"
1810 
1911 #define   CTL_LAYER(lm)                 \
2012 	(((lm) == LM_5) ? (0x024) : (((lm) - LM_0) * 0x004))
....@@ -30,14 +22,18 @@
3022 #define   CTL_PREPARE                   0x0d0
3123 #define   CTL_SW_RESET                  0x030
3224 #define   CTL_LAYER_EXTN_OFFSET         0x40
25
+#define   CTL_INTF_ACTIVE               0x0F4
26
+#define   CTL_INTF_FLUSH                0x110
27
+#define   CTL_INTF_MASTER               0x134
3328 
3429 #define CTL_MIXER_BORDER_OUT            BIT(24)
3530 #define CTL_FLUSH_MASK_CTL              BIT(17)
3631 
3732 #define DPU_REG_RESET_TIMEOUT_US        2000
33
+#define  INTF_IDX       31
3834 
39
-static struct dpu_ctl_cfg *_ctl_offset(enum dpu_ctl ctl,
40
-		struct dpu_mdss_cfg *m,
35
+static const struct dpu_ctl_cfg *_ctl_offset(enum dpu_ctl ctl,
36
+		const struct dpu_mdss_cfg *m,
4137 		void __iomem *addr,
4238 		struct dpu_hw_blk_reg_map *b)
4339 {
....@@ -72,41 +68,6 @@
7268 	return stages;
7369 }
7470 
75
-static inline void dpu_hw_ctl_trigger_start(struct dpu_hw_ctl *ctx)
76
-{
77
-	DPU_REG_WRITE(&ctx->hw, CTL_START, 0x1);
78
-}
79
-
80
-static inline void dpu_hw_ctl_trigger_pending(struct dpu_hw_ctl *ctx)
81
-{
82
-	DPU_REG_WRITE(&ctx->hw, CTL_PREPARE, 0x1);
83
-}
84
-
85
-static inline void dpu_hw_ctl_clear_pending_flush(struct dpu_hw_ctl *ctx)
86
-{
87
-	ctx->pending_flush_mask = 0x0;
88
-}
89
-
90
-static inline void dpu_hw_ctl_update_pending_flush(struct dpu_hw_ctl *ctx,
91
-		u32 flushbits)
92
-{
93
-	ctx->pending_flush_mask |= flushbits;
94
-}
95
-
96
-static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx)
97
-{
98
-	if (!ctx)
99
-		return 0x0;
100
-
101
-	return ctx->pending_flush_mask;
102
-}
103
-
104
-static inline void dpu_hw_ctl_trigger_flush(struct dpu_hw_ctl *ctx)
105
-{
106
-
107
-	DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask);
108
-}
109
-
11071 static inline u32 dpu_hw_ctl_get_flush_register(struct dpu_hw_ctl *ctx)
11172 {
11273 	struct dpu_hw_blk_reg_map *c = &ctx->hw;
....@@ -114,7 +75,64 @@
11475 	return DPU_REG_READ(c, CTL_FLUSH);
11576 }
11677 
117
-static inline uint32_t dpu_hw_ctl_get_bitmask_sspp(struct dpu_hw_ctl *ctx,
78
+static inline void dpu_hw_ctl_trigger_start(struct dpu_hw_ctl *ctx)
79
+{
80
+	trace_dpu_hw_ctl_trigger_start(ctx->pending_flush_mask,
81
+				       dpu_hw_ctl_get_flush_register(ctx));
82
+	DPU_REG_WRITE(&ctx->hw, CTL_START, 0x1);
83
+}
84
+
85
+static inline void dpu_hw_ctl_trigger_pending(struct dpu_hw_ctl *ctx)
86
+{
87
+	trace_dpu_hw_ctl_trigger_prepare(ctx->pending_flush_mask,
88
+					 dpu_hw_ctl_get_flush_register(ctx));
89
+	DPU_REG_WRITE(&ctx->hw, CTL_PREPARE, 0x1);
90
+}
91
+
92
+static inline void dpu_hw_ctl_clear_pending_flush(struct dpu_hw_ctl *ctx)
93
+{
94
+	trace_dpu_hw_ctl_clear_pending_flush(ctx->pending_flush_mask,
95
+				     dpu_hw_ctl_get_flush_register(ctx));
96
+	ctx->pending_flush_mask = 0x0;
97
+}
98
+
99
+static inline void dpu_hw_ctl_update_pending_flush(struct dpu_hw_ctl *ctx,
100
+		u32 flushbits)
101
+{
102
+	trace_dpu_hw_ctl_update_pending_flush(flushbits,
103
+					      ctx->pending_flush_mask);
104
+	ctx->pending_flush_mask |= flushbits;
105
+}
106
+
107
+static inline void dpu_hw_ctl_update_pending_intf_flush(struct dpu_hw_ctl *ctx,
108
+		u32 flushbits)
109
+{
110
+	ctx->pending_intf_flush_mask |= flushbits;
111
+}
112
+
113
+static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx)
114
+{
115
+	return ctx->pending_flush_mask;
116
+}
117
+
118
+static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx)
119
+{
120
+
121
+	if (ctx->pending_flush_mask & BIT(INTF_IDX))
122
+		DPU_REG_WRITE(&ctx->hw, CTL_INTF_FLUSH,
123
+				ctx->pending_intf_flush_mask);
124
+
125
+	DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask);
126
+}
127
+
128
+static inline void dpu_hw_ctl_trigger_flush(struct dpu_hw_ctl *ctx)
129
+{
130
+	trace_dpu_hw_ctl_trigger_pending_flush(ctx->pending_flush_mask,
131
+				     dpu_hw_ctl_get_flush_register(ctx));
132
+	DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask);
133
+}
134
+
135
+static uint32_t dpu_hw_ctl_get_bitmask_sspp(struct dpu_hw_ctl *ctx,
118136 	enum dpu_sspp sspp)
119137 {
120138 	uint32_t flushbits = 0;
....@@ -169,7 +187,7 @@
169187 	return flushbits;
170188 }
171189 
172
-static inline uint32_t dpu_hw_ctl_get_bitmask_mixer(struct dpu_hw_ctl *ctx,
190
+static uint32_t dpu_hw_ctl_get_bitmask_mixer(struct dpu_hw_ctl *ctx,
173191 	enum dpu_lm lm)
174192 {
175193 	uint32_t flushbits = 0;
....@@ -202,7 +220,7 @@
202220 	return flushbits;
203221 }
204222 
205
-static inline int dpu_hw_ctl_get_bitmask_intf(struct dpu_hw_ctl *ctx,
223
+static int dpu_hw_ctl_get_bitmask_intf(struct dpu_hw_ctl *ctx,
206224 		u32 *flushbits, enum dpu_intf intf)
207225 {
208226 	switch (intf) {
....@@ -224,17 +242,43 @@
224242 	return 0;
225243 }
226244 
227
-static inline int dpu_hw_ctl_get_bitmask_cdm(struct dpu_hw_ctl *ctx,
228
-		u32 *flushbits, enum dpu_cdm cdm)
245
+static int dpu_hw_ctl_get_bitmask_intf_v1(struct dpu_hw_ctl *ctx,
246
+		u32 *flushbits, enum dpu_intf intf)
229247 {
230
-	switch (cdm) {
231
-	case CDM_0:
232
-		*flushbits |= BIT(26);
248
+	*flushbits |= BIT(31);
249
+	return 0;
250
+}
251
+
252
+static int dpu_hw_ctl_active_get_bitmask_intf(struct dpu_hw_ctl *ctx,
253
+		u32 *flushbits, enum dpu_intf intf)
254
+{
255
+	*flushbits |= BIT(intf - INTF_0);
256
+	return 0;
257
+}
258
+
259
+static uint32_t dpu_hw_ctl_get_bitmask_dspp(struct dpu_hw_ctl *ctx,
260
+	enum dpu_dspp dspp)
261
+{
262
+	uint32_t flushbits = 0;
263
+
264
+	switch (dspp) {
265
+	case DSPP_0:
266
+		flushbits = BIT(13);
267
+		break;
268
+	case DSPP_1:
269
+		flushbits = BIT(14);
270
+		break;
271
+	case DSPP_2:
272
+		flushbits = BIT(15);
273
+		break;
274
+	case DSPP_3:
275
+		flushbits = BIT(21);
233276 		break;
234277 	default:
235
-		return -EINVAL;
278
+		return 0;
236279 	}
237
-	return 0;
280
+
281
+	return flushbits;
238282 }
239283 
240284 static u32 dpu_hw_ctl_poll_reset_status(struct dpu_hw_ctl *ctx, u32 timeout_us)
....@@ -439,6 +483,24 @@
439483 	DPU_REG_WRITE(c, CTL_LAYER_EXT3(lm), mixercfg_ext3);
440484 }
441485 
486
+
487
+static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
488
+		struct dpu_hw_intf_cfg *cfg)
489
+{
490
+	struct dpu_hw_blk_reg_map *c = &ctx->hw;
491
+	u32 intf_active = 0;
492
+	u32 mode_sel = 0;
493
+
494
+	if (cfg->intf_mode_sel == DPU_CTL_MODE_SEL_CMD)
495
+		mode_sel |= BIT(17);
496
+
497
+	intf_active = DPU_REG_READ(c, CTL_INTF_ACTIVE);
498
+	intf_active |= BIT(cfg->intf - INTF_0);
499
+
500
+	DPU_REG_WRITE(c, CTL_TOP, mode_sel);
501
+	DPU_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active);
502
+}
503
+
442504 static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
443505 		struct dpu_hw_intf_cfg *cfg)
444506 {
....@@ -472,36 +534,42 @@
472534 static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops,
473535 		unsigned long cap)
474536 {
537
+	if (cap & BIT(DPU_CTL_ACTIVE_CFG)) {
538
+		ops->trigger_flush = dpu_hw_ctl_trigger_flush_v1;
539
+		ops->setup_intf_cfg = dpu_hw_ctl_intf_cfg_v1;
540
+		ops->get_bitmask_intf = dpu_hw_ctl_get_bitmask_intf_v1;
541
+		ops->get_bitmask_active_intf =
542
+			dpu_hw_ctl_active_get_bitmask_intf;
543
+		ops->update_pending_intf_flush =
544
+			dpu_hw_ctl_update_pending_intf_flush;
545
+	} else {
546
+		ops->trigger_flush = dpu_hw_ctl_trigger_flush;
547
+		ops->setup_intf_cfg = dpu_hw_ctl_intf_cfg;
548
+		ops->get_bitmask_intf = dpu_hw_ctl_get_bitmask_intf;
549
+	}
475550 	ops->clear_pending_flush = dpu_hw_ctl_clear_pending_flush;
476551 	ops->update_pending_flush = dpu_hw_ctl_update_pending_flush;
477552 	ops->get_pending_flush = dpu_hw_ctl_get_pending_flush;
478
-	ops->trigger_flush = dpu_hw_ctl_trigger_flush;
479553 	ops->get_flush_register = dpu_hw_ctl_get_flush_register;
480554 	ops->trigger_start = dpu_hw_ctl_trigger_start;
481555 	ops->trigger_pending = dpu_hw_ctl_trigger_pending;
482
-	ops->setup_intf_cfg = dpu_hw_ctl_intf_cfg;
483556 	ops->reset = dpu_hw_ctl_reset_control;
484557 	ops->wait_reset_status = dpu_hw_ctl_wait_reset_status;
485558 	ops->clear_all_blendstages = dpu_hw_ctl_clear_all_blendstages;
486559 	ops->setup_blendstage = dpu_hw_ctl_setup_blendstage;
487560 	ops->get_bitmask_sspp = dpu_hw_ctl_get_bitmask_sspp;
488561 	ops->get_bitmask_mixer = dpu_hw_ctl_get_bitmask_mixer;
489
-	ops->get_bitmask_intf = dpu_hw_ctl_get_bitmask_intf;
490
-	ops->get_bitmask_cdm = dpu_hw_ctl_get_bitmask_cdm;
562
+	ops->get_bitmask_dspp = dpu_hw_ctl_get_bitmask_dspp;
491563 };
492564 
493
-static struct dpu_hw_blk_ops dpu_hw_ops = {
494
-	.start = NULL,
495
-	.stop = NULL,
496
-};
565
+static struct dpu_hw_blk_ops dpu_hw_ops;
497566 
498567 struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx,
499568 		void __iomem *addr,
500
-		struct dpu_mdss_cfg *m)
569
+		const struct dpu_mdss_cfg *m)
501570 {
502571 	struct dpu_hw_ctl *c;
503
-	struct dpu_ctl_cfg *cfg;
504
-	int rc;
572
+	const struct dpu_ctl_cfg *cfg;
505573 
506574 	c = kzalloc(sizeof(*c), GFP_KERNEL);
507575 	if (!c)
....@@ -520,18 +588,9 @@
520588 	c->mixer_count = m->mixer_count;
521589 	c->mixer_hw_caps = m->mixer;
522590 
523
-	rc = dpu_hw_blk_init(&c->base, DPU_HW_BLK_CTL, idx, &dpu_hw_ops);
524
-	if (rc) {
525
-		DPU_ERROR("failed to init hw blk %d\n", rc);
526
-		goto blk_init_error;
527
-	}
591
+	dpu_hw_blk_init(&c->base, DPU_HW_BLK_CTL, idx, &dpu_hw_ops);
528592 
529593 	return c;
530
-
531
-blk_init_error:
532
-	kzfree(c);
533
-
534
-	return ERR_PTR(rc);
535594 }
536595 
537596 void dpu_hw_ctl_destroy(struct dpu_hw_ctl *ctx)