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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
....@@ -1,13 +1,5 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
2
- *
3
- * This program is free software; you can redistribute it and/or modify
4
- * it under the terms of the GNU General Public License version 2 and
5
- * only version 2 as published by the Free Software Foundation.
6
- *
7
- * This program is distributed in the hope that it will be useful,
8
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
9
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
10
- * GNU General Public License for more details.
113  */
124 
135 #ifndef _DPU_HW_CATALOG_H
....@@ -17,7 +9,6 @@
179 #include <linux/bug.h>
1810 #include <linux/bitmap.h>
1911 #include <linux/err.h>
20
-#include <drm/drmP.h>
2112 
2213 /**
2314  * Max hardware block count: For ex: max 12 SSPP pipes or
....@@ -46,7 +37,10 @@
4637 #define DPU_HW_VER_400	DPU_HW_VER(4, 0, 0) /* sdm845 v1.0 */
4738 #define DPU_HW_VER_401	DPU_HW_VER(4, 0, 1) /* sdm845 v2.0 */
4839 #define DPU_HW_VER_410	DPU_HW_VER(4, 1, 0) /* sdm670 v1.0 */
49
-#define DPU_HW_VER_500	DPU_HW_VER(5, 0, 0) /* sdm855 v1.0 */
40
+#define DPU_HW_VER_500	DPU_HW_VER(5, 0, 0) /* sm8150 v1.0 */
41
+#define DPU_HW_VER_501	DPU_HW_VER(5, 0, 1) /* sm8150 v2.0 */
42
+#define DPU_HW_VER_600	DPU_HW_VER(6, 0, 0) /* sm8250 */
43
+#define DPU_HW_VER_620	DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */
5044 
5145 
5246 #define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170)
....@@ -54,6 +48,7 @@
5448 #define IS_SDM845_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_400)
5549 #define IS_SDM670_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_410)
5650 #define IS_SDM855_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_500)
51
+#define IS_SC7180_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_620)
5752 
5853 
5954 #define DPU_HW_BLK_NAME_LEN	16
....@@ -72,9 +67,8 @@
7267 	DPU_HW_UBWC_VER_10 = 0x100,
7368 	DPU_HW_UBWC_VER_20 = 0x200,
7469 	DPU_HW_UBWC_VER_30 = 0x300,
70
+	DPU_HW_UBWC_VER_40 = 0x400,
7571 };
76
-
77
-#define IS_UBWC_20_SUPPORTED(rev)       ((rev) >= DPU_HW_UBWC_VER_20)
7872 
7973 /**
8074  * MDP TOP BLOCK features
....@@ -101,6 +95,7 @@
10195  * @DPU_SSPP_SRC             Src and fetch part of the pipes,
10296  * @DPU_SSPP_SCALER_QSEED2,  QSEED2 algorithm support
10397  * @DPU_SSPP_SCALER_QSEED3,  QSEED3 alogorithm support
98
+ * @DPU_SSPP_SCALER_QSEED4,  QSEED4 algorithm support
10499  * @DPU_SSPP_SCALER_RGB,     RGB Scaler, supported by RGB pipes
105100  * @DPU_SSPP_CSC,            Support of Color space converion
106101  * @DPU_SSPP_CSC_10BIT,      Support of 10-bit Color space conversion
....@@ -119,6 +114,7 @@
119114 	DPU_SSPP_SRC = 0x1,
120115 	DPU_SSPP_SCALER_QSEED2,
121116 	DPU_SSPP_SCALER_QSEED3,
117
+	DPU_SSPP_SCALER_QSEED4,
122118 	DPU_SSPP_SCALER_RGB,
123119 	DPU_SSPP_CSC,
124120 	DPU_SSPP_CSC_10BIT,
....@@ -151,6 +147,17 @@
151147 };
152148 
153149 /**
150
+ * DSPP sub-blocks
151
+ * @DPU_DSPP_PCC             Panel color correction block
152
+ * @DPU_DSPP_GC              Gamma correction block
153
+ */
154
+enum {
155
+	DPU_DSPP_PCC = 0x1,
156
+	DPU_DSPP_GC,
157
+	DPU_DSPP_MAX
158
+};
159
+
160
+/**
154161  * PINGPONG sub-blocks
155162  * @DPU_PINGPONG_TE         Tear check block
156163  * @DPU_PINGPONG_TE2        Additional tear check block for split pipes
....@@ -175,7 +182,21 @@
175182  */
176183 enum {
177184 	DPU_CTL_SPLIT_DISPLAY = 0x1,
185
+	DPU_CTL_ACTIVE_CFG,
178186 	DPU_CTL_MAX
187
+};
188
+
189
+/**
190
+ * INTF sub-blocks
191
+ * @DPU_INTF_INPUT_CTRL         Supports the setting of pp block from which
192
+ *                              pixel data arrives to this INTF
193
+ * @DPU_INTF_TE                 INTF block has TE configuration support
194
+ * @DPU_INTF_MAX
195
+ */
196
+enum {
197
+	DPU_INTF_INPUT_CTRL = 0x1,
198
+	DPU_INTF_TE,
199
+	DPU_INTF_MAX
179200 };
180201 
181202 /**
....@@ -252,17 +273,6 @@
252273 };
253274 
254275 /**
255
- * struct dpu_format_extended - define dpu specific pixel format+modifier
256
- * @fourcc_format: Base FOURCC pixel format code
257
- * @modifier: 64-bit drm format modifier, same modifier must be applied to all
258
- *            framebuffer planes
259
- */
260
-struct dpu_format_extended {
261
-	uint32_t fourcc_format;
262
-	uint64_t modifier;
263
-};
264
-
265
-/**
266276  * enum dpu_qos_lut_usage - define QoS LUT use cases
267277  */
268278 enum dpu_qos_lut_usage {
....@@ -289,7 +299,7 @@
289299  */
290300 struct dpu_qos_lut_tbl {
291301 	u32 nentry;
292
-	struct dpu_qos_lut_entry *entries;
302
+	const struct dpu_qos_lut_entry *entries;
293303 };
294304 
295305 /**
....@@ -303,6 +313,11 @@
303313  * @has_src_split      source split feature status
304314  * @has_dim_layer      dim layer feature status
305315  * @has_idle_pc        indicate if idle power collapse feature is supported
316
+ * @has_3d_merge       indicate if 3D merge is supported
317
+ * @max_linewidth      max linewidth for sspp
318
+ * @pixel_ram_size     size of latency hiding and de-tiling buffer in bytes
319
+ * @max_hdeci_exp      max horizontal decimation supported (max is 2^value)
320
+ * @max_vdeci_exp      max vertical decimation supported (max is 2^value)
306321  */
307322 struct dpu_caps {
308323 	u32 max_mixer_width;
....@@ -313,22 +328,12 @@
313328 	bool has_src_split;
314329 	bool has_dim_layer;
315330 	bool has_idle_pc;
316
-};
317
-
318
-/**
319
- * struct dpu_sspp_blks_common : SSPP sub-blocks common configuration
320
- * @maxwidth: max pixelwidth supported by this pipe
321
- * @pixel_ram_size: size of latency hiding and de-tiling buffer in bytes
322
- * @maxhdeciexp: max horizontal decimation supported by this pipe
323
- *				(max is 2^value)
324
- * @maxvdeciexp: max vertical decimation supported by this pipe
325
- *				(max is 2^value)
326
- */
327
-struct dpu_sspp_blks_common {
328
-	u32 maxlinewidth;
331
+	bool has_3d_merge;
332
+	/* SSPP limits */
333
+	u32 max_linewidth;
329334 	u32 pixel_ram_size;
330
-	u32 maxhdeciexp;
331
-	u32 maxvdeciexp;
335
+	u32 max_hdeci_exp;
336
+	u32 max_vdeci_exp;
332337 };
333338 
334339 /**
....@@ -340,6 +345,7 @@
340345  * @maxupscale:  maxupscale ratio supported
341346  * @smart_dma_priority: hw priority of rect1 of multirect pipe
342347  * @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps
348
+ * @qseed_ver: qseed version
343349  * @src_blk:
344350  * @scaler_blk:
345351  * @csc_blk:
....@@ -348,16 +354,18 @@
348354  * @pcc_blk:
349355  * @igc_blk:
350356  * @format_list: Pointer to list of supported formats
357
+ * @num_formats: Number of supported formats
351358  * @virt_format_list: Pointer to list of supported formats for virtual planes
359
+ * @virt_num_formats: Number of supported formats for virtual planes
352360  */
353361 struct dpu_sspp_sub_blks {
354
-	const struct dpu_sspp_blks_common *common;
355362 	u32 creq_vblank;
356363 	u32 danger_vblank;
357364 	u32 maxdwnscale;
358365 	u32 maxupscale;
359366 	u32 smart_dma_priority;
360367 	u32 max_per_pipe_bw;
368
+	u32 qseed_ver;
361369 	struct dpu_src_blk src_blk;
362370 	struct dpu_scaler_blk scaler_blk;
363371 	struct dpu_pp_blk csc_blk;
....@@ -366,8 +374,10 @@
366374 	struct dpu_pp_blk pcc_blk;
367375 	struct dpu_pp_blk igc_blk;
368376 
369
-	const struct dpu_format_extended *format_list;
370
-	const struct dpu_format_extended *virt_format_list;
377
+	const u32 *format_list;
378
+	u32 num_formats;
379
+	const u32 *virt_format_list;
380
+	u32 virt_num_formats;
371381 };
372382 
373383 /**
....@@ -382,6 +392,16 @@
382392 	u32 maxblendstages;
383393 	u32 blendstage_base[MAX_BLOCKS];
384394 	struct dpu_pp_blk gc;
395
+};
396
+
397
+/**
398
+ * struct dpu_dspp_sub_blks: Information of DSPP block
399
+ * @gc : gamma correction block
400
+ * @pcc: pixel color correction block
401
+ */
402
+struct dpu_dspp_sub_blks {
403
+	struct dpu_pp_blk gc;
404
+	struct dpu_pp_blk pcc;
385405 };
386406 
387407 struct dpu_pingpong_sub_blks {
....@@ -409,6 +429,7 @@
409429 	DPU_CLK_CTRL_CURSOR0,
410430 	DPU_CLK_CTRL_CURSOR1,
411431 	DPU_CLK_CTRL_INLINE_ROT0_SSPP,
432
+	DPU_CLK_CTRL_REG_DMA,
412433 	DPU_CLK_CTRL_MAX,
413434 };
414435 
....@@ -428,15 +449,12 @@
428449  * @highest_bank_bit:  UBWC parameter
429450  * @ubwc_static:       ubwc static configuration
430451  * @ubwc_swizzle:      ubwc default swizzle setting
431
- * @has_dest_scaler:   indicates support of destination scaler
432452  * @clk_ctrls          clock control register definition
433453  */
434454 struct dpu_mdp_cfg {
435455 	DPU_HW_BLK_INFO;
436456 	u32 highest_bank_bit;
437
-	u32 ubwc_static;
438457 	u32 ubwc_swizzle;
439
-	bool has_dest_scaler;
440458 	struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX];
441459 };
442460 
....@@ -474,47 +492,27 @@
474492  * @features           bit mask identifying sub-blocks/features
475493  * @sblk:              LM Sub-blocks information
476494  * @pingpong:          ID of connected PingPong, PINGPONG_MAX if unsupported
477
- * @ds:                ID of connected DS, DS_MAX if unsupported
478495  * @lm_pair_mask:      Bitmask of LMs that can be controlled by same CTL
479496  */
480497 struct dpu_lm_cfg {
481498 	DPU_HW_BLK_INFO;
482499 	const struct dpu_lm_sub_blks *sblk;
483500 	u32 pingpong;
484
-	u32 ds;
501
+	u32 dspp;
485502 	unsigned long lm_pair_mask;
486503 };
487504 
488505 /**
489
- * struct dpu_ds_top_cfg - information of dest scaler top
490
- * @id               enum identifying this block
491
- * @base             register offset of this block
492
- * @features         bit mask identifying features
493
- * @version          hw version of dest scaler
494
- * @maxinputwidth    maximum input line width
495
- * @maxoutputwidth   maximum output line width
496
- * @maxupscale       maximum upscale ratio
506
+ * struct dpu_dspp_cfg - information of DSPP blocks
507
+ * @id                 enum identifying this block
508
+ * @base               register offset of this block
509
+ * @features           bit mask identifying sub-blocks/features
510
+ *                     supported by this block
511
+ * @sblk               sub-blocks information
497512  */
498
-struct dpu_ds_top_cfg {
513
+struct dpu_dspp_cfg  {
499514 	DPU_HW_BLK_INFO;
500
-	u32 version;
501
-	u32 maxinputwidth;
502
-	u32 maxoutputwidth;
503
-	u32 maxupscale;
504
-};
505
-
506
-/**
507
- * struct dpu_ds_cfg - information of dest scaler blocks
508
- * @id          enum identifying this block
509
- * @base        register offset wrt DS top offset
510
- * @features    bit mask identifying features
511
- * @version     hw version of the qseed block
512
- * @top         DS top information
513
- */
514
-struct dpu_ds_cfg {
515
-	DPU_HW_BLK_INFO;
516
-	u32 version;
517
-	const struct dpu_ds_top_cfg *top;
515
+	const struct dpu_dspp_sub_blks *sblk;
518516 };
519517 
520518 /**
....@@ -527,18 +525,6 @@
527525 struct dpu_pingpong_cfg  {
528526 	DPU_HW_BLK_INFO;
529527 	const struct dpu_pingpong_sub_blks *sblk;
530
-};
531
-
532
-/**
533
- * struct dpu_cdm_cfg - information of chroma down blocks
534
- * @id                 enum identifying this block
535
- * @base               register offset of this block
536
- * @features           bit mask identifying sub-blocks/features
537
- * @intf_connect       Bitmask of INTF IDs this CDM can connect to
538
- */
539
-struct dpu_cdm_cfg   {
540
-	DPU_HW_BLK_INFO;
541
-	unsigned long intf_connect;
542528 };
543529 
544530 /**
....@@ -575,7 +561,7 @@
575561  */
576562 struct dpu_vbif_dynamic_ot_tbl {
577563 	u32 count;
578
-	struct dpu_vbif_dynamic_ot_cfg *cfg;
564
+	const struct dpu_vbif_dynamic_ot_cfg *cfg;
579565 };
580566 
581567 /**
....@@ -585,7 +571,7 @@
585571  */
586572 struct dpu_vbif_qos_tbl {
587573 	u32 npriority_lvl;
588
-	u32 *priority_lvl;
574
+	const u32 *priority_lvl;
589575 };
590576 
591577 /**
....@@ -627,6 +613,8 @@
627613 	DPU_HW_BLK_INFO;
628614 	u32 version;
629615 	u32 trigger_sel_off;
616
+	u32 xin_id;
617
+	enum dpu_clk_ctrl_type clk_ctrl;
630618 };
631619 
632620 /**
....@@ -671,6 +659,8 @@
671659  * @downscaling_prefill_lines  downscaling latency in lines
672660  * @amortizable_theshold minimum y position for traffic shaping prefill
673661  * @min_prefill_lines  minimum pipeline latency in lines
662
+ * @clk_inefficiency_factor DPU src clock inefficiency factor
663
+ * @bw_inefficiency_factor DPU axi bus bw inefficiency factor
674664  * @safe_lut_tbl: LUT tables for safe signals
675665  * @danger_lut_tbl: LUT tables for danger signals
676666  * @qos_lut_tbl: LUT tables for QoS signals
....@@ -695,6 +685,8 @@
695685 	u32 downscaling_prefill_lines;
696686 	u32 amortizable_threshold;
697687 	u32 min_prefill_lines;
688
+	u32 clk_inefficiency_factor;
689
+	u32 bw_inefficiency_factor;
698690 	u32 safe_lut_tbl[DPU_QOS_LUT_USAGE_MAX];
699691 	u32 danger_lut_tbl[DPU_QOS_LUT_USAGE_MAX];
700692 	struct dpu_qos_lut_tbl qos_lut_tbl[DPU_QOS_LUT_USAGE_MAX];
....@@ -710,6 +702,7 @@
710702  * @dma_formats        Supported formats for dma pipe
711703  * @cursor_formats     Supported formats for cursor pipe
712704  * @vig_formats        Supported formats for vig pipe
705
+ * @mdss_irqs:         Bitmap with the irqs supported by the target
713706  */
714707 struct dpu_mdss_cfg {
715708 	u32 hwversion;
....@@ -717,43 +710,42 @@
717710 	const struct dpu_caps *caps;
718711 
719712 	u32 mdp_count;
720
-	struct dpu_mdp_cfg *mdp;
713
+	const struct dpu_mdp_cfg *mdp;
721714 
722715 	u32 ctl_count;
723
-	struct dpu_ctl_cfg *ctl;
716
+	const struct dpu_ctl_cfg *ctl;
724717 
725718 	u32 sspp_count;
726
-	struct dpu_sspp_cfg *sspp;
719
+	const struct dpu_sspp_cfg *sspp;
727720 
728721 	u32 mixer_count;
729
-	struct dpu_lm_cfg *mixer;
730
-
731
-	u32 ds_count;
732
-	struct dpu_ds_cfg *ds;
722
+	const struct dpu_lm_cfg *mixer;
733723 
734724 	u32 pingpong_count;
735
-	struct dpu_pingpong_cfg *pingpong;
736
-
737
-	u32 cdm_count;
738
-	struct dpu_cdm_cfg *cdm;
725
+	const struct dpu_pingpong_cfg *pingpong;
739726 
740727 	u32 intf_count;
741
-	struct dpu_intf_cfg *intf;
728
+	const struct dpu_intf_cfg *intf;
742729 
743730 	u32 vbif_count;
744
-	struct dpu_vbif_cfg *vbif;
731
+	const struct dpu_vbif_cfg *vbif;
745732 
746733 	u32 reg_dma_count;
747734 	struct dpu_reg_dma_cfg dma_cfg;
748735 
749736 	u32 ad_count;
750737 
738
+	u32 dspp_count;
739
+	const struct dpu_dspp_cfg *dspp;
740
+
751741 	/* Add additional block data structures here */
752742 
753743 	struct dpu_perf_cfg perf;
754
-	struct dpu_format_extended *dma_formats;
755
-	struct dpu_format_extended *cursor_formats;
756
-	struct dpu_format_extended *vig_formats;
744
+	const struct dpu_format_extended *dma_formats;
745
+	const struct dpu_format_extended *cursor_formats;
746
+	const struct dpu_format_extended *vig_formats;
747
+
748
+	unsigned long mdss_irqs;
757749 };
758750 
759751 struct dpu_mdss_hw_cfg_handler {
....@@ -771,11 +763,10 @@
771763 #define BLK_DMA(s) ((s)->dma)
772764 #define BLK_CURSOR(s) ((s)->cursor)
773765 #define BLK_MIXER(s) ((s)->mixer)
774
-#define BLK_DS(s) ((s)->ds)
775766 #define BLK_PINGPONG(s) ((s)->pingpong)
776
-#define BLK_CDM(s) ((s)->cdm)
777767 #define BLK_INTF(s) ((s)->intf)
778768 #define BLK_AD(s) ((s)->ad)
769
+#define BLK_DSPP(s) ((s)->dspp)
779770 
780771 /**
781772  * dpu_hw_catalog_init - dpu hardware catalog init API retrieves
....@@ -792,13 +783,4 @@
792783  */
793784 void dpu_hw_catalog_deinit(struct dpu_mdss_cfg *dpu_cfg);
794785 
795
-/**
796
- * dpu_hw_sspp_multirect_enabled - check multirect enabled for the sspp
797
- * @cfg:          pointer to sspp cfg
798
- */
799
-static inline bool dpu_hw_sspp_multirect_enabled(const struct dpu_sspp_cfg *cfg)
800
-{
801
-	return test_bit(DPU_SSPP_SMART_DMA_V1, &cfg->features) ||
802
-			 test_bit(DPU_SSPP_SMART_DMA_V2, &cfg->features);
803
-}
804786 #endif /* _DPU_HW_CATALOG_H */