forked from ~ljy/RK356X_SDK_RELEASE
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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
....@@ -1,13 +1,5 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
2
- *
3
- * This program is free software; you can redistribute it and/or modify
4
- * it under the terms of the GNU General Public License version 2 and
5
- * only version 2 as published by the Free Software Foundation.
6
- *
7
- * This program is distributed in the hope that it will be useful,
8
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
9
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
10
- * GNU General Public License for more details.
113  */
124 
135 #define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
....@@ -18,14 +10,14 @@
1810 #include "dpu_trace.h"
1911 
2012 #define DPU_DEBUG_VIDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \
21
-		(e) && (e)->base.parent ? \
22
-		(e)->base.parent->base.id : -1, \
13
+		(e) && (e)->parent ? \
14
+		(e)->parent->base.id : -1, \
2315 		(e) && (e)->hw_intf ? \
2416 		(e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
2517 
2618 #define DPU_ERROR_VIDENC(e, fmt, ...) DPU_ERROR("enc%d intf%d " fmt, \
27
-		(e) && (e)->base.parent ? \
28
-		(e)->base.parent->base.id : -1, \
19
+		(e) && (e)->parent ? \
20
+		(e)->parent->base.id : -1, \
2921 		(e) && (e)->hw_intf ? \
3022 		(e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
3123 
....@@ -44,7 +36,7 @@
4436 }
4537 
4638 static void drm_mode_to_intf_timing_params(
47
-		const struct dpu_encoder_phys_vid *vid_enc,
39
+		const struct dpu_encoder_phys *phys_enc,
4840 		const struct drm_display_mode *mode,
4941 		struct intf_timing_params *timing)
5042 {
....@@ -92,7 +84,7 @@
9284 	timing->hsync_skew = mode->hskew;
9385 
9486 	/* DSI controller cannot handle active-low sync signals. */
95
-	if (vid_enc->hw_intf->cap->type == INTF_DSI) {
87
+	if (phys_enc->hw_intf->cap->type == INTF_DSI) {
9688 		timing->hsync_polarity = 0;
9789 		timing->vsync_polarity = 0;
9890 	}
....@@ -108,9 +100,17 @@
108100 	 * display_v_end -= mode->hsync_start - mode->hdisplay;
109101 	 * }
110102 	 */
103
+	/* for DP/EDP, Shift timings to align it to bottom right */
104
+	if ((phys_enc->hw_intf->cap->type == INTF_DP) ||
105
+		(phys_enc->hw_intf->cap->type == INTF_EDP)) {
106
+		timing->h_back_porch += timing->h_front_porch;
107
+		timing->h_front_porch = 0;
108
+		timing->v_back_porch += timing->v_front_porch;
109
+		timing->v_front_porch = 0;
110
+	}
111111 }
112112 
113
-static inline u32 get_horizontal_total(const struct intf_timing_params *timing)
113
+static u32 get_horizontal_total(const struct intf_timing_params *timing)
114114 {
115115 	u32 active = timing->xres;
116116 	u32 inactive =
....@@ -119,7 +119,7 @@
119119 	return active + inactive;
120120 }
121121 
122
-static inline u32 get_vertical_total(const struct intf_timing_params *timing)
122
+static u32 get_vertical_total(const struct intf_timing_params *timing)
123123 {
124124 	u32 active = timing->yres;
125125 	u32 inactive =
....@@ -143,11 +143,11 @@
143143  * lines based on the chip worst case latencies.
144144  */
145145 static u32 programmable_fetch_get_num_lines(
146
-		struct dpu_encoder_phys_vid *vid_enc,
146
+		struct dpu_encoder_phys *phys_enc,
147147 		const struct intf_timing_params *timing)
148148 {
149149 	u32 worst_case_needed_lines =
150
-	    vid_enc->hw_intf->cap->prog_fetch_lines_worst_case;
150
+	    phys_enc->hw_intf->cap->prog_fetch_lines_worst_case;
151151 	u32 start_of_frame_lines =
152152 	    timing->v_back_porch + timing->vsync_pulse_width;
153153 	u32 needed_vfp_lines = worst_case_needed_lines - start_of_frame_lines;
....@@ -155,26 +155,26 @@
155155 
156156 	/* Fetch must be outside active lines, otherwise undefined. */
157157 	if (start_of_frame_lines >= worst_case_needed_lines) {
158
-		DPU_DEBUG_VIDENC(vid_enc,
158
+		DPU_DEBUG_VIDENC(phys_enc,
159159 				"prog fetch is not needed, large vbp+vsw\n");
160160 		actual_vfp_lines = 0;
161161 	} else if (timing->v_front_porch < needed_vfp_lines) {
162162 		/* Warn fetch needed, but not enough porch in panel config */
163163 		pr_warn_once
164164 			("low vbp+vfp may lead to perf issues in some cases\n");
165
-		DPU_DEBUG_VIDENC(vid_enc,
165
+		DPU_DEBUG_VIDENC(phys_enc,
166166 				"less vfp than fetch req, using entire vfp\n");
167167 		actual_vfp_lines = timing->v_front_porch;
168168 	} else {
169
-		DPU_DEBUG_VIDENC(vid_enc, "room in vfp for needed prefetch\n");
169
+		DPU_DEBUG_VIDENC(phys_enc, "room in vfp for needed prefetch\n");
170170 		actual_vfp_lines = needed_vfp_lines;
171171 	}
172172 
173
-	DPU_DEBUG_VIDENC(vid_enc,
173
+	DPU_DEBUG_VIDENC(phys_enc,
174174 		"v_front_porch %u v_back_porch %u vsync_pulse_width %u\n",
175175 		timing->v_front_porch, timing->v_back_porch,
176176 		timing->vsync_pulse_width);
177
-	DPU_DEBUG_VIDENC(vid_enc,
177
+	DPU_DEBUG_VIDENC(phys_enc,
178178 		"wc_lines %u needed_vfp_lines %u actual_vfp_lines %u\n",
179179 		worst_case_needed_lines, needed_vfp_lines, actual_vfp_lines);
180180 
....@@ -194,8 +194,6 @@
194194 static void programmable_fetch_config(struct dpu_encoder_phys *phys_enc,
195195 				      const struct intf_timing_params *timing)
196196 {
197
-	struct dpu_encoder_phys_vid *vid_enc =
198
-		to_dpu_encoder_phys_vid(phys_enc);
199197 	struct intf_prog_fetch f = { 0 };
200198 	u32 vfp_fetch_lines = 0;
201199 	u32 horiz_total = 0;
....@@ -203,10 +201,10 @@
203201 	u32 vfp_fetch_start_vsync_counter = 0;
204202 	unsigned long lock_flags;
205203 
206
-	if (WARN_ON_ONCE(!vid_enc->hw_intf->ops.setup_prg_fetch))
204
+	if (WARN_ON_ONCE(!phys_enc->hw_intf->ops.setup_prg_fetch))
207205 		return;
208206 
209
-	vfp_fetch_lines = programmable_fetch_get_num_lines(vid_enc, timing);
207
+	vfp_fetch_lines = programmable_fetch_get_num_lines(phys_enc, timing);
210208 	if (vfp_fetch_lines) {
211209 		vert_total = get_vertical_total(timing);
212210 		horiz_total = get_horizontal_total(timing);
....@@ -216,12 +214,12 @@
216214 		f.fetch_start = vfp_fetch_start_vsync_counter;
217215 	}
218216 
219
-	DPU_DEBUG_VIDENC(vid_enc,
217
+	DPU_DEBUG_VIDENC(phys_enc,
220218 		"vfp_fetch_lines %u vfp_fetch_start_vsync_counter %u\n",
221219 		vfp_fetch_lines, vfp_fetch_start_vsync_counter);
222220 
223221 	spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
224
-	vid_enc->hw_intf->ops.setup_prg_fetch(vid_enc->hw_intf, &f);
222
+	phys_enc->hw_intf->ops.setup_prg_fetch(phys_enc->hw_intf, &f);
225223 	spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
226224 }
227225 
....@@ -230,8 +228,7 @@
230228 		const struct drm_display_mode *mode,
231229 		struct drm_display_mode *adj_mode)
232230 {
233
-	if (phys_enc)
234
-		DPU_DEBUG_VIDENC(to_dpu_encoder_phys_vid(phys_enc), "\n");
231
+	DPU_DEBUG_VIDENC(phys_enc, "\n");
235232 
236233 	/*
237234 	 * Modifying mode has consequences when the mode comes back to us
....@@ -242,7 +239,6 @@
242239 static void dpu_encoder_phys_vid_setup_timing_engine(
243240 		struct dpu_encoder_phys *phys_enc)
244241 {
245
-	struct dpu_encoder_phys_vid *vid_enc;
246242 	struct drm_display_mode mode;
247243 	struct intf_timing_params timing_params = { 0 };
248244 	const struct dpu_format *fmt = NULL;
....@@ -250,19 +246,18 @@
250246 	unsigned long lock_flags;
251247 	struct dpu_hw_intf_cfg intf_cfg = { 0 };
252248 
253
-	if (!phys_enc || !phys_enc->hw_ctl->ops.setup_intf_cfg) {
254
-		DPU_ERROR("invalid encoder %d\n", phys_enc != 0);
249
+	if (!phys_enc->hw_ctl->ops.setup_intf_cfg) {
250
+		DPU_ERROR("invalid encoder %d\n", phys_enc != NULL);
255251 		return;
256252 	}
257253 
258254 	mode = phys_enc->cached_mode;
259
-	vid_enc = to_dpu_encoder_phys_vid(phys_enc);
260
-	if (!vid_enc->hw_intf->ops.setup_timing_gen) {
255
+	if (!phys_enc->hw_intf->ops.setup_timing_gen) {
261256 		DPU_ERROR("timing engine setup is not supported\n");
262257 		return;
263258 	}
264259 
265
-	DPU_DEBUG_VIDENC(vid_enc, "enabling mode:\n");
260
+	DPU_DEBUG_VIDENC(phys_enc, "enabling mode:\n");
266261 	drm_mode_debug_printmodeline(&mode);
267262 
268263 	if (phys_enc->split_role != ENC_ROLE_SOLO) {
....@@ -271,32 +266,38 @@
271266 		mode.hsync_start >>= 1;
272267 		mode.hsync_end >>= 1;
273268 
274
-		DPU_DEBUG_VIDENC(vid_enc,
269
+		DPU_DEBUG_VIDENC(phys_enc,
275270 			"split_role %d, halve horizontal %d %d %d %d\n",
276271 			phys_enc->split_role,
277272 			mode.hdisplay, mode.htotal,
278273 			mode.hsync_start, mode.hsync_end);
279274 	}
280275 
281
-	drm_mode_to_intf_timing_params(vid_enc, &mode, &timing_params);
276
+	drm_mode_to_intf_timing_params(phys_enc, &mode, &timing_params);
282277 
283278 	fmt = dpu_get_dpu_format(fmt_fourcc);
284
-	DPU_DEBUG_VIDENC(vid_enc, "fmt_fourcc 0x%X\n", fmt_fourcc);
279
+	DPU_DEBUG_VIDENC(phys_enc, "fmt_fourcc 0x%X\n", fmt_fourcc);
285280 
286
-	intf_cfg.intf = vid_enc->hw_intf->idx;
281
+	intf_cfg.intf = phys_enc->hw_intf->idx;
287282 	intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID;
288283 	intf_cfg.stream_sel = 0; /* Don't care value for video mode */
289284 	intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
290285 
291286 	spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
292
-	vid_enc->hw_intf->ops.setup_timing_gen(vid_enc->hw_intf,
287
+	phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf,
293288 			&timing_params, fmt);
294289 	phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
290
+
291
+	/* setup which pp blk will connect to this intf */
292
+	if (phys_enc->hw_intf->ops.bind_pingpong_blk)
293
+		phys_enc->hw_intf->ops.bind_pingpong_blk(
294
+				phys_enc->hw_intf,
295
+				true,
296
+				phys_enc->hw_pp->idx);
297
+
295298 	spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
296299 
297300 	programmable_fetch_config(phys_enc, &timing_params);
298
-
299
-	vid_enc->timing_params = timing_params;
300301 }
301302 
302303 static void dpu_encoder_phys_vid_vblank_irq(void *arg, int irq_idx)
....@@ -305,14 +306,8 @@
305306 	struct dpu_hw_ctl *hw_ctl;
306307 	unsigned long lock_flags;
307308 	u32 flush_register = 0;
308
-	int new_cnt = -1, old_cnt = -1;
309
-
310
-	if (!phys_enc)
311
-		return;
312309 
313310 	hw_ctl = phys_enc->hw_ctl;
314
-	if (!hw_ctl)
315
-		return;
316311 
317312 	DPU_ATRACE_BEGIN("vblank_irq");
318313 
....@@ -320,7 +315,7 @@
320315 		phys_enc->parent_ops->handle_vblank_virt(phys_enc->parent,
321316 				phys_enc);
322317 
323
-	old_cnt  = atomic_read(&phys_enc->pending_kickoff_cnt);
318
+	atomic_read(&phys_enc->pending_kickoff_cnt);
324319 
325320 	/*
326321 	 * only decrement the pending flush count if we've actually flushed
....@@ -328,16 +323,19 @@
328323 	 * so we need to double-check with hw that it accepted the flush bits
329324 	 */
330325 	spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
331
-	if (hw_ctl && hw_ctl->ops.get_flush_register)
326
+	if (hw_ctl->ops.get_flush_register)
332327 		flush_register = hw_ctl->ops.get_flush_register(hw_ctl);
333328 
334329 	if (!(flush_register & hw_ctl->ops.get_pending_flush(hw_ctl)))
335
-		new_cnt = atomic_add_unless(&phys_enc->pending_kickoff_cnt,
336
-				-1, 0);
330
+		atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
337331 	spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
338332 
339333 	/* Signal any waiting atomic commit thread */
340334 	wake_up_all(&phys_enc->pending_kickoff_wq);
335
+
336
+	phys_enc->parent_ops->handle_frame_done(phys_enc->parent, phys_enc,
337
+			DPU_ENCODER_FRAME_EVENT_DONE);
338
+
341339 	DPU_ATRACE_END("vblank_irq");
342340 }
343341 
....@@ -345,29 +343,15 @@
345343 {
346344 	struct dpu_encoder_phys *phys_enc = arg;
347345 
348
-	if (!phys_enc)
349
-		return;
350
-
351346 	if (phys_enc->parent_ops->handle_underrun_virt)
352347 		phys_enc->parent_ops->handle_underrun_virt(phys_enc->parent,
353348 			phys_enc);
354349 }
355350 
356
-static bool _dpu_encoder_phys_is_dual_ctl(struct dpu_encoder_phys *phys_enc)
357
-{
358
-	if (!phys_enc)
359
-		return false;
360
-
361
-	if (phys_enc->topology_name == DPU_RM_TOPOLOGY_DUALPIPE)
362
-		return true;
363
-
364
-	return false;
365
-}
366
-
367351 static bool dpu_encoder_phys_vid_needs_single_flush(
368352 		struct dpu_encoder_phys *phys_enc)
369353 {
370
-	return (phys_enc && _dpu_encoder_phys_is_dual_ctl(phys_enc));
354
+	return phys_enc->split_role != ENC_ROLE_SOLO;
371355 }
372356 
373357 static void _dpu_encoder_phys_vid_setup_irq_hw_idx(
....@@ -395,38 +379,10 @@
395379 		struct drm_display_mode *mode,
396380 		struct drm_display_mode *adj_mode)
397381 {
398
-	struct dpu_rm *rm;
399
-	struct dpu_rm_hw_iter iter;
400
-	int i, instance;
401
-	struct dpu_encoder_phys_vid *vid_enc;
402
-
403
-	if (!phys_enc || !phys_enc->dpu_kms) {
404
-		DPU_ERROR("invalid encoder/kms\n");
405
-		return;
406
-	}
407
-
408
-	rm = &phys_enc->dpu_kms->rm;
409
-	vid_enc = to_dpu_encoder_phys_vid(phys_enc);
410
-
411382 	if (adj_mode) {
412383 		phys_enc->cached_mode = *adj_mode;
413384 		drm_mode_debug_printmodeline(adj_mode);
414
-		DPU_DEBUG_VIDENC(vid_enc, "caching mode:\n");
415
-	}
416
-
417
-	instance = phys_enc->split_role == ENC_ROLE_SLAVE ? 1 : 0;
418
-
419
-	/* Retrieve previously allocated HW Resources. Shouldn't fail */
420
-	dpu_rm_init_hw_iter(&iter, phys_enc->parent->base.id, DPU_HW_BLK_CTL);
421
-	for (i = 0; i <= instance; i++) {
422
-		if (dpu_rm_get_hw(rm, &iter))
423
-			phys_enc->hw_ctl = (struct dpu_hw_ctl *)iter.hw;
424
-	}
425
-	if (IS_ERR_OR_NULL(phys_enc->hw_ctl)) {
426
-		DPU_ERROR_VIDENC(vid_enc, "failed to init ctl, %ld\n",
427
-				PTR_ERR(phys_enc->hw_ctl));
428
-		phys_enc->hw_ctl = NULL;
429
-		return;
385
+		DPU_DEBUG_VIDENC(phys_enc, "caching mode:\n");
430386 	}
431387 
432388 	_dpu_encoder_phys_vid_setup_irq_hw_idx(phys_enc);
....@@ -437,16 +393,9 @@
437393 		bool enable)
438394 {
439395 	int ret = 0;
440
-	struct dpu_encoder_phys_vid *vid_enc;
441396 	int refcount;
442397 
443
-	if (!phys_enc) {
444
-		DPU_ERROR("invalid encoder\n");
445
-		return -EINVAL;
446
-	}
447
-
448398 	refcount = atomic_read(&phys_enc->vblank_refcount);
449
-	vid_enc = to_dpu_encoder_phys_vid(phys_enc);
450399 
451400 	/* Slave encoders don't report vblank */
452401 	if (!dpu_encoder_phys_vid_is_master(phys_enc))
....@@ -471,7 +420,7 @@
471420 	if (ret) {
472421 		DRM_ERROR("failed: id:%u intf:%d ret:%d enable:%d refcnt:%d\n",
473422 			  DRMID(phys_enc->parent),
474
-			  vid_enc->hw_intf->idx - INTF_0, ret, enable,
423
+			  phys_enc->hw_intf->idx - INTF_0, ret, enable,
475424 			  refcount);
476425 	}
477426 	return ret;
....@@ -479,34 +428,18 @@
479428 
480429 static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)
481430 {
482
-	struct msm_drm_private *priv;
483
-	struct dpu_encoder_phys_vid *vid_enc;
484
-	struct dpu_hw_intf *intf;
485431 	struct dpu_hw_ctl *ctl;
486432 	u32 flush_mask = 0;
433
+	u32 intf_flush_mask = 0;
487434 
488
-	if (!phys_enc || !phys_enc->parent || !phys_enc->parent->dev ||
489
-			!phys_enc->parent->dev->dev_private) {
490
-		DPU_ERROR("invalid encoder/device\n");
491
-		return;
492
-	}
493
-	priv = phys_enc->parent->dev->dev_private;
494
-
495
-	vid_enc = to_dpu_encoder_phys_vid(phys_enc);
496
-	intf = vid_enc->hw_intf;
497435 	ctl = phys_enc->hw_ctl;
498
-	if (!vid_enc->hw_intf || !phys_enc->hw_ctl) {
499
-		DPU_ERROR("invalid hw_intf %d hw_ctl %d\n",
500
-				vid_enc->hw_intf != 0, phys_enc->hw_ctl != 0);
501
-		return;
502
-	}
503436 
504
-	DPU_DEBUG_VIDENC(vid_enc, "\n");
437
+	DPU_DEBUG_VIDENC(phys_enc, "\n");
505438 
506
-	if (WARN_ON(!vid_enc->hw_intf->ops.enable_timing))
439
+	if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing))
507440 		return;
508441 
509
-	dpu_encoder_helper_split_config(phys_enc, vid_enc->hw_intf->idx);
442
+	dpu_encoder_helper_split_config(phys_enc, phys_enc->hw_intf->idx);
510443 
511444 	dpu_encoder_phys_vid_setup_timing_engine(phys_enc);
512445 
....@@ -519,12 +452,21 @@
519452 		!dpu_encoder_phys_vid_is_master(phys_enc))
520453 		goto skip_flush;
521454 
522
-	ctl->ops.get_bitmask_intf(ctl, &flush_mask, intf->idx);
455
+	ctl->ops.get_bitmask_intf(ctl, &flush_mask, phys_enc->hw_intf->idx);
523456 	ctl->ops.update_pending_flush(ctl, flush_mask);
524457 
458
+	if (ctl->ops.get_bitmask_active_intf)
459
+		ctl->ops.get_bitmask_active_intf(ctl, &intf_flush_mask,
460
+			phys_enc->hw_intf->idx);
461
+
462
+	if (ctl->ops.update_pending_intf_flush)
463
+		ctl->ops.update_pending_intf_flush(ctl, intf_flush_mask);
464
+
525465 skip_flush:
526
-	DPU_DEBUG_VIDENC(vid_enc, "update pending flush ctl %d flush_mask %x\n",
527
-		ctl->idx - CTL_0, flush_mask);
466
+	DPU_DEBUG_VIDENC(phys_enc,
467
+		"update pending flush ctl %d flush_mask 0%x intf_mask 0x%x\n",
468
+		ctl->idx - CTL_0, flush_mask, intf_flush_mask);
469
+
528470 
529471 	/* ctl_flush & timing engine enable will be triggered by framework */
530472 	if (phys_enc->enable_state == DPU_ENC_DISABLED)
....@@ -533,61 +475,28 @@
533475 
534476 static void dpu_encoder_phys_vid_destroy(struct dpu_encoder_phys *phys_enc)
535477 {
536
-	struct dpu_encoder_phys_vid *vid_enc;
537
-
538
-	if (!phys_enc) {
539
-		DPU_ERROR("invalid encoder\n");
540
-		return;
541
-	}
542
-
543
-	vid_enc = to_dpu_encoder_phys_vid(phys_enc);
544
-	DPU_DEBUG_VIDENC(vid_enc, "\n");
545
-	kfree(vid_enc);
478
+	DPU_DEBUG_VIDENC(phys_enc, "\n");
479
+	kfree(phys_enc);
546480 }
547481 
548482 static void dpu_encoder_phys_vid_get_hw_resources(
549483 		struct dpu_encoder_phys *phys_enc,
550
-		struct dpu_encoder_hw_resources *hw_res,
551
-		struct drm_connector_state *conn_state)
484
+		struct dpu_encoder_hw_resources *hw_res)
552485 {
553
-	struct dpu_encoder_phys_vid *vid_enc;
554
-
555
-	if (!phys_enc || !hw_res) {
556
-		DPU_ERROR("invalid arg(s), enc %d hw_res %d conn_state %d\n",
557
-				phys_enc != 0, hw_res != 0, conn_state != 0);
558
-		return;
559
-	}
560
-
561
-	vid_enc = to_dpu_encoder_phys_vid(phys_enc);
562
-	if (!vid_enc->hw_intf) {
563
-		DPU_ERROR("invalid arg(s), hw_intf\n");
564
-		return;
565
-	}
566
-
567
-	DPU_DEBUG_VIDENC(vid_enc, "\n");
568
-	hw_res->intfs[vid_enc->hw_intf->idx - INTF_0] = INTF_MODE_VIDEO;
486
+	hw_res->intfs[phys_enc->intf_idx - INTF_0] = INTF_MODE_VIDEO;
569487 }
570488 
571
-static int _dpu_encoder_phys_vid_wait_for_vblank(
572
-		struct dpu_encoder_phys *phys_enc, bool notify)
489
+static int dpu_encoder_phys_vid_wait_for_vblank(
490
+		struct dpu_encoder_phys *phys_enc)
573491 {
574492 	struct dpu_encoder_wait_info wait_info;
575493 	int ret;
576
-
577
-	if (!phys_enc) {
578
-		pr_err("invalid encoder\n");
579
-		return -EINVAL;
580
-	}
581494 
582495 	wait_info.wq = &phys_enc->pending_kickoff_wq;
583496 	wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt;
584497 	wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
585498 
586499 	if (!dpu_encoder_phys_vid_is_master(phys_enc)) {
587
-		if (notify && phys_enc->parent_ops->handle_frame_done)
588
-			phys_enc->parent_ops->handle_frame_done(
589
-					phys_enc->parent, phys_enc,
590
-					DPU_ENCODER_FRAME_EVENT_DONE);
591500 		return 0;
592501 	}
593502 
....@@ -597,36 +506,39 @@
597506 
598507 	if (ret == -ETIMEDOUT) {
599508 		dpu_encoder_helper_report_irq_timeout(phys_enc, INTR_IDX_VSYNC);
600
-	} else if (!ret && notify && phys_enc->parent_ops->handle_frame_done)
601
-		phys_enc->parent_ops->handle_frame_done(
602
-				phys_enc->parent, phys_enc,
603
-				DPU_ENCODER_FRAME_EVENT_DONE);
509
+	}
604510 
605511 	return ret;
606512 }
607513 
608
-static int dpu_encoder_phys_vid_wait_for_vblank(
514
+static int dpu_encoder_phys_vid_wait_for_commit_done(
609515 		struct dpu_encoder_phys *phys_enc)
610516 {
611
-	return _dpu_encoder_phys_vid_wait_for_vblank(phys_enc, true);
517
+	struct dpu_hw_ctl *hw_ctl = phys_enc->hw_ctl;
518
+	int ret;
519
+
520
+	if (!hw_ctl)
521
+		return 0;
522
+
523
+	ret = wait_event_timeout(phys_enc->pending_kickoff_wq,
524
+		(hw_ctl->ops.get_flush_register(hw_ctl) == 0),
525
+		msecs_to_jiffies(50));
526
+	if (ret <= 0) {
527
+		DPU_ERROR("vblank timeout\n");
528
+		return -ETIMEDOUT;
529
+	}
530
+
531
+	return 0;
612532 }
613533 
614534 static void dpu_encoder_phys_vid_prepare_for_kickoff(
615
-		struct dpu_encoder_phys *phys_enc,
616
-		struct dpu_encoder_kickoff_params *params)
535
+		struct dpu_encoder_phys *phys_enc)
617536 {
618
-	struct dpu_encoder_phys_vid *vid_enc;
619537 	struct dpu_hw_ctl *ctl;
620538 	int rc;
621539 
622
-	if (!phys_enc || !params) {
623
-		DPU_ERROR("invalid encoder/parameters\n");
624
-		return;
625
-	}
626
-	vid_enc = to_dpu_encoder_phys_vid(phys_enc);
627
-
628540 	ctl = phys_enc->hw_ctl;
629
-	if (!ctl || !ctl->ops.wait_reset_status)
541
+	if (!ctl->ops.wait_reset_status)
630542 		return;
631543 
632544 	/*
....@@ -635,37 +547,29 @@
635547 	 */
636548 	rc = ctl->ops.wait_reset_status(ctl);
637549 	if (rc) {
638
-		DPU_ERROR_VIDENC(vid_enc, "ctl %d reset failure: %d\n",
550
+		DPU_ERROR_VIDENC(phys_enc, "ctl %d reset failure: %d\n",
639551 				ctl->idx, rc);
640552 		dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_VSYNC);
641
-		dpu_dbg_dump(false, __func__, true, true);
642553 	}
643554 }
644555 
645556 static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc)
646557 {
647
-	struct msm_drm_private *priv;
648
-	struct dpu_encoder_phys_vid *vid_enc;
649558 	unsigned long lock_flags;
650559 	int ret;
651560 
652
-	if (!phys_enc || !phys_enc->parent || !phys_enc->parent->dev ||
653
-			!phys_enc->parent->dev->dev_private) {
561
+	if (!phys_enc->parent || !phys_enc->parent->dev) {
654562 		DPU_ERROR("invalid encoder/device\n");
655563 		return;
656564 	}
657
-	priv = phys_enc->parent->dev->dev_private;
658565 
659
-	vid_enc = to_dpu_encoder_phys_vid(phys_enc);
660
-	if (!vid_enc->hw_intf || !phys_enc->hw_ctl) {
566
+	if (!phys_enc->hw_intf) {
661567 		DPU_ERROR("invalid hw_intf %d hw_ctl %d\n",
662
-				vid_enc->hw_intf != 0, phys_enc->hw_ctl != 0);
568
+				phys_enc->hw_intf != NULL, phys_enc->hw_ctl != NULL);
663569 		return;
664570 	}
665571 
666
-	DPU_DEBUG_VIDENC(vid_enc, "\n");
667
-
668
-	if (WARN_ON(!vid_enc->hw_intf->ops.enable_timing))
572
+	if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing))
669573 		return;
670574 
671575 	if (phys_enc->enable_state == DPU_ENC_DISABLED) {
....@@ -674,7 +578,7 @@
674578 	}
675579 
676580 	spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
677
-	vid_enc->hw_intf->ops.enable_timing(vid_enc->hw_intf, 0);
581
+	phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 0);
678582 	if (dpu_encoder_phys_vid_is_master(phys_enc))
679583 		dpu_encoder_phys_inc_pending(phys_enc);
680584 	spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
....@@ -688,12 +592,12 @@
688592 	 * scanout buffer) don't latch properly..
689593 	 */
690594 	if (dpu_encoder_phys_vid_is_master(phys_enc)) {
691
-		ret = _dpu_encoder_phys_vid_wait_for_vblank(phys_enc, false);
595
+		ret = dpu_encoder_phys_vid_wait_for_vblank(phys_enc);
692596 		if (ret) {
693597 			atomic_set(&phys_enc->pending_kickoff_cnt, 0);
694598 			DRM_ERROR("wait disable failed: id:%u intf:%d ret:%d\n",
695599 				  DRMID(phys_enc->parent),
696
-				  vid_enc->hw_intf->idx - INTF_0, ret);
600
+				  phys_enc->hw_intf->idx - INTF_0, ret);
697601 		}
698602 	}
699603 
....@@ -704,15 +608,6 @@
704608 		struct dpu_encoder_phys *phys_enc)
705609 {
706610 	unsigned long lock_flags;
707
-	struct dpu_encoder_phys_vid *vid_enc;
708
-
709
-	if (!phys_enc) {
710
-		DPU_ERROR("invalid encoder\n");
711
-		return;
712
-	}
713
-
714
-	vid_enc = to_dpu_encoder_phys_vid(phys_enc);
715
-	DPU_DEBUG_VIDENC(vid_enc, "enable_state %d\n", phys_enc->enable_state);
716611 
717612 	/*
718613 	 * Video mode must flush CTL before enabling timing engine
....@@ -720,9 +615,9 @@
720615 	 */
721616 	if (phys_enc->enable_state == DPU_ENC_ENABLING) {
722617 		trace_dpu_enc_phys_vid_post_kickoff(DRMID(phys_enc->parent),
723
-				    vid_enc->hw_intf->idx - INTF_0);
618
+				    phys_enc->hw_intf->idx - INTF_0);
724619 		spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
725
-		vid_enc->hw_intf->ops.enable_timing(vid_enc->hw_intf, 1);
620
+		phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 1);
726621 		spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
727622 		phys_enc->enable_state = DPU_ENC_ENABLED;
728623 	}
....@@ -731,16 +626,10 @@
731626 static void dpu_encoder_phys_vid_irq_control(struct dpu_encoder_phys *phys_enc,
732627 		bool enable)
733628 {
734
-	struct dpu_encoder_phys_vid *vid_enc;
735629 	int ret;
736630 
737
-	if (!phys_enc)
738
-		return;
739
-
740
-	vid_enc = to_dpu_encoder_phys_vid(phys_enc);
741
-
742631 	trace_dpu_enc_phys_vid_irq_ctrl(DRMID(phys_enc->parent),
743
-			    vid_enc->hw_intf->idx - INTF_0,
632
+			    phys_enc->hw_intf->idx - INTF_0,
744633 			    enable,
745634 			    atomic_read(&phys_enc->vblank_refcount));
746635 
....@@ -756,48 +645,16 @@
756645 	}
757646 }
758647 
759
-static void dpu_encoder_phys_vid_setup_misr(struct dpu_encoder_phys *phys_enc,
760
-						bool enable, u32 frame_count)
761
-{
762
-	struct dpu_encoder_phys_vid *vid_enc;
763
-
764
-	if (!phys_enc)
765
-		return;
766
-	vid_enc = to_dpu_encoder_phys_vid(phys_enc);
767
-
768
-	if (vid_enc->hw_intf && vid_enc->hw_intf->ops.setup_misr)
769
-		vid_enc->hw_intf->ops.setup_misr(vid_enc->hw_intf,
770
-							enable, frame_count);
771
-}
772
-
773
-static u32 dpu_encoder_phys_vid_collect_misr(struct dpu_encoder_phys *phys_enc)
774
-{
775
-	struct dpu_encoder_phys_vid *vid_enc;
776
-
777
-	if (!phys_enc)
778
-		return 0;
779
-	vid_enc = to_dpu_encoder_phys_vid(phys_enc);
780
-
781
-	return vid_enc->hw_intf && vid_enc->hw_intf->ops.collect_misr ?
782
-		vid_enc->hw_intf->ops.collect_misr(vid_enc->hw_intf) : 0;
783
-}
784
-
785648 static int dpu_encoder_phys_vid_get_line_count(
786649 		struct dpu_encoder_phys *phys_enc)
787650 {
788
-	struct dpu_encoder_phys_vid *vid_enc;
789
-
790
-	if (!phys_enc)
791
-		return -EINVAL;
792
-
793651 	if (!dpu_encoder_phys_vid_is_master(phys_enc))
794652 		return -EINVAL;
795653 
796
-	vid_enc = to_dpu_encoder_phys_vid(phys_enc);
797
-	if (!vid_enc->hw_intf || !vid_enc->hw_intf->ops.get_line_count)
654
+	if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_line_count)
798655 		return -EINVAL;
799656 
800
-	return vid_enc->hw_intf->ops.get_line_count(vid_enc->hw_intf);
657
+	return phys_enc->hw_intf->ops.get_line_count(phys_enc->hw_intf);
801658 }
802659 
803660 static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops)
....@@ -810,16 +667,13 @@
810667 	ops->destroy = dpu_encoder_phys_vid_destroy;
811668 	ops->get_hw_resources = dpu_encoder_phys_vid_get_hw_resources;
812669 	ops->control_vblank_irq = dpu_encoder_phys_vid_control_vblank_irq;
813
-	ops->wait_for_commit_done = dpu_encoder_phys_vid_wait_for_vblank;
670
+	ops->wait_for_commit_done = dpu_encoder_phys_vid_wait_for_commit_done;
814671 	ops->wait_for_vblank = dpu_encoder_phys_vid_wait_for_vblank;
815672 	ops->wait_for_tx_complete = dpu_encoder_phys_vid_wait_for_vblank;
816673 	ops->irq_control = dpu_encoder_phys_vid_irq_control;
817674 	ops->prepare_for_kickoff = dpu_encoder_phys_vid_prepare_for_kickoff;
818675 	ops->handle_post_kickoff = dpu_encoder_phys_vid_handle_post_kickoff;
819676 	ops->needs_single_flush = dpu_encoder_phys_vid_needs_single_flush;
820
-	ops->setup_misr = dpu_encoder_phys_vid_setup_misr;
821
-	ops->collect_misr = dpu_encoder_phys_vid_collect_misr;
822
-	ops->hw_reset = dpu_encoder_helper_hw_reset;
823677 	ops->get_line_count = dpu_encoder_phys_vid_get_line_count;
824678 }
825679 
....@@ -827,9 +681,6 @@
827681 		struct dpu_enc_phys_init_params *p)
828682 {
829683 	struct dpu_encoder_phys *phys_enc = NULL;
830
-	struct dpu_encoder_phys_vid *vid_enc = NULL;
831
-	struct dpu_rm_hw_iter iter;
832
-	struct dpu_hw_mdp *hw_mdp;
833684 	struct dpu_encoder_irq *irq;
834685 	int i, ret = 0;
835686 
....@@ -838,44 +689,16 @@
838689 		goto fail;
839690 	}
840691 
841
-	vid_enc = kzalloc(sizeof(*vid_enc), GFP_KERNEL);
842
-	if (!vid_enc) {
692
+	phys_enc = kzalloc(sizeof(*phys_enc), GFP_KERNEL);
693
+	if (!phys_enc) {
843694 		ret = -ENOMEM;
844695 		goto fail;
845696 	}
846697 
847
-	phys_enc = &vid_enc->base;
848
-
849
-	hw_mdp = dpu_rm_get_mdp(&p->dpu_kms->rm);
850
-	if (IS_ERR_OR_NULL(hw_mdp)) {
851
-		ret = PTR_ERR(hw_mdp);
852
-		DPU_ERROR("failed to get mdptop\n");
853
-		goto fail;
854
-	}
855
-	phys_enc->hw_mdptop = hw_mdp;
698
+	phys_enc->hw_mdptop = p->dpu_kms->hw_mdp;
856699 	phys_enc->intf_idx = p->intf_idx;
857700 
858
-	/**
859
-	 * hw_intf resource permanently assigned to this encoder
860
-	 * Other resources allocated at atomic commit time by use case
861
-	 */
862
-	dpu_rm_init_hw_iter(&iter, 0, DPU_HW_BLK_INTF);
863
-	while (dpu_rm_get_hw(&p->dpu_kms->rm, &iter)) {
864
-		struct dpu_hw_intf *hw_intf = (struct dpu_hw_intf *)iter.hw;
865
-
866
-		if (hw_intf->idx == p->intf_idx) {
867
-			vid_enc->hw_intf = hw_intf;
868
-			break;
869
-		}
870
-	}
871
-
872
-	if (!vid_enc->hw_intf) {
873
-		ret = -EINVAL;
874
-		DPU_ERROR("failed to get hw_intf\n");
875
-		goto fail;
876
-	}
877
-
878
-	DPU_DEBUG_VIDENC(vid_enc, "\n");
701
+	DPU_DEBUG_VIDENC(phys_enc, "\n");
879702 
880703 	dpu_encoder_phys_vid_init_ops(&phys_enc->ops);
881704 	phys_enc->parent = p->parent;
....@@ -909,13 +732,13 @@
909732 	init_waitqueue_head(&phys_enc->pending_kickoff_wq);
910733 	phys_enc->enable_state = DPU_ENC_DISABLED;
911734 
912
-	DPU_DEBUG_VIDENC(vid_enc, "created intf idx:%d\n", p->intf_idx);
735
+	DPU_DEBUG_VIDENC(phys_enc, "created intf idx:%d\n", p->intf_idx);
913736 
914737 	return phys_enc;
915738 
916739 fail:
917740 	DPU_ERROR("failed to create encoder\n");
918
-	if (vid_enc)
741
+	if (phys_enc)
919742 		dpu_encoder_phys_vid_destroy(phys_enc);
920743 
921744 	return ERR_PTR(ret);