~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,34 +1,26 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
1	2	/*
2	3	* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
3	4	* Copyright (C) 2013 Red Hat
4	5	* Author: Rob Clark <robdclark@gmail.com>
5		- *
6		- * This program is free software; you can redistribute it and/or modify it
7		- * under the terms of the GNU General Public License version 2 as published by
8		- * the Free Software Foundation.
9		- *
10		- * This program is distributed in the hope that it will be useful, but WITHOUT
11		- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12		- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13		- * more details.
14		- *
15		- * You should have received a copy of the GNU General Public License along with
16		- * this program. If not, see <http://www.gnu.org/licenses/>.
17	6	*/
18	7
19	8	#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
20		-#include <linux/kthread.h>
21	9	#include <linux/debugfs.h>
	10	+#include <linux/kthread.h>
22	11	#include <linux/seq_file.h>
	12	+
	13	+#include <drm/drm_crtc.h>
	14	+#include <drm/drm_file.h>
	15	+#include <drm/drm_probe_helper.h>
23	16
24	17	#include "msm_drv.h"
25	18	#include "dpu_kms.h"
26		-#include <drm/drm_crtc.h>
27		-#include <drm/drm_crtc_helper.h>
28	19	#include "dpu_hwio.h"
29	20	#include "dpu_hw_catalog.h"
30	21	#include "dpu_hw_intf.h"
31	22	#include "dpu_hw_ctl.h"
	23	+#include "dpu_hw_dspp.h"
32	24	#include "dpu_formats.h"
33	25	#include "dpu_encoder_phys.h"
34	26	#include "dpu_crtc.h"
..	..	@@ -65,11 +57,12 @@
65	57
66	58	#define MAX_CHANNELS_PER_ENC 2
67	59
68		-#define MISR_BUFF_SIZE 256
69		-
70	60	#define IDLE_SHORT_TIMEOUT 1
71	61
72		-#define MAX_VDISPLAY_SPLIT 1080
	62	+#define MAX_HDISPLAY_SPLIT 1080
	63	+
	64	+/* timeout in frames waiting for frame done */
	65	+#define DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES 5
73	66
74	67	/**
75	68	* enum dpu_enc_rc_events - events for resource control state machine
..	..	@@ -132,8 +125,9 @@
132	125	* Virtual encoder defers as much as possible to the physical encoders.
133	126	* Virtual encoder registers itself with the DRM Framework as the encoder.
134	127	* @base: drm_encoder base class for registration with DRM
135		- * @enc_spin_lock: Virtual-Encoder-Wide Spin Lock for IRQ purposes
	128	+ * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes
136	129	* @bus_scaling_client: Client handle to the bus scaling interface
	130	+ * @enabled: True if the encoder is active, protected by enc_lock
137	131	* @num_phys_encs: Actual number of physical encoders contained.
138	132	* @phys_encs: Container of physical encoders managed.
139	133	* @cur_master: Pointer to the current master in this mode. Optimization
..	..	@@ -143,26 +137,26 @@
143	137	* @intfs_swapped Whether or not the phys_enc interfaces have been swapped
144	138	* for partial update right-only cases, such as pingpong
145	139	* split where virtual pingpong does not generate IRQs
146		- * @crtc_vblank_cb: Callback into the upper layer / CRTC for
147		- * notification of the VBLANK
148		- * @crtc_vblank_cb_data: Data from upper layer for VBLANK notification
	140	+ * @crtc: Pointer to the currently assigned crtc. Normally you
	141	+ * would use crtc->state->encoder_mask to determine the
	142	+ * link between encoder/crtc. However in this case we need
	143	+ * to track crtc in the disable() hook which is called
	144	+ * _after_ encoder_mask is cleared.
149	145	* @crtc_kickoff_cb: Callback into CRTC that will flush & start
150	146	* all CTL paths
151	147	* @crtc_kickoff_cb_data: Opaque user data given to crtc_kickoff_cb
152	148	* @debugfs_root: Debug file system root file node
153		- * @enc_lock: Lock around physical encoder create/destroy and
154		- access.
	149	+ * @enc_lock: Lock around physical encoder
	150	+ * create/destroy/enable/disable
155	151	* @frame_busy_mask: Bitmask tracking which phys_enc we are still
156	152	* busy processing current command.
157	153	* Bit0 = phys_encs[0] etc.
158	154	* @crtc_frame_event_cb: callback handler for frame event
159	155	* @crtc_frame_event_cb_data: callback handler private data
160		- * @frame_done_timeout: frame done timeout in Hz
	156	+ * @frame_done_timeout_ms: frame done timeout in ms
161	157	* @frame_done_timer: watchdog timer for frame done event
162	158	* @vsync_event_timer: vsync timer
163	159	* @disp_info: local copy of msm_display_info struct
164		- * @misr_enable: misr enable/disable status
165		- * @misr_frame_count: misr frame count before start capturing the data
166	160	* @idle_pc_supported: indicate if idle power collaps is supported
167	161	* @rc_lock: resource control mutex lock to protect
168	162	* virt encoder over various state changes
..	..	@@ -171,7 +165,6 @@
171	165	* clks and resources after IDLE_TIMEOUT time.
172	166	* @vsync_event_work: worker to handle vsync event for autorefresh
173	167	* @topology: topology of the display
174		- * @mode_set_complete: flag to indicate modeset completion
175	168	* @idle_timeout: idle timeout duration in milliseconds
176	169	*/
177	170	struct dpu_encoder_virt {
..	..	@@ -179,17 +172,17 @@
179	172	spinlock_t enc_spinlock;
180	173	uint32_t bus_scaling_client;
181	174
182		- uint32_t display_num_of_h_tiles;
	175	+ bool enabled;
183	176
184	177	unsigned int num_phys_encs;
185	178	struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
186	179	struct dpu_encoder_phys *cur_master;
	180	+ struct dpu_encoder_phys *cur_slave;
187	181	struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
188	182
189	183	bool intfs_swapped;
190	184
191		- void (crtc_vblank_cb)(void );
192		- void *crtc_vblank_cb_data;
	185	+ struct drm_crtc *crtc;
193	186
194	187	struct dentry *debugfs_root;
195	188	struct mutex enc_lock;
..	..	@@ -197,58 +190,52 @@
197	190	void (crtc_frame_event_cb)(void , u32 event);
198	191	void *crtc_frame_event_cb_data;
199	192
200		- atomic_t frame_done_timeout;
	193	+ atomic_t frame_done_timeout_ms;
201	194	struct timer_list frame_done_timer;
202	195	struct timer_list vsync_event_timer;
203	196
204	197	struct msm_display_info disp_info;
205		- bool misr_enable;
206		- u32 misr_frame_count;
207	198
208	199	bool idle_pc_supported;
209	200	struct mutex rc_lock;
210	201	enum dpu_enc_rc_states rc_state;
211		- struct kthread_delayed_work delayed_off_work;
	202	+ struct delayed_work delayed_off_work;
212	203	struct kthread_work vsync_event_work;
213	204	struct msm_display_topology topology;
214		- bool mode_set_complete;
215	205
216	206	u32 idle_timeout;
217	207	};
218	208
219	209	#define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
220		-static inline int _dpu_encoder_power_enable(struct dpu_encoder_virt *dpu_enc,
221		- bool enable)
	210	+
	211	+static u32 dither_matrix[DITHER_MATRIX_SZ] = {
	212	+ 15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
	213	+};
	214	+
	215	+static void _dpu_encoder_setup_dither(struct dpu_hw_pingpong *hw_pp, unsigned bpc)
222	216	{
223		- struct drm_encoder *drm_enc;
224		- struct msm_drm_private *priv;
225		- struct dpu_kms *dpu_kms;
	217	+ struct dpu_hw_dither_cfg dither_cfg = { 0 };
226	218
227		- if (!dpu_enc) {
228		- DPU_ERROR("invalid dpu enc\n");
229		- return -EINVAL;
	219	+ if (!hw_pp->ops.setup_dither)
	220	+ return;
	221	+
	222	+ switch (bpc) {
	223	+ case 6:
	224	+ dither_cfg.c0_bitdepth = 6;
	225	+ dither_cfg.c1_bitdepth = 6;
	226	+ dither_cfg.c2_bitdepth = 6;
	227	+ dither_cfg.c3_bitdepth = 6;
	228	+ dither_cfg.temporal_en = 0;
	229	+ break;
	230	+ default:
	231	+ hw_pp->ops.setup_dither(hw_pp, NULL);
	232	+ return;
230	233	}
231	234
232		- drm_enc = &dpu_enc->base;
233		- if (!drm_enc->dev \|\| !drm_enc->dev->dev_private) {
234		- DPU_ERROR("drm device invalid\n");
235		- return -EINVAL;
236		- }
	235	+ memcpy(&dither_cfg.matrix, dither_matrix,
	236	+ sizeof(u32) * DITHER_MATRIX_SZ);
237	237
238		- priv = drm_enc->dev->dev_private;
239		- if (!priv->kms) {
240		- DPU_ERROR("invalid kms\n");
241		- return -EINVAL;
242		- }
243		-
244		- dpu_kms = to_dpu_kms(priv->kms);
245		-
246		- if (enable)
247		- pm_runtime_get_sync(&dpu_kms->pdev->dev);
248		- else
249		- pm_runtime_put_sync(&dpu_kms->pdev->dev);
250		-
251		- return 0;
	238	+ hw_pp->ops.setup_dither(hw_pp, &dither_cfg);
252	239	}
253	240
254	241	void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc,
..	..	@@ -275,7 +262,7 @@
275	262	u32 irq_status;
276	263	int ret;
277	264
278		- if (!phys_enc \|\| !wait_info \|\| intr_idx >= INTR_IDX_MAX) {
	265	+ if (!wait_info \|\| intr_idx >= INTR_IDX_MAX) {
279	266	DPU_ERROR("invalid params\n");
280	267	return -EINVAL;
281	268	}
..	..	@@ -350,7 +337,7 @@
350	337	struct dpu_encoder_irq *irq;
351	338	int ret = 0;
352	339
353		- if (!phys_enc \|\| intr_idx >= INTR_IDX_MAX) {
	340	+ if (intr_idx >= INTR_IDX_MAX) {
354	341	DPU_ERROR("invalid params\n");
355	342	return -EINVAL;
356	343	}
..	..	@@ -405,10 +392,6 @@
405	392	struct dpu_encoder_irq *irq;
406	393	int ret;
407	394
408		- if (!phys_enc) {
409		- DPU_ERROR("invalid encoder\n");
410		- return -EINVAL;
411		- }
412	395	irq = &phys_enc->irq[intr_idx];
413	396
414	397	/* silently skip irqs that weren't registered */
..	..	@@ -443,30 +426,22 @@
443	426	}
444	427
445	428	void dpu_encoder_get_hw_resources(struct drm_encoder *drm_enc,
446		- struct dpu_encoder_hw_resources *hw_res,
447		- struct drm_connector_state *conn_state)
	429	+ struct dpu_encoder_hw_resources *hw_res)
448	430	{
449	431	struct dpu_encoder_virt *dpu_enc = NULL;
450	432	int i = 0;
451		-
452		- if (!hw_res \|\| !drm_enc \|\| !conn_state) {
453		- DPU_ERROR("invalid argument(s), drm_enc %d, res %d, state %d\n",
454		- drm_enc != 0, hw_res != 0, conn_state != 0);
455		- return;
456		- }
457	433
458	434	dpu_enc = to_dpu_encoder_virt(drm_enc);
459	435	DPU_DEBUG_ENC(dpu_enc, "\n");
460	436
461	437	/* Query resources used by phys encs, expected to be without overlap */
462	438	memset(hw_res, 0, sizeof(*hw_res));
463		- hw_res->display_num_of_h_tiles = dpu_enc->display_num_of_h_tiles;
464	439
465	440	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
466	441	struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
467	442
468		- if (phys && phys->ops.get_hw_resources)
469		- phys->ops.get_hw_resources(phys, hw_res, conn_state);
	443	+ if (phys->ops.get_hw_resources)
	444	+ phys->ops.get_hw_resources(phys, hw_res);
470	445	}
471	446	}
472	447
..	..	@@ -488,7 +463,7 @@
488	463	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
489	464	struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
490	465
491		- if (phys && phys->ops.destroy) {
	466	+ if (phys->ops.destroy) {
492	467	phys->ops.destroy(phys);
493	468	--dpu_enc->num_phys_encs;
494	469	dpu_enc->phys_encs[i] = NULL;
..	..	@@ -514,8 +489,8 @@
514	489	struct dpu_hw_mdp *hw_mdptop;
515	490	struct msm_display_info *disp_info;
516	491
517		- if (!phys_enc \|\| !phys_enc->hw_mdptop \|\| !phys_enc->parent) {
518		- DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != 0);
	492	+ if (!phys_enc->hw_mdptop \|\| !phys_enc->parent) {
	493	+ DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != NULL);
519	494	return;
520	495	}
521	496
..	..	@@ -523,7 +498,7 @@
523	498	hw_mdptop = phys_enc->hw_mdptop;
524	499	disp_info = &dpu_enc->disp_info;
525	500
526		- if (disp_info->intf_type != DRM_MODE_CONNECTOR_DSI)
	501	+ if (disp_info->intf_type != DRM_MODE_ENCODER_DSI)
527	502	return;
528	503
529	504	/**
..	..	@@ -554,38 +529,43 @@
554	529	}
555	530	}
556	531
557		-static void _dpu_encoder_adjust_mode(struct drm_connector *connector,
558		- struct drm_display_mode *adj_mode)
559		-{
560		- struct drm_display_mode *cur_mode;
561		-
562		- if (!connector \|\| !adj_mode)
563		- return;
564		-
565		- list_for_each_entry(cur_mode, &connector->modes, head) {
566		- if (cur_mode->vdisplay == adj_mode->vdisplay &&
567		- cur_mode->hdisplay == adj_mode->hdisplay &&
568		- cur_mode->vrefresh == adj_mode->vrefresh) {
569		- adj_mode->private = cur_mode->private;
570		- adj_mode->private_flags \|= cur_mode->private_flags;
571		- }
572		- }
573		-}
574		-
575	532	static struct msm_display_topology dpu_encoder_get_topology(
576	533	struct dpu_encoder_virt *dpu_enc,
577	534	struct dpu_kms *dpu_kms,
578	535	struct drm_display_mode *mode)
579	536	{
580		- struct msm_display_topology topology;
	537	+ struct msm_display_topology topology = {0};
581	538	int i, intf_count = 0;
582	539
583	540	for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
584	541	if (dpu_enc->phys_encs[i])
585	542	intf_count++;
586	543
587		- /* User split topology for width > 1080 */
588		- topology.num_lm = (mode->vdisplay > MAX_VDISPLAY_SPLIT) ? 2 : 1;
	544	+ /* Datapath topology selection
	545	+ *
	546	+ * Dual display
	547	+ * 2 LM, 2 INTF ( Split display using 2 interfaces)
	548	+ *
	549	+ * Single display
	550	+ * 1 LM, 1 INTF
	551	+ * 2 LM, 1 INTF (stream merge to support high resolution interfaces)
	552	+ *
	553	+ * Adding color blocks only to primary interface if available in
	554	+ * sufficient number
	555	+ */
	556	+ if (intf_count == 2)
	557	+ topology.num_lm = 2;
	558	+ else if (!dpu_kms->catalog->caps->has_3d_merge)
	559	+ topology.num_lm = 1;
	560	+ else
	561	+ topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;
	562	+
	563	+ if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI) {
	564	+ if (dpu_kms->catalog->dspp &&
	565	+ (dpu_kms->catalog->dspp_count >= topology.num_lm))
	566	+ topology.num_dspp = topology.num_lm;
	567	+ }
	568	+
589	569	topology.num_enc = 0;
590	570	topology.num_intf = intf_count;
591	571
..	..	@@ -602,12 +582,13 @@
602	582	const struct drm_display_mode *mode;
603	583	struct drm_display_mode *adj_mode;
604	584	struct msm_display_topology topology;
	585	+ struct dpu_global_state *global_state;
605	586	int i = 0;
606	587	int ret = 0;
607	588
608	589	if (!drm_enc \|\| !crtc_state \|\| !conn_state) {
609	590	DPU_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n",
610		- drm_enc != 0, crtc_state != 0, conn_state != 0);
	591	+ drm_enc != NULL, crtc_state != NULL, conn_state != NULL);
611	592	return -EINVAL;
612	593	}
613	594
..	..	@@ -618,25 +599,20 @@
618	599	dpu_kms = to_dpu_kms(priv->kms);
619	600	mode = &crtc_state->mode;
620	601	adj_mode = &crtc_state->adjusted_mode;
621		- trace_dpu_enc_atomic_check(DRMID(drm_enc));
	602	+ global_state = dpu_kms_get_global_state(crtc_state->state);
	603	+ if (IS_ERR(global_state))
	604	+ return PTR_ERR(global_state);
622	605
623		- /*
624		- * display drivers may populate private fields of the drm display mode
625		- * structure while registering possible modes of a connector with DRM.
626		- * These private fields are not populated back while DRM invokes
627		- * the mode_set callbacks. This module retrieves and populates the
628		- * private fields of the given mode.
629		- */
630		- _dpu_encoder_adjust_mode(conn_state->connector, adj_mode);
	606	+ trace_dpu_enc_atomic_check(DRMID(drm_enc));
631	607
632	608	/* perform atomic check on the first physical encoder (master) */
633	609	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
634	610	struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
635	611
636		- if (phys && phys->ops.atomic_check)
	612	+ if (phys->ops.atomic_check)
637	613	ret = phys->ops.atomic_check(phys, crtc_state,
638	614	conn_state);
639		- else if (phys && phys->ops.mode_fixup)
	615	+ else if (phys->ops.mode_fixup)
640	616	if (!phys->ops.mode_fixup(phys, mode, adj_mode))
641	617	ret = -EINVAL;
642	618
..	..	@@ -649,25 +625,22 @@
649	625
650	626	topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
651	627
652		- /* Reserve dynamic resources now. Indicating AtomicTest phase */
	628	+ /* Reserve dynamic resources now. */
653	629	if (!ret) {
654	630	/*
655		- * Avoid reserving resources when mode set is pending. Topology
656		- * info may not be available to complete reservation.
	631	+ * Release and Allocate resources on every modeset
	632	+ * Dont allocate when active is false.
657	633	*/
658		- if (drm_atomic_crtc_needs_modeset(crtc_state)
659		- && dpu_enc->mode_set_complete) {
660		- ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, crtc_state,
661		- conn_state, topology, true);
662		- dpu_enc->mode_set_complete = false;
	634	+ if (drm_atomic_crtc_needs_modeset(crtc_state)) {
	635	+ dpu_rm_release(global_state, drm_enc);
	636	+
	637	+ if (!crtc_state->active_changed \|\| crtc_state->enable)
	638	+ ret = dpu_rm_reserve(&dpu_kms->rm, global_state,
	639	+ drm_enc, crtc_state, topology);
663	640	}
664	641	}
665	642
666		- if (!ret)
667		- drm_mode_set_crtcinfo(adj_mode, 0);
668		-
669		- trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags,
670		- adj_mode->private_flags);
	643	+ trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags);
671	644
672	645	return ret;
673	646	}
..	..	@@ -698,11 +671,6 @@
698	671	priv = drm_enc->dev->dev_private;
699	672
700	673	dpu_kms = to_dpu_kms(priv->kms);
701		- if (!dpu_kms) {
702		- DPU_ERROR("invalid dpu_kms\n");
703		- return;
704		- }
705		-
706	674	hw_mdptop = dpu_kms->hw_mdp;
707	675	if (!hw_mdptop) {
708	676	DPU_ERROR("invalid mdptop\n");
..	..	@@ -740,7 +708,7 @@
740	708	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
741	709	struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
742	710
743		- if (phys && phys->ops.irq_control)
	711	+ if (phys->ops.irq_control)
744	712	phys->ops.irq_control(phys, enable);
745	713	}
746	714
..	..	@@ -786,11 +754,9 @@
786	754	{
787	755	struct dpu_encoder_virt *dpu_enc;
788	756	struct msm_drm_private *priv;
789		- struct msm_drm_thread *disp_thread;
790	757	bool is_vid_mode = false;
791	758
792		- if (!drm_enc \|\| !drm_enc->dev \|\| !drm_enc->dev->dev_private \|\|
793		- !drm_enc->crtc) {
	759	+ if (!drm_enc \|\| !drm_enc->dev \|\| !drm_enc->crtc) {
794	760	DPU_ERROR("invalid parameters\n");
795	761	return -EINVAL;
796	762	}
..	..	@@ -798,12 +764,6 @@
798	764	priv = drm_enc->dev->dev_private;
799	765	is_vid_mode = dpu_enc->disp_info.capabilities &
800	766	MSM_DISPLAY_CAP_VID_MODE;
801		-
802		- if (drm_enc->crtc->index >= ARRAY_SIZE(priv->disp_thread)) {
803		- DPU_ERROR("invalid crtc index\n");
804		- return -EINVAL;
805		- }
806		- disp_thread = &priv->disp_thread[drm_enc->crtc->index];
807	767
808	768	/*
809	769	* when idle_pc is not supported, process only KICKOFF, STOP and MODESET
..	..	@@ -821,8 +781,7 @@
821	781	switch (sw_event) {
822	782	case DPU_ENC_RC_EVENT_KICKOFF:
823	783	/* cancel delayed off work, if any */
824		- if (kthread_cancel_delayed_work_sync(
825		- &dpu_enc->delayed_off_work))
	784	+ if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work))
826	785	DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n",
827	786	sw_event);
828	787
..	..	@@ -881,10 +840,8 @@
881	840	return 0;
882	841	}
883	842
884		- kthread_queue_delayed_work(
885		- &disp_thread->worker,
886		- &dpu_enc->delayed_off_work,
887		- msecs_to_jiffies(dpu_enc->idle_timeout));
	843	+ queue_delayed_work(priv->wq, &dpu_enc->delayed_off_work,
	844	+ msecs_to_jiffies(dpu_enc->idle_timeout));
888	845
889	846	trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
890	847	dpu_enc->idle_pc_supported, dpu_enc->rc_state,
..	..	@@ -893,8 +850,7 @@
893	850
894	851	case DPU_ENC_RC_EVENT_PRE_STOP:
895	852	/* cancel delayed off work, if any */
896		- if (kthread_cancel_delayed_work_sync(
897		- &dpu_enc->delayed_off_work))
	853	+ if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work))
898	854	DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n",
899	855	sw_event);
900	856
..	..	@@ -1014,10 +970,16 @@
1014	970	struct dpu_kms *dpu_kms;
1015	971	struct list_head *connector_list;
1016	972	struct drm_connector conn = NULL, conn_iter;
1017		- struct dpu_rm_hw_iter pp_iter;
	973	+ struct drm_crtc *drm_crtc;
	974	+ struct dpu_crtc_state *cstate;
	975	+ struct dpu_global_state *global_state;
1018	976	struct msm_display_topology topology;
1019		- enum dpu_rm_topology_name topology_name;
1020		- int i = 0, ret;
	977	+ struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC];
	978	+ struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];
	979	+ struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];
	980	+ struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL };
	981	+ int num_lm, num_ctl, num_pp, num_dspp;
	982	+ int i, j;
1021	983
1022	984	if (!drm_enc) {
1023	985	DPU_ERROR("invalid encoder\n");
..	..	@@ -1031,7 +993,16 @@
1031	993	dpu_kms = to_dpu_kms(priv->kms);
1032	994	connector_list = &dpu_kms->dev->mode_config.connector_list;
1033	995
	996	+ global_state = dpu_kms_get_existing_global_state(dpu_kms);
	997	+ if (IS_ERR_OR_NULL(global_state)) {
	998	+ DPU_ERROR("Failed to get global state");
	999	+ return;
	1000	+ }
	1001	+
1034	1002	trace_dpu_enc_mode_set(DRMID(drm_enc));
	1003	+
	1004	+ if (drm_enc->encoder_type == DRM_MODE_ENCODER_TMDS && priv->dp)
	1005	+ msm_dp_display_mode_set(priv->dp, drm_enc, mode, adj_mode);
1035	1006
1036	1007	list_for_each_entry(conn_iter, connector_list, head)
1037	1008	if (conn_iter->encoder == drm_enc)
..	..	@@ -1045,63 +1016,95 @@
1045	1016	return;
1046	1017	}
1047	1018
	1019	+ drm_for_each_crtc(drm_crtc, drm_enc->dev)
	1020	+ if (drm_crtc->state->encoder_mask & drm_encoder_mask(drm_enc))
	1021	+ break;
	1022	+
1048	1023	topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
1049	1024
1050		- /* Reserve dynamic resources now. Indicating non-AtomicTest phase */
1051		- ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, drm_enc->crtc->state,
1052		- conn->state, topology, false);
1053		- if (ret) {
1054		- DPU_ERROR_ENC(dpu_enc,
1055		- "failed to reserve hw resources, %d\n", ret);
1056		- return;
	1025	+ /* Query resource that have been reserved in atomic check step. */
	1026	+ num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
	1027	+ drm_enc->base.id, DPU_HW_BLK_PINGPONG, hw_pp,
	1028	+ ARRAY_SIZE(hw_pp));
	1029	+ num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
	1030	+ drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl));
	1031	+ num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
	1032	+ drm_enc->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm));
	1033	+ num_dspp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
	1034	+ drm_enc->base.id, DPU_HW_BLK_DSPP, hw_dspp,
	1035	+ ARRAY_SIZE(hw_dspp));
	1036	+
	1037	+ for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
	1038	+ dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i])
	1039	+ : NULL;
	1040	+
	1041	+ cstate = to_dpu_crtc_state(drm_crtc->state);
	1042	+
	1043	+ for (i = 0; i < num_lm; i++) {
	1044	+ int ctl_idx = (i < num_ctl) ? i : (num_ctl-1);
	1045	+
	1046	+ cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]);
	1047	+ cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]);
	1048	+ cstate->mixers[i].hw_dspp = to_dpu_hw_dspp(hw_dspp[i]);
1057	1049	}
1058	1050
1059		- dpu_rm_init_hw_iter(&pp_iter, drm_enc->base.id, DPU_HW_BLK_PINGPONG);
1060		- for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
1061		- dpu_enc->hw_pp[i] = NULL;
1062		- if (!dpu_rm_get_hw(&dpu_kms->rm, &pp_iter))
1063		- break;
1064		- dpu_enc->hw_pp[i] = (struct dpu_hw_pingpong *) pp_iter.hw;
1065		- }
	1051	+ cstate->num_mixers = num_lm;
1066	1052
1067		- topology_name = dpu_rm_get_topology_name(topology);
1068	1053	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
	1054	+ int num_blk;
	1055	+ struct dpu_hw_blk *hw_blk[MAX_CHANNELS_PER_ENC];
1069	1056	struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1070	1057
1071		- if (phys) {
1072		- if (!dpu_enc->hw_pp[i]) {
1073		- DPU_ERROR_ENC(dpu_enc,
1074		- "invalid pingpong block for the encoder\n");
1075		- return;
1076		- }
1077		- phys->hw_pp = dpu_enc->hw_pp[i];
1078		- phys->connector = conn->state->connector;
1079		- phys->topology_name = topology_name;
1080		- if (phys->ops.mode_set)
1081		- phys->ops.mode_set(phys, mode, adj_mode);
	1058	+ if (!dpu_enc->hw_pp[i]) {
	1059	+ DPU_ERROR_ENC(dpu_enc,
	1060	+ "no pp block assigned at idx: %d\n", i);
	1061	+ return;
1082	1062	}
1083		- }
1084	1063
1085		- dpu_enc->mode_set_complete = true;
	1064	+ if (!hw_ctl[i]) {
	1065	+ DPU_ERROR_ENC(dpu_enc,
	1066	+ "no ctl block assigned at idx: %d\n", i);
	1067	+ return;
	1068	+ }
	1069	+
	1070	+ phys->hw_pp = dpu_enc->hw_pp[i];
	1071	+ phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]);
	1072	+
	1073	+ num_blk = dpu_rm_get_assigned_resources(&dpu_kms->rm,
	1074	+ global_state, drm_enc->base.id, DPU_HW_BLK_INTF,
	1075	+ hw_blk, ARRAY_SIZE(hw_blk));
	1076	+ for (j = 0; j < num_blk; j++) {
	1077	+ struct dpu_hw_intf *hw_intf;
	1078	+
	1079	+ hw_intf = to_dpu_hw_intf(hw_blk[i]);
	1080	+ if (hw_intf->idx == phys->intf_idx)
	1081	+ phys->hw_intf = hw_intf;
	1082	+ }
	1083	+
	1084	+ if (!phys->hw_intf) {
	1085	+ DPU_ERROR_ENC(dpu_enc,
	1086	+ "no intf block assigned at idx: %d\n", i);
	1087	+ return;
	1088	+ }
	1089	+
	1090	+ phys->connector = conn->state->connector;
	1091	+ if (phys->ops.mode_set)
	1092	+ phys->ops.mode_set(phys, mode, adj_mode);
	1093	+ }
1086	1094	}
1087	1095
1088	1096	static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
1089	1097	{
1090	1098	struct dpu_encoder_virt *dpu_enc = NULL;
1091	1099	struct msm_drm_private *priv;
1092		- struct dpu_kms *dpu_kms;
	1100	+ int i;
1093	1101
1094		- if (!drm_enc \|\| !drm_enc->dev \|\| !drm_enc->dev->dev_private) {
	1102	+ if (!drm_enc \|\| !drm_enc->dev) {
1095	1103	DPU_ERROR("invalid parameters\n");
1096	1104	return;
1097	1105	}
1098	1106
1099	1107	priv = drm_enc->dev->dev_private;
1100		- dpu_kms = to_dpu_kms(priv->kms);
1101		- if (!dpu_kms) {
1102		- DPU_ERROR("invalid dpu_kms\n");
1103		- return;
1104		- }
1105	1108
1106	1109	dpu_enc = to_dpu_encoder_virt(drm_enc);
1107	1110	if (!dpu_enc \|\| !dpu_enc->cur_master) {
..	..	@@ -1109,49 +1112,51 @@
1109	1112	return;
1110	1113	}
1111	1114
1112		- if (dpu_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DisplayPort &&
1113		- dpu_enc->cur_master->hw_mdptop &&
1114		- dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select)
1115		- dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select(
1116		- dpu_enc->cur_master->hw_mdptop);
1117	1115
1118		- if (dpu_enc->cur_master->hw_mdptop &&
1119		- dpu_enc->cur_master->hw_mdptop->ops.reset_ubwc)
1120		- dpu_enc->cur_master->hw_mdptop->ops.reset_ubwc(
1121		- dpu_enc->cur_master->hw_mdptop,
1122		- dpu_kms->catalog);
	1116	+ if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_TMDS &&
	1117	+ dpu_enc->cur_master->hw_mdptop &&
	1118	+ dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select)
	1119	+ dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select(
	1120	+ dpu_enc->cur_master->hw_mdptop);
1123	1121
1124	1122	_dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info);
	1123	+
	1124	+ if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI &&
	1125	+ !WARN_ON(dpu_enc->num_phys_encs == 0)) {
	1126	+ unsigned bpc = dpu_enc->phys_encs[0]->connector->display_info.bpc;
	1127	+ for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
	1128	+ if (!dpu_enc->hw_pp[i])
	1129	+ continue;
	1130	+ _dpu_encoder_setup_dither(dpu_enc->hw_pp[i], bpc);
	1131	+ }
	1132	+ }
1125	1133	}
1126	1134
1127		-void dpu_encoder_virt_restore(struct drm_encoder *drm_enc)
	1135	+void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc)
1128	1136	{
1129		- struct dpu_encoder_virt *dpu_enc = NULL;
1130		- int i;
	1137	+ struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1131	1138
1132		- if (!drm_enc) {
1133		- DPU_ERROR("invalid encoder\n");
1134		- return;
1135		- }
1136		- dpu_enc = to_dpu_encoder_virt(drm_enc);
	1139	+ mutex_lock(&dpu_enc->enc_lock);
1137	1140
1138		- for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1139		- struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
	1141	+ if (!dpu_enc->enabled)
	1142	+ goto out;
1140	1143
1141		- if (phys && (phys != dpu_enc->cur_master) && phys->ops.restore)
1142		- phys->ops.restore(phys);
1143		- }
1144		-
	1144	+ if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.restore)
	1145	+ dpu_enc->cur_slave->ops.restore(dpu_enc->cur_slave);
1145	1146	if (dpu_enc->cur_master && dpu_enc->cur_master->ops.restore)
1146	1147	dpu_enc->cur_master->ops.restore(dpu_enc->cur_master);
1147	1148
1148	1149	_dpu_encoder_virt_enable_helper(drm_enc);
	1150	+
	1151	+out:
	1152	+ mutex_unlock(&dpu_enc->enc_lock);
1149	1153	}
1150	1154
1151	1155	static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
1152	1156	{
1153	1157	struct dpu_encoder_virt *dpu_enc = NULL;
1154		- int i, ret = 0;
	1158	+ int ret = 0;
	1159	+ struct msm_drm_private *priv;
1155	1160	struct drm_display_mode *cur_mode = NULL;
1156	1161
1157	1162	if (!drm_enc) {
..	..	@@ -1159,55 +1164,43 @@
1159	1164	return;
1160	1165	}
1161	1166	dpu_enc = to_dpu_encoder_virt(drm_enc);
	1167	+
	1168	+ mutex_lock(&dpu_enc->enc_lock);
1162	1169	cur_mode = &dpu_enc->base.crtc->state->adjusted_mode;
	1170	+ priv = drm_enc->dev->dev_private;
1163	1171
1164	1172	trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay,
1165	1173	cur_mode->vdisplay);
1166	1174
1167		- dpu_enc->cur_master = NULL;
1168		- for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1169		- struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
	1175	+ /* always enable slave encoder before master */
	1176	+ if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.enable)
	1177	+ dpu_enc->cur_slave->ops.enable(dpu_enc->cur_slave);
1170	1178
1171		- if (phys && phys->ops.is_master && phys->ops.is_master(phys)) {
1172		- DPU_DEBUG_ENC(dpu_enc, "master is now idx %d\n", i);
1173		- dpu_enc->cur_master = phys;
1174		- break;
1175		- }
1176		- }
1177		-
1178		- if (!dpu_enc->cur_master) {
1179		- DPU_ERROR("virt encoder has no master! num_phys %d\n", i);
1180		- return;
1181		- }
	1179	+ if (dpu_enc->cur_master && dpu_enc->cur_master->ops.enable)
	1180	+ dpu_enc->cur_master->ops.enable(dpu_enc->cur_master);
1182	1181
1183	1182	ret = dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF);
1184	1183	if (ret) {
1185	1184	DPU_ERROR_ENC(dpu_enc, "dpu resource control failed: %d\n",
1186	1185	ret);
1187		- return;
	1186	+ goto out;
1188	1187	}
1189		-
1190		- for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1191		- struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1192		-
1193		- if (!phys)
1194		- continue;
1195		-
1196		- if (phys != dpu_enc->cur_master) {
1197		- if (phys->ops.enable)
1198		- phys->ops.enable(phys);
1199		- }
1200		-
1201		- if (dpu_enc->misr_enable && (dpu_enc->disp_info.capabilities &
1202		- MSM_DISPLAY_CAP_VID_MODE) && phys->ops.setup_misr)
1203		- phys->ops.setup_misr(phys, true,
1204		- dpu_enc->misr_frame_count);
1205		- }
1206		-
1207		- if (dpu_enc->cur_master->ops.enable)
1208		- dpu_enc->cur_master->ops.enable(dpu_enc->cur_master);
1209	1188
1210	1189	_dpu_encoder_virt_enable_helper(drm_enc);
	1190	+
	1191	+ if (drm_enc->encoder_type == DRM_MODE_ENCODER_TMDS && priv->dp) {
	1192	+ ret = msm_dp_display_enable(priv->dp,
	1193	+ drm_enc);
	1194	+ if (ret) {
	1195	+ DPU_ERROR_ENC(dpu_enc, "dp display enable failed: %d\n",
	1196	+ ret);
	1197	+ goto out;
	1198	+ }
	1199	+ }
	1200	+ dpu_enc->enabled = true;
	1201	+
	1202	+out:
	1203	+ mutex_unlock(&dpu_enc->enc_lock);
1211	1204	}
1212	1205
1213	1206	static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc)
..	..	@@ -1215,7 +1208,6 @@
1215	1208	struct dpu_encoder_virt *dpu_enc = NULL;
1216	1209	struct msm_drm_private *priv;
1217	1210	struct dpu_kms *dpu_kms;
1218		- struct drm_display_mode *mode;
1219	1211	int i = 0;
1220	1212
1221	1213	if (!drm_enc) {
..	..	@@ -1224,15 +1216,13 @@
1224	1216	} else if (!drm_enc->dev) {
1225	1217	DPU_ERROR("invalid dev\n");
1226	1218	return;
1227		- } else if (!drm_enc->dev->dev_private) {
1228		- DPU_ERROR("invalid dev_private\n");
1229		- return;
1230	1219	}
1231		-
1232		- mode = &drm_enc->crtc->state->adjusted_mode;
1233	1220
1234	1221	dpu_enc = to_dpu_encoder_virt(drm_enc);
1235	1222	DPU_DEBUG_ENC(dpu_enc, "\n");
	1223	+
	1224	+ mutex_lock(&dpu_enc->enc_lock);
	1225	+ dpu_enc->enabled = false;
1236	1226
1237	1227	priv = drm_enc->dev->dev_private;
1238	1228	dpu_kms = to_dpu_kms(priv->kms);
..	..	@@ -1242,17 +1232,23 @@
1242	1232	/* wait for idle */
1243	1233	dpu_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);
1244	1234
	1235	+ if (drm_enc->encoder_type == DRM_MODE_ENCODER_TMDS && priv->dp) {
	1236	+ if (msm_dp_display_pre_disable(priv->dp, drm_enc))
	1237	+ DPU_ERROR_ENC(dpu_enc, "dp display push idle failed\n");
	1238	+ }
	1239	+
1245	1240	dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP);
1246	1241
1247	1242	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1248	1243	struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1249	1244
1250		- if (phys && phys->ops.disable)
	1245	+ if (phys->ops.disable)
1251	1246	phys->ops.disable(phys);
1252	1247	}
1253	1248
	1249	+
1254	1250	/* after phys waits for frame-done, should be no more frames pending */
1255		- if (atomic_xchg(&dpu_enc->frame_done_timeout, 0)) {
	1251	+ if (atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {
1256	1252	DPU_ERROR("enc%d timeout pending\n", drm_enc->base.id);
1257	1253	del_timer_sync(&dpu_enc->frame_done_timer);
1258	1254	}
..	..	@@ -1260,15 +1256,17 @@
1260	1256	dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_STOP);
1261	1257
1262	1258	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1263		- if (dpu_enc->phys_encs[i])
1264		- dpu_enc->phys_encs[i]->connector = NULL;
	1259	+ dpu_enc->phys_encs[i]->connector = NULL;
1265	1260	}
1266		-
1267		- dpu_enc->cur_master = NULL;
1268	1261
1269	1262	DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n");
1270	1263
1271		- dpu_rm_release(&dpu_kms->rm, drm_enc);
	1264	+ if (drm_enc->encoder_type == DRM_MODE_ENCODER_TMDS && priv->dp) {
	1265	+ if (msm_dp_display_disable(priv->dp, drm_enc))
	1266	+ DPU_ERROR_ENC(dpu_enc, "dp display disable failed\n");
	1267	+ }
	1268	+
	1269	+ mutex_unlock(&dpu_enc->enc_lock);
1272	1270	}
1273	1271
1274	1272	static enum dpu_intf dpu_encoder_get_intf(struct dpu_mdss_cfg *catalog,
..	..	@@ -1299,8 +1297,8 @@
1299	1297	dpu_enc = to_dpu_encoder_virt(drm_enc);
1300	1298
1301	1299	spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1302		- if (dpu_enc->crtc_vblank_cb)
1303		- dpu_enc->crtc_vblank_cb(dpu_enc->crtc_vblank_cb_data);
	1300	+ if (dpu_enc->crtc)
	1301	+ dpu_crtc_vblank_callback(dpu_enc->crtc);
1304	1302	spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1305	1303
1306	1304	atomic_inc(&phy_enc->vsync_cnt);
..	..	@@ -1320,31 +1318,38 @@
1320	1318	DPU_ATRACE_END("encoder_underrun_callback");
1321	1319	}
1322	1320
1323		-void dpu_encoder_register_vblank_callback(struct drm_encoder *drm_enc,
1324		- void (vbl_cb)(void ), void *vbl_data)
	1321	+void dpu_encoder_assign_crtc(struct drm_encoder drm_enc, struct drm_crtc crtc)
1325	1322	{
1326	1323	struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1327	1324	unsigned long lock_flags;
1328		- bool enable;
	1325	+
	1326	+ spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
	1327	+ /* crtc should always be cleared before re-assigning */
	1328	+ WARN_ON(crtc && dpu_enc->crtc);
	1329	+ dpu_enc->crtc = crtc;
	1330	+ spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
	1331	+}
	1332	+
	1333	+void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *drm_enc,
	1334	+ struct drm_crtc *crtc, bool enable)
	1335	+{
	1336	+ struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
	1337	+ unsigned long lock_flags;
1329	1338	int i;
1330	1339
1331		- enable = vbl_cb ? true : false;
1332		-
1333		- if (!drm_enc) {
1334		- DPU_ERROR("invalid encoder\n");
1335		- return;
1336		- }
1337	1340	trace_dpu_enc_vblank_cb(DRMID(drm_enc), enable);
1338	1341
1339	1342	spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1340		- dpu_enc->crtc_vblank_cb = vbl_cb;
1341		- dpu_enc->crtc_vblank_cb_data = vbl_data;
	1343	+ if (dpu_enc->crtc != crtc) {
	1344	+ spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
	1345	+ return;
	1346	+ }
1342	1347	spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1343	1348
1344	1349	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1345	1350	struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1346	1351
1347		- if (phys && phys->ops.control_vblank_irq)
	1352	+ if (phys->ops.control_vblank_irq)
1348	1353	phys->ops.control_vblank_irq(phys, enable);
1349	1354	}
1350	1355	}
..	..	@@ -1395,14 +1400,14 @@
1395	1400	/* One of the physical encoders has become idle */
1396	1401	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1397	1402	if (dpu_enc->phys_encs[i] == ready_phys) {
1398		- clear_bit(i, dpu_enc->frame_busy_mask);
1399	1403	trace_dpu_enc_frame_done_cb(DRMID(drm_enc), i,
1400	1404	dpu_enc->frame_busy_mask[0]);
	1405	+ clear_bit(i, dpu_enc->frame_busy_mask);
1401	1406	}
1402	1407	}
1403	1408
1404	1409	if (!dpu_enc->frame_busy_mask[0]) {
1405		- atomic_set(&dpu_enc->frame_done_timeout, 0);
	1410	+ atomic_set(&dpu_enc->frame_done_timeout_ms, 0);
1406	1411	del_timer(&dpu_enc->frame_done_timer);
1407	1412
1408	1413	dpu_encoder_resource_control(drm_enc,
..	..	@@ -1420,7 +1425,7 @@
1420	1425	}
1421	1426	}
1422	1427
1423		-static void dpu_encoder_off_work(struct kthread_work *work)
	1428	+static void dpu_encoder_off_work(struct work_struct *work)
1424	1429	{
1425	1430	struct dpu_encoder_virt *dpu_enc = container_of(work,
1426	1431	struct dpu_encoder_virt, delayed_off_work.work);
..	..	@@ -1443,18 +1448,12 @@
1443	1448	* phys: Pointer to physical encoder structure
1444	1449	* extra_flush_bits: Additional bit mask to include in flush trigger
1445	1450	*/
1446		-static inline void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc,
	1451	+static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc,
1447	1452	struct dpu_encoder_phys *phys, uint32_t extra_flush_bits)
1448	1453	{
1449	1454	struct dpu_hw_ctl *ctl;
1450	1455	int pending_kickoff_cnt;
1451	1456	u32 ret = UINT_MAX;
1452		-
1453		- if (!drm_enc \|\| !phys) {
1454		- DPU_ERROR("invalid argument(s), drm_enc %d, phys_enc %d\n",
1455		- drm_enc != 0, phys != 0);
1456		- return;
1457		- }
1458	1457
1459	1458	if (!phys->hw_pp) {
1460	1459	DPU_ERROR("invalid pingpong hw\n");
..	..	@@ -1462,7 +1461,7 @@
1462	1461	}
1463	1462
1464	1463	ctl = phys->hw_ctl;
1465		- if (!ctl \|\| !ctl->ops.trigger_flush) {
	1464	+ if (!ctl->ops.trigger_flush) {
1466	1465	DPU_ERROR("missing trigger cb\n");
1467	1466	return;
1468	1467	}
..	..	@@ -1478,14 +1477,15 @@
1478	1477	ret = ctl->ops.get_pending_flush(ctl);
1479	1478
1480	1479	trace_dpu_enc_trigger_flush(DRMID(drm_enc), phys->intf_idx,
1481		- pending_kickoff_cnt, ctl->idx, ret);
	1480	+ pending_kickoff_cnt, ctl->idx,
	1481	+ extra_flush_bits, ret);
1482	1482	}
1483	1483
1484	1484	/**
1485	1485	* _dpu_encoder_trigger_start - trigger start for a physical encoder
1486	1486	* phys: Pointer to physical encoder structure
1487	1487	*/
1488		-static inline void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys)
	1488	+static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys)
1489	1489	{
1490	1490	if (!phys) {
1491	1491	DPU_ERROR("invalid argument(s)\n");
..	..	@@ -1505,13 +1505,8 @@
1505	1505	{
1506	1506	struct dpu_hw_ctl *ctl;
1507	1507
1508		- if (!phys_enc) {
1509		- DPU_ERROR("invalid encoder\n");
1510		- return;
1511		- }
1512		-
1513	1508	ctl = phys_enc->hw_ctl;
1514		- if (ctl && ctl->ops.trigger_start) {
	1509	+ if (ctl->ops.trigger_start) {
1515	1510	ctl->ops.trigger_start(ctl);
1516	1511	trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx);
1517	1512	}
..	..	@@ -1542,30 +1537,24 @@
1542	1537	return rc;
1543	1538	}
1544	1539
1545		-void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc)
	1540	+static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc)
1546	1541	{
1547	1542	struct dpu_encoder_virt *dpu_enc;
1548	1543	struct dpu_hw_ctl *ctl;
1549	1544	int rc;
1550	1545
1551		- if (!phys_enc) {
1552		- DPU_ERROR("invalid encoder\n");
1553		- return;
1554		- }
1555	1546	dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
1556	1547	ctl = phys_enc->hw_ctl;
1557	1548
1558		- if (!ctl \|\| !ctl->ops.reset)
	1549	+ if (!ctl->ops.reset)
1559	1550	return;
1560	1551
1561	1552	DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(phys_enc->parent),
1562	1553	ctl->idx);
1563	1554
1564	1555	rc = ctl->ops.reset(ctl);
1565		- if (rc) {
	1556	+ if (rc)
1566	1557	DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx);
1567		- dpu_dbg_dump(false, __func__, true, true);
1568		- }
1569	1558
1570	1559	phys_enc->enable_state = DPU_ENC_ENABLED;
1571	1560	}
..	..	@@ -1585,11 +1574,6 @@
1585	1574	uint32_t i, pending_flush;
1586	1575	unsigned long lock_flags;
1587	1576
1588		- if (!dpu_enc) {
1589		- DPU_ERROR("invalid encoder\n");
1590		- return;
1591		- }
1592		-
1593	1577	pending_flush = 0x0;
1594	1578
1595	1579	/* update pending counts and trigger kickoff ctl flush atomically */
..	..	@@ -1599,15 +1583,19 @@
1599	1583	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1600	1584	struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1601	1585
1602		- if (!phys \|\| phys->enable_state == DPU_ENC_DISABLED)
	1586	+ if (phys->enable_state == DPU_ENC_DISABLED)
1603	1587	continue;
1604	1588
1605	1589	ctl = phys->hw_ctl;
1606		- if (!ctl)
1607		- continue;
1608	1590
	1591	+ /*
	1592	+ * This is cleared in frame_done worker, which isn't invoked
	1593	+ * for async commits. So don't set this for async, since it'll
	1594	+ * roll over to the next commit.
	1595	+ */
1609	1596	if (phys->split_role != ENC_ROLE_SLAVE)
1610	1597	set_bit(i, dpu_enc->frame_busy_mask);
	1598	+
1611	1599	if (!phys->ops.needs_single_flush \|\|
1612	1600	!phys->ops.needs_single_flush(phys))
1613	1601	_dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0);
..	..	@@ -1646,17 +1634,15 @@
1646	1634	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1647	1635	phys = dpu_enc->phys_encs[i];
1648	1636
1649		- if (phys && phys->hw_ctl) {
1650		- ctl = phys->hw_ctl;
1651		- if (ctl->ops.clear_pending_flush)
1652		- ctl->ops.clear_pending_flush(ctl);
	1637	+ ctl = phys->hw_ctl;
	1638	+ if (ctl->ops.clear_pending_flush)
	1639	+ ctl->ops.clear_pending_flush(ctl);
1653	1640
1654		- /* update only for command mode primary ctl */
1655		- if ((phys == dpu_enc->cur_master) &&
1656		- (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE)
1657		- && ctl->ops.trigger_pending)
1658		- ctl->ops.trigger_pending(ctl);
1659		- }
	1641	+ /* update only for command mode primary ctl */
	1642	+ if ((phys == dpu_enc->cur_master) &&
	1643	+ (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE)
	1644	+ && ctl->ops.trigger_pending)
	1645	+ ctl->ops.trigger_pending(ctl);
1660	1646	}
1661	1647	}
1662	1648
..	..	@@ -1707,8 +1693,7 @@
1707	1693	return line_time;
1708	1694	}
1709	1695
1710		-static int _dpu_encoder_wakeup_time(struct drm_encoder *drm_enc,
1711		- ktime_t *wakeup_time)
	1696	+int dpu_encoder_vsync_time(struct drm_encoder drm_enc, ktime_t wakeup_time)
1712	1697	{
1713	1698	struct drm_display_mode *mode;
1714	1699	struct dpu_encoder_virt *dpu_enc;
..	..	@@ -1762,8 +1747,7 @@
1762	1747	struct msm_drm_private *priv;
1763	1748	struct msm_drm_thread *event_thread;
1764	1749
1765		- if (!drm_enc->dev \|\| !drm_enc->dev->dev_private \|\|
1766		- !drm_enc->crtc) {
	1750	+ if (!drm_enc->dev \|\| !drm_enc->crtc) {
1767	1751	DPU_ERROR("invalid parameters\n");
1768	1752	return;
1769	1753	}
..	..	@@ -1795,7 +1779,7 @@
1795	1779	return;
1796	1780	}
1797	1781
1798		- if (_dpu_encoder_wakeup_time(&dpu_enc->base, &wakeup_time))
	1782	+ if (dpu_encoder_vsync_time(&dpu_enc->base, &wakeup_time))
1799	1783	return;
1800	1784
1801	1785	trace_dpu_enc_vsync_event_work(DRMID(&dpu_enc->base), wakeup_time);
..	..	@@ -1803,18 +1787,13 @@
1803	1787	nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
1804	1788	}
1805	1789
1806		-void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc,
1807		- struct dpu_encoder_kickoff_params *params)
	1790	+void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
1808	1791	{
1809	1792	struct dpu_encoder_virt *dpu_enc;
1810	1793	struct dpu_encoder_phys *phys;
1811	1794	bool needs_hw_reset = false;
1812	1795	unsigned int i;
1813	1796
1814		- if (!drm_enc \|\| !params) {
1815		- DPU_ERROR("invalid args\n");
1816		- return;
1817		- }
1818	1797	dpu_enc = to_dpu_encoder_virt(drm_enc);
1819	1798
1820	1799	trace_dpu_enc_prepare_kickoff(DRMID(drm_enc));
..	..	@@ -1823,12 +1802,10 @@
1823	1802	DPU_ATRACE_BEGIN("enc_prepare_for_kickoff");
1824	1803	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1825	1804	phys = dpu_enc->phys_encs[i];
1826		- if (phys) {
1827		- if (phys->ops.prepare_for_kickoff)
1828		- phys->ops.prepare_for_kickoff(phys, params);
1829		- if (phys->enable_state == DPU_ENC_ERR_NEEDS_HW_RESET)
1830		- needs_hw_reset = true;
1831		- }
	1805	+ if (phys->ops.prepare_for_kickoff)
	1806	+ phys->ops.prepare_for_kickoff(phys);
	1807	+ if (phys->enable_state == DPU_ENC_ERR_NEEDS_HW_RESET)
	1808	+ needs_hw_reset = true;
1832	1809	}
1833	1810	DPU_ATRACE_END("enc_prepare_for_kickoff");
1834	1811
..	..	@@ -1838,9 +1815,7 @@
1838	1815	if (needs_hw_reset) {
1839	1816	trace_dpu_enc_prepare_kickoff_reset(DRMID(drm_enc));
1840	1817	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1841		- phys = dpu_enc->phys_encs[i];
1842		- if (phys && phys->ops.hw_reset)
1843		- phys->ops.hw_reset(phys);
	1818	+ dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]);
1844	1819	}
1845	1820	}
1846	1821	}
..	..	@@ -1850,22 +1825,20 @@
1850	1825	struct dpu_encoder_virt *dpu_enc;
1851	1826	struct dpu_encoder_phys *phys;
1852	1827	ktime_t wakeup_time;
	1828	+ unsigned long timeout_ms;
1853	1829	unsigned int i;
1854	1830
1855		- if (!drm_enc) {
1856		- DPU_ERROR("invalid encoder\n");
1857		- return;
1858		- }
1859	1831	DPU_ATRACE_BEGIN("encoder_kickoff");
1860	1832	dpu_enc = to_dpu_encoder_virt(drm_enc);
1861	1833
1862	1834	trace_dpu_enc_kickoff(DRMID(drm_enc));
1863	1835
1864		- atomic_set(&dpu_enc->frame_done_timeout,
1865		- DPU_FRAME_DONE_TIMEOUT * 1000 /
1866		- drm_enc->crtc->state->adjusted_mode.vrefresh);
1867		- mod_timer(&dpu_enc->frame_done_timer, jiffies +
1868		- ((atomic_read(&dpu_enc->frame_done_timeout) * HZ) / 1000));
	1836	+ timeout_ms = DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES * 1000 /
	1837	+ drm_mode_vrefresh(&drm_enc->crtc->state->adjusted_mode);
	1838	+
	1839	+ atomic_set(&dpu_enc->frame_done_timeout_ms, timeout_ms);
	1840	+ mod_timer(&dpu_enc->frame_done_timer,
	1841	+ jiffies + msecs_to_jiffies(timeout_ms));
1869	1842
1870	1843	/* All phys encs are ready to go, trigger the kickoff */
1871	1844	_dpu_encoder_kickoff_phys(dpu_enc);
..	..	@@ -1873,12 +1846,12 @@
1873	1846	/* allow phys encs to handle any post-kickoff business */
1874	1847	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1875	1848	phys = dpu_enc->phys_encs[i];
1876		- if (phys && phys->ops.handle_post_kickoff)
	1849	+ if (phys->ops.handle_post_kickoff)
1877	1850	phys->ops.handle_post_kickoff(phys);
1878	1851	}
1879	1852
1880		- if (dpu_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DSI &&
1881		- !_dpu_encoder_wakeup_time(drm_enc, &wakeup_time)) {
	1853	+ if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI &&
	1854	+ !dpu_encoder_vsync_time(drm_enc, &wakeup_time)) {
1882	1855	trace_dpu_enc_early_kickoff(DRMID(drm_enc),
1883	1856	ktime_to_ms(wakeup_time));
1884	1857	mod_timer(&dpu_enc->vsync_event_timer,
..	..	@@ -1902,7 +1875,7 @@
1902	1875
1903	1876	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1904	1877	phys = dpu_enc->phys_encs[i];
1905		- if (phys && phys->ops.prepare_commit)
	1878	+ if (phys->ops.prepare_commit)
1906	1879	phys->ops.prepare_commit(phys);
1907	1880	}
1908	1881	}
..	..	@@ -1910,20 +1883,12 @@
1910	1883	#ifdef CONFIG_DEBUG_FS
1911	1884	static int _dpu_encoder_status_show(struct seq_file s, void data)
1912	1885	{
1913		- struct dpu_encoder_virt *dpu_enc;
	1886	+ struct dpu_encoder_virt *dpu_enc = s->private;
1914	1887	int i;
1915		-
1916		- if (!s \|\| !s->private)
1917		- return -EINVAL;
1918		-
1919		- dpu_enc = s->private;
1920	1888
1921	1889	mutex_lock(&dpu_enc->enc_lock);
1922	1890	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1923	1891	struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1924		-
1925		- if (!phys)
1926		- continue;
1927	1892
1928	1893	seq_printf(s, "intf:%d vsync:%8d underrun:%8d ",
1929	1894	phys->intf_idx - INTF_0,
..	..	@@ -1947,193 +1912,42 @@
1947	1912	return 0;
1948	1913	}
1949	1914
1950		-static int _dpu_encoder_debugfs_status_open(struct inode *inode,
1951		- struct file *file)
1952		-{
1953		- return single_open(file, _dpu_encoder_status_show, inode->i_private);
1954		-}
1955		-
1956		-static ssize_t _dpu_encoder_misr_setup(struct file *file,
1957		- const char __user user_buf, size_t count, loff_t ppos)
1958		-{
1959		- struct dpu_encoder_virt *dpu_enc;
1960		- int i = 0, rc;
1961		- char buf[MISR_BUFF_SIZE + 1];
1962		- size_t buff_copy;
1963		- u32 frame_count, enable;
1964		-
1965		- if (!file \|\| !file->private_data)
1966		- return -EINVAL;
1967		-
1968		- dpu_enc = file->private_data;
1969		-
1970		- buff_copy = min_t(size_t, count, MISR_BUFF_SIZE);
1971		- if (copy_from_user(buf, user_buf, buff_copy))
1972		- return -EINVAL;
1973		-
1974		- buf[buff_copy] = 0; /* end of string */
1975		-
1976		- if (sscanf(buf, "%u %u", &enable, &frame_count) != 2)
1977		- return -EINVAL;
1978		-
1979		- rc = _dpu_encoder_power_enable(dpu_enc, true);
1980		- if (rc)
1981		- return rc;
1982		-
1983		- mutex_lock(&dpu_enc->enc_lock);
1984		- dpu_enc->misr_enable = enable;
1985		- dpu_enc->misr_frame_count = frame_count;
1986		- for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1987		- struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1988		-
1989		- if (!phys \|\| !phys->ops.setup_misr)
1990		- continue;
1991		-
1992		- phys->ops.setup_misr(phys, enable, frame_count);
1993		- }
1994		- mutex_unlock(&dpu_enc->enc_lock);
1995		- _dpu_encoder_power_enable(dpu_enc, false);
1996		-
1997		- return count;
1998		-}
1999		-
2000		-static ssize_t _dpu_encoder_misr_read(struct file *file,
2001		- char __user user_buff, size_t count, loff_t ppos)
2002		-{
2003		- struct dpu_encoder_virt *dpu_enc;
2004		- int i = 0, len = 0;
2005		- char buf[MISR_BUFF_SIZE + 1] = {'\0'};
2006		- int rc;
2007		-
2008		- if (*ppos)
2009		- return 0;
2010		-
2011		- if (!file \|\| !file->private_data)
2012		- return -EINVAL;
2013		-
2014		- dpu_enc = file->private_data;
2015		-
2016		- rc = _dpu_encoder_power_enable(dpu_enc, true);
2017		- if (rc)
2018		- return rc;
2019		-
2020		- mutex_lock(&dpu_enc->enc_lock);
2021		- if (!dpu_enc->misr_enable) {
2022		- len += snprintf(buf + len, MISR_BUFF_SIZE - len,
2023		- "disabled\n");
2024		- goto buff_check;
2025		- } else if (dpu_enc->disp_info.capabilities &
2026		- ~MSM_DISPLAY_CAP_VID_MODE) {
2027		- len += snprintf(buf + len, MISR_BUFF_SIZE - len,
2028		- "unsupported\n");
2029		- goto buff_check;
2030		- }
2031		-
2032		- for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2033		- struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2034		-
2035		- if (!phys \|\| !phys->ops.collect_misr)
2036		- continue;
2037		-
2038		- len += snprintf(buf + len, MISR_BUFF_SIZE - len,
2039		- "Intf idx:%d\n", phys->intf_idx - INTF_0);
2040		- len += snprintf(buf + len, MISR_BUFF_SIZE - len, "0x%x\n",
2041		- phys->ops.collect_misr(phys));
2042		- }
2043		-
2044		-buff_check:
2045		- if (count <= len) {
2046		- len = 0;
2047		- goto end;
2048		- }
2049		-
2050		- if (copy_to_user(user_buff, buf, len)) {
2051		- len = -EFAULT;
2052		- goto end;
2053		- }
2054		-
2055		- ppos += len; / increase offset */
2056		-
2057		-end:
2058		- mutex_unlock(&dpu_enc->enc_lock);
2059		- _dpu_encoder_power_enable(dpu_enc, false);
2060		- return len;
2061		-}
	1915	+DEFINE_SHOW_ATTRIBUTE(_dpu_encoder_status);
2062	1916
2063	1917	static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc)
2064	1918	{
2065		- struct dpu_encoder_virt *dpu_enc;
2066		- struct msm_drm_private *priv;
2067		- struct dpu_kms *dpu_kms;
	1919	+ struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
2068	1920	int i;
2069		-
2070		- static const struct file_operations debugfs_status_fops = {
2071		- .open = _dpu_encoder_debugfs_status_open,
2072		- .read = seq_read,
2073		- .llseek = seq_lseek,
2074		- .release = single_release,
2075		- };
2076		-
2077		- static const struct file_operations debugfs_misr_fops = {
2078		- .open = simple_open,
2079		- .read = _dpu_encoder_misr_read,
2080		- .write = _dpu_encoder_misr_setup,
2081		- };
2082	1921
2083	1922	char name[DPU_NAME_SIZE];
2084	1923
2085		- if (!drm_enc \|\| !drm_enc->dev \|\| !drm_enc->dev->dev_private) {
	1924	+ if (!drm_enc->dev) {
2086	1925	DPU_ERROR("invalid encoder or kms\n");
2087	1926	return -EINVAL;
2088	1927	}
2089		-
2090		- dpu_enc = to_dpu_encoder_virt(drm_enc);
2091		- priv = drm_enc->dev->dev_private;
2092		- dpu_kms = to_dpu_kms(priv->kms);
2093	1928
2094	1929	snprintf(name, DPU_NAME_SIZE, "encoder%u", drm_enc->base.id);
2095	1930
2096	1931	/* create overall sub-directory for the encoder */
2097	1932	dpu_enc->debugfs_root = debugfs_create_dir(name,
2098	1933	drm_enc->dev->primary->debugfs_root);
2099		- if (!dpu_enc->debugfs_root)
2100		- return -ENOMEM;
2101	1934
2102	1935	/* don't error check these */
2103	1936	debugfs_create_file("status", 0600,
2104		- dpu_enc->debugfs_root, dpu_enc, &debugfs_status_fops);
2105		-
2106		- debugfs_create_file("misr_data", 0600,
2107		- dpu_enc->debugfs_root, dpu_enc, &debugfs_misr_fops);
	1937	+ dpu_enc->debugfs_root, dpu_enc, &_dpu_encoder_status_fops);
2108	1938
2109	1939	for (i = 0; i < dpu_enc->num_phys_encs; i++)
2110		- if (dpu_enc->phys_encs[i] &&
2111		- dpu_enc->phys_encs[i]->ops.late_register)
	1940	+ if (dpu_enc->phys_encs[i]->ops.late_register)
2112	1941	dpu_enc->phys_encs[i]->ops.late_register(
2113	1942	dpu_enc->phys_encs[i],
2114	1943	dpu_enc->debugfs_root);
2115	1944
2116	1945	return 0;
2117	1946	}
2118		-
2119		-static void _dpu_encoder_destroy_debugfs(struct drm_encoder *drm_enc)
2120		-{
2121		- struct dpu_encoder_virt *dpu_enc;
2122		-
2123		- if (!drm_enc)
2124		- return;
2125		-
2126		- dpu_enc = to_dpu_encoder_virt(drm_enc);
2127		- debugfs_remove_recursive(dpu_enc->debugfs_root);
2128		-}
2129	1947	#else
2130	1948	static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc)
2131	1949	{
2132	1950	return 0;
2133		-}
2134		-
2135		-static void _dpu_encoder_destroy_debugfs(struct drm_encoder *drm_enc)
2136		-{
2137	1951	}
2138	1952	#endif
2139	1953
..	..	@@ -2144,7 +1958,9 @@
2144	1958
2145	1959	static void dpu_encoder_early_unregister(struct drm_encoder *encoder)
2146	1960	{
2147		- _dpu_encoder_destroy_debugfs(encoder);
	1961	+ struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder);
	1962	+
	1963	+ debugfs_remove_recursive(dpu_enc->debugfs_root);
2148	1964	}
2149	1965
2150	1966	static int dpu_encoder_virt_add_phys_encs(
..	..	@@ -2173,7 +1989,7 @@
2173	1989	if (IS_ERR_OR_NULL(enc)) {
2174	1990	DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n",
2175	1991	PTR_ERR(enc));
2176		- return enc == 0 ? -EINVAL : PTR_ERR(enc);
	1992	+ return enc == NULL ? -EINVAL : PTR_ERR(enc);
2177	1993	}
2178	1994
2179	1995	dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
..	..	@@ -2186,12 +2002,17 @@
2186	2002	if (IS_ERR_OR_NULL(enc)) {
2187	2003	DPU_ERROR_ENC(dpu_enc, "failed to init cmd enc: %ld\n",
2188	2004	PTR_ERR(enc));
2189		- return enc == 0 ? -EINVAL : PTR_ERR(enc);
	2005	+ return enc == NULL ? -EINVAL : PTR_ERR(enc);
2190	2006	}
2191	2007
2192	2008	dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
2193	2009	++dpu_enc->num_phys_encs;
2194	2010	}
	2011	+
	2012	+ if (params->split_role == ENC_ROLE_SLAVE)
	2013	+ dpu_enc->cur_slave = enc;
	2014	+ else
	2015	+ dpu_enc->cur_master = enc;
2195	2016
2196	2017	return 0;
2197	2018	}
..	..	@@ -2204,19 +2025,19 @@
2204	2025
2205	2026	static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
2206	2027	struct dpu_kms *dpu_kms,
2207		- struct msm_display_info *disp_info,
2208		- int *drm_enc_mode)
	2028	+ struct msm_display_info *disp_info)
2209	2029	{
2210	2030	int ret = 0;
2211	2031	int i = 0;
2212		- enum dpu_intf_type intf_type;
	2032	+ enum dpu_intf_type intf_type = INTF_NONE;
2213	2033	struct dpu_enc_phys_init_params phys_params;
2214	2034
2215		- if (!dpu_enc \|\| !dpu_kms) {
2216		- DPU_ERROR("invalid arg(s), enc %d kms %d\n",
2217		- dpu_enc != 0, dpu_kms != 0);
	2035	+ if (!dpu_enc) {
	2036	+ DPU_ERROR("invalid arg(s), enc %d\n", dpu_enc != NULL);
2218	2037	return -EINVAL;
2219	2038	}
	2039	+
	2040	+ dpu_enc->cur_master = NULL;
2220	2041
2221	2042	memset(&phys_params, 0, sizeof(phys_params));
2222	2043	phys_params.dpu_kms = dpu_kms;
..	..	@@ -2226,23 +2047,16 @@
2226	2047
2227	2048	DPU_DEBUG("\n");
2228	2049
2229		- if (disp_info->intf_type == DRM_MODE_CONNECTOR_DSI) {
2230		- *drm_enc_mode = DRM_MODE_ENCODER_DSI;
	2050	+ switch (disp_info->intf_type) {
	2051	+ case DRM_MODE_ENCODER_DSI:
2231	2052	intf_type = INTF_DSI;
2232		- } else if (disp_info->intf_type == DRM_MODE_CONNECTOR_HDMIA) {
2233		- *drm_enc_mode = DRM_MODE_ENCODER_TMDS;
2234		- intf_type = INTF_HDMI;
2235		- } else if (disp_info->intf_type == DRM_MODE_CONNECTOR_DisplayPort) {
2236		- *drm_enc_mode = DRM_MODE_ENCODER_TMDS;
	2053	+ break;
	2054	+ case DRM_MODE_ENCODER_TMDS:
2237	2055	intf_type = INTF_DP;
2238		- } else {
2239		- DPU_ERROR_ENC(dpu_enc, "unsupported display interface type\n");
2240		- return -EINVAL;
	2056	+ break;
2241	2057	}
2242	2058
2243	2059	WARN_ON(disp_info->num_of_h_tiles < 1);
2244		-
2245		- dpu_enc->display_num_of_h_tiles = disp_info->num_of_h_tiles;
2246	2060
2247	2061	DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
2248	2062
..	..	@@ -2292,11 +2106,8 @@
2292	2106
2293	2107	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2294	2108	struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2295		-
2296		- if (phys) {
2297		- atomic_set(&phys->vsync_cnt, 0);
2298		- atomic_set(&phys->underrun_cnt, 0);
2299		- }
	2109	+ atomic_set(&phys->vsync_cnt, 0);
	2110	+ atomic_set(&phys->underrun_cnt, 0);
2300	2111	}
2301	2112	mutex_unlock(&dpu_enc->enc_lock);
2302	2113
..	..	@@ -2308,20 +2119,18 @@
2308	2119	struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t,
2309	2120	frame_done_timer);
2310	2121	struct drm_encoder *drm_enc = &dpu_enc->base;
2311		- struct msm_drm_private *priv;
2312	2122	u32 event;
2313	2123
2314		- if (!drm_enc->dev \|\| !drm_enc->dev->dev_private) {
	2124	+ if (!drm_enc->dev) {
2315	2125	DPU_ERROR("invalid parameters\n");
2316	2126	return;
2317	2127	}
2318		- priv = drm_enc->dev->dev_private;
2319	2128
2320	2129	if (!dpu_enc->frame_busy_mask[0] \|\| !dpu_enc->crtc_frame_event_cb) {
2321	2130	DRM_DEBUG_KMS("id:%u invalid timeout frame_busy_mask=%lu\n",
2322	2131	DRMID(drm_enc), dpu_enc->frame_busy_mask[0]);
2323	2132	return;
2324		- } else if (!atomic_xchg(&dpu_enc->frame_done_timeout, 0)) {
	2133	+ } else if (!atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {
2325	2134	DRM_DEBUG_KMS("id:%u invalid timeout\n", DRMID(drm_enc));
2326	2135	return;
2327	2136	}
..	..	@@ -2356,32 +2165,25 @@
2356	2165	struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
2357	2166	struct drm_encoder *drm_enc = NULL;
2358	2167	struct dpu_encoder_virt *dpu_enc = NULL;
2359		- int drm_enc_mode = DRM_MODE_ENCODER_NONE;
2360	2168	int ret = 0;
2361	2169
2362	2170	dpu_enc = to_dpu_encoder_virt(enc);
2363	2171
2364		- mutex_init(&dpu_enc->enc_lock);
2365		- ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info,
2366		- &drm_enc_mode);
	2172	+ ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info);
2367	2173	if (ret)
2368	2174	goto fail;
2369	2175
2370		- dpu_enc->cur_master = NULL;
2371		- spin_lock_init(&dpu_enc->enc_spinlock);
2372		-
2373		- atomic_set(&dpu_enc->frame_done_timeout, 0);
	2176	+ atomic_set(&dpu_enc->frame_done_timeout_ms, 0);
2374	2177	timer_setup(&dpu_enc->frame_done_timer,
2375	2178	dpu_encoder_frame_done_timeout, 0);
2376	2179
2377		- if (disp_info->intf_type == DRM_MODE_CONNECTOR_DSI)
	2180	+ if (disp_info->intf_type == DRM_MODE_ENCODER_DSI)
2378	2181	timer_setup(&dpu_enc->vsync_event_timer,
2379	2182	dpu_encoder_vsync_event_handler,
2380	2183	0);
2381	2184
2382	2185
2383		- mutex_init(&dpu_enc->rc_lock);
2384		- kthread_init_delayed_work(&dpu_enc->delayed_off_work,
	2186	+ INIT_DELAYED_WORK(&dpu_enc->delayed_off_work,
2385	2187	dpu_encoder_off_work);
2386	2188	dpu_enc->idle_timeout = IDLE_TIMEOUT;
2387	2189
..	..	@@ -2423,6 +2225,11 @@
2423	2225
2424	2226	drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs);
2425	2227
	2228	+ spin_lock_init(&dpu_enc->enc_spinlock);
	2229	+ dpu_enc->enabled = false;
	2230	+ mutex_init(&dpu_enc->enc_lock);
	2231	+ mutex_init(&dpu_enc->rc_lock);
	2232	+
2426	2233	return &dpu_enc->base;
2427	2234	}
2428	2235
..	..	@@ -2442,8 +2249,6 @@
2442	2249
2443	2250	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2444	2251	struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2445		- if (!phys)
2446		- continue;
2447	2252
2448	2253	switch (event) {
2449	2254	case MSM_ENC_COMMIT_DONE:
..	..	@@ -2459,7 +2264,7 @@
2459	2264	DPU_ERROR_ENC(dpu_enc, "unknown wait event %d\n",
2460	2265	event);
2461	2266	return -EINVAL;
2462		- };
	2267	+ }
2463	2268
2464	2269	if (fn_wait) {
2465	2270	DPU_ATRACE_BEGIN("wait_for_completion_event");
..	..	@@ -2476,7 +2281,6 @@
2476	2281	enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder)
2477	2282	{
2478	2283	struct dpu_encoder_virt *dpu_enc = NULL;
2479		- int i;
2480	2284
2481	2285	if (!encoder) {
2482	2286	DPU_ERROR("invalid encoder\n");
..	..	@@ -2487,12 +2291,8 @@
2487	2291	if (dpu_enc->cur_master)
2488	2292	return dpu_enc->cur_master->intf_mode;
2489	2293
2490		- for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2491		- struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2492		-
2493		- if (phys)
2494		- return phys->intf_mode;
2495		- }
	2294	+ if (dpu_enc->num_phys_encs)
	2295	+ return dpu_enc->phys_encs[0]->intf_mode;
2496	2296
2497	2297	return INTF_MODE_NONE;
2498	2298	}