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| 1 | +/* SPDX-License-Identifier: GPL-2.0-only */ |
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| 1 | 2 | /* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. |
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| 2 | | - * |
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| 3 | | - * This program is free software; you can redistribute it and/or modify |
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| 4 | | - * it under the terms of the GNU General Public License version 2 and |
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| 5 | | - * only version 2 as published by the Free Software Foundation. |
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| 6 | | - * |
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| 7 | | - * This program is distributed in the hope that it will be useful, |
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| 8 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 9 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 10 | | - * GNU General Public License for more details. |
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| 11 | 3 | */ |
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| 12 | 4 | |
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| 13 | 5 | #ifndef _DPU_CORE_PERF_H_ |
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| .. | .. |
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| 19 | 11 | #include <drm/drm_crtc.h> |
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| 20 | 12 | |
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| 21 | 13 | #include "dpu_hw_catalog.h" |
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| 22 | | -#include "dpu_power_handle.h" |
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| 23 | 14 | |
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| 24 | 15 | #define DPU_PERF_DEFAULT_MAX_CORE_CLK_RATE 412500000 |
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| 25 | 16 | |
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| .. | .. |
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| 30 | 21 | * @core_clk_rate: core clock rate request |
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| 31 | 22 | */ |
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| 32 | 23 | struct dpu_core_perf_params { |
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| 33 | | - u64 max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_MAX]; |
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| 34 | | - u64 bw_ctl[DPU_POWER_HANDLE_DBUS_ID_MAX]; |
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| 24 | + u64 max_per_pipe_ib; |
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| 25 | + u64 bw_ctl; |
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| 35 | 26 | u64 core_clk_rate; |
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| 36 | 27 | }; |
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| 37 | 28 | |
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| .. | .. |
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| 52 | 43 | * @dev: Pointer to drm device |
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| 53 | 44 | * @debugfs_root: top level debug folder |
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| 54 | 45 | * @catalog: Pointer to catalog configuration |
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| 55 | | - * @phandle: Pointer to power handler |
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| 56 | 46 | * @core_clk: Pointer to core clock structure |
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| 57 | 47 | * @core_clk_rate: current core clock rate |
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| 58 | 48 | * @max_core_clk_rate: maximum allowable core clock rate |
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| .. | .. |
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| 66 | 56 | struct drm_device *dev; |
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| 67 | 57 | struct dentry *debugfs_root; |
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| 68 | 58 | struct dpu_mdss_cfg *catalog; |
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| 69 | | - struct dpu_power_handle *phandle; |
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| 70 | 59 | struct dss_clk *core_clk; |
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| 71 | 60 | u64 core_clk_rate; |
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| 72 | 61 | u64 max_core_clk_rate; |
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| .. | .. |
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| 113 | 102 | * @perf: Pointer to core performance context |
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| 114 | 103 | * @dev: Pointer to drm device |
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| 115 | 104 | * @catalog: Pointer to catalog |
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| 116 | | - * @phandle: Pointer to power handle |
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| 117 | 105 | * @core_clk: pointer to core clock |
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| 118 | 106 | */ |
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| 119 | 107 | int dpu_core_perf_init(struct dpu_core_perf *perf, |
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| 120 | 108 | struct drm_device *dev, |
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| 121 | 109 | struct dpu_mdss_cfg *catalog, |
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| 122 | | - struct dpu_power_handle *phandle, |
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| 123 | 110 | struct dss_clk *core_clk); |
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| 111 | + |
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| 112 | +struct dpu_kms; |
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| 124 | 113 | |
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| 125 | 114 | /** |
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| 126 | 115 | * dpu_core_perf_debugfs_init - initialize debugfs for core performance context |
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| 127 | | - * @perf: Pointer to core performance context |
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| 116 | + * @dpu_kms: Pointer to the dpu_kms struct |
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| 128 | 117 | * @debugfs_parent: Pointer to parent debugfs |
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| 129 | 118 | */ |
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| 130 | | -int dpu_core_perf_debugfs_init(struct dpu_core_perf *perf, |
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| 131 | | - struct dentry *parent); |
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| 119 | +int dpu_core_perf_debugfs_init(struct dpu_kms *dpu_kms, struct dentry *parent); |
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| 132 | 120 | |
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| 133 | 121 | #endif /* _DPU_CORE_PERF_H_ */ |
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