add new system file

hc

2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/gpu/drm/drm_cache.c
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@@ -62,10 +62,10 @@
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 {
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 	unsigned long i;
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-	mb();
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+	mb(); /*Full memory barrier used before so that CLFLUSH is ordered*/
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 	for (i = 0; i < num_pages; i++)
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 		drm_clflush_page(*pages++);
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-	mb();
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+	mb(); /*Also used after CLFLUSH so that all cache is flushed*/
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 }
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 #endif
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@@ -92,6 +92,7 @@
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 #elif defined(__powerpc__)
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 	unsigned long i;
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+
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 	for (i = 0; i < num_pages; i++) {
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 		struct page *page = pages[i];
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 		void *page_virtual;
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@@ -125,10 +126,10 @@
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 	if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
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 		struct sg_page_iter sg_iter;
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-		mb();
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-		for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
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+		mb(); /*CLFLUSH is ordered only by using memory barriers*/
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+		for_each_sgtable_page(st, &sg_iter, 0)
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 			drm_clflush_page(sg_page_iter_page(&sg_iter));
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-		mb();
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+		mb(); /*Make sure that all cache line entry is flushed*/
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 		return;
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 	}
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@@ -157,12 +158,13 @@
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 	if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
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 		const int size = boot_cpu_data.x86_clflush_size;
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 		void *end = addr + length;
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+
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 		addr = (void *)(((unsigned long)addr) & -size);
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-		mb();
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+		mb(); /*CLFLUSH is only ordered with a full memory barrier*/
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 		for (; addr < end; addr += size)
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 			clflushopt(addr);
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 		clflushopt(end - 1); /* force serialisation */
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-		mb();
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+		mb(); /*Ensure that evry data cache line entry is flushed*/
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 		return;
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 	}
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