~hc/RK356X_SDK_RELEASE.git

..	..	@@ -21,6 +21,105 @@
21	21	#ifndef _gc_9_0_SH_MASK_HEADER
22	22	#define _gc_9_0_SH_MASK_HEADER
23	23
	24	+//GCEA_EDC_CNT
	25	+#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0
	26	+#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2
	27	+#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4
	28	+#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6
	29	+#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8
	30	+#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa
	31	+#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc
	32	+#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe
	33	+#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10
	34	+#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12
	35	+#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14
	36	+#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16
	37	+#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18
	38	+#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a
	39	+#define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c
	40	+#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
	41	+#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
	42	+#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
	43	+#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
	44	+#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
	45	+#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
	46	+#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L
	47	+#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L
	48	+#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L
	49	+#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L
	50	+#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L
	51	+#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L
	52	+#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L
	53	+#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L
	54	+#define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L
	55	+
	56	+#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0
	57	+#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2
	58	+#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4
	59	+#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6
	60	+#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8
	61	+#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa
	62	+#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc
	63	+#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe
	64	+#define GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10
	65	+#define GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12
	66	+#define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14
	67	+#define GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16
	68	+#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
	69	+#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
	70	+#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
	71	+#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
	72	+#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
	73	+#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
	74	+#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L
	75	+#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L
	76	+#define GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L
	77	+#define GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L
	78	+#define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L
	79	+#define GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L
	80	+
	81	+// addressBlock: gc_cppdec2
	82	+//CPF_EDC_TAG_CNT
	83	+#define CPF_EDC_TAG_CNT__DED_COUNT__SHIFT 0x0
	84	+#define CPF_EDC_TAG_CNT__SEC_COUNT__SHIFT 0x2
	85	+#define CPF_EDC_TAG_CNT__DED_COUNT_MASK 0x00000003L
	86	+#define CPF_EDC_TAG_CNT__SEC_COUNT_MASK 0x0000000CL
	87	+//CPF_EDC_ROQ_CNT
	88	+#define CPF_EDC_ROQ_CNT__COUNT_ME1__SHIFT 0x0
	89	+#define CPF_EDC_ROQ_CNT__COUNT_ME2__SHIFT 0x2
	90	+#define CPF_EDC_ROQ_CNT__COUNT_ME1_MASK 0x00000003L
	91	+#define CPF_EDC_ROQ_CNT__COUNT_ME2_MASK 0x0000000CL
	92	+//CPG_EDC_TAG_CNT
	93	+#define CPG_EDC_TAG_CNT__DED_COUNT__SHIFT 0x0
	94	+#define CPG_EDC_TAG_CNT__SEC_COUNT__SHIFT 0x2
	95	+#define CPG_EDC_TAG_CNT__DED_COUNT_MASK 0x00000003L
	96	+#define CPG_EDC_TAG_CNT__SEC_COUNT_MASK 0x0000000CL
	97	+//CPG_EDC_DMA_CNT
	98	+#define CPG_EDC_DMA_CNT__ROQ_COUNT__SHIFT 0x0
	99	+#define CPG_EDC_DMA_CNT__TAG_DED_COUNT__SHIFT 0x2
	100	+#define CPG_EDC_DMA_CNT__TAG_SEC_COUNT__SHIFT 0x4
	101	+#define CPG_EDC_DMA_CNT__ROQ_COUNT_MASK 0x00000003L
	102	+#define CPG_EDC_DMA_CNT__TAG_DED_COUNT_MASK 0x0000000CL
	103	+#define CPG_EDC_DMA_CNT__TAG_SEC_COUNT_MASK 0x00000030L
	104	+//CPC_EDC_SCRATCH_CNT
	105	+#define CPC_EDC_SCRATCH_CNT__DED_COUNT__SHIFT 0x0
	106	+#define CPC_EDC_SCRATCH_CNT__SEC_COUNT__SHIFT 0x2
	107	+#define CPC_EDC_SCRATCH_CNT__DED_COUNT_MASK 0x00000003L
	108	+#define CPC_EDC_SCRATCH_CNT__SEC_COUNT_MASK 0x0000000CL
	109	+//CPC_EDC_UCODE_CNT
	110	+#define CPC_EDC_UCODE_CNT__DED_COUNT__SHIFT 0x0
	111	+#define CPC_EDC_UCODE_CNT__SEC_COUNT__SHIFT 0x2
	112	+#define CPC_EDC_UCODE_CNT__DED_COUNT_MASK 0x00000003L
	113	+#define CPC_EDC_UCODE_CNT__SEC_COUNT_MASK 0x0000000CL
	114	+//DC_EDC_STATE_CNT
	115	+#define DC_EDC_STATE_CNT__COUNT_ME1__SHIFT 0x0
	116	+#define DC_EDC_STATE_CNT__COUNT_ME1_MASK 0x00000003L
	117	+//DC_EDC_CSINVOC_CNT
	118	+#define DC_EDC_CSINVOC_CNT__COUNT_ME1__SHIFT 0x0
	119	+#define DC_EDC_CSINVOC_CNT__COUNT_ME1_MASK 0x00000003L
	120	+//DC_EDC_RESTORE_CNT
	121	+#define DC_EDC_RESTORE_CNT__COUNT_ME1__SHIFT 0x0
	122	+#define DC_EDC_RESTORE_CNT__COUNT_ME1_MASK 0x00000003L
24	123
25	124	// addressBlock: gc_grbmdec
26	125	//GRBM_CNTL
..	..	@@ -1961,7 +2060,8 @@
1961	2060
1962	2061	// addressBlock: gc_sqdec
1963	2062	//SQ_CONFIG
1964		-#define SQ_CONFIG__UNUSED__SHIFT 0x0
	2063	+#define SQ_CONFIG__DISABLE_BARRIER_WAITCNT__SHIFT 0x0
	2064	+#define SQ_CONFIG__UNUSED__SHIFT 0x1
1965	2065	#define SQ_CONFIG__OVERRIDE_ALU_BUSY__SHIFT 0x7
1966	2066	#define SQ_CONFIG__DEBUG_EN__SHIFT 0x8
1967	2067	#define SQ_CONFIG__DEBUG_SINGLE_MEMOP__SHIFT 0x9
..	..	@@ -1980,7 +2080,8 @@
1980	2080	#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING__SHIFT 0x1d
1981	2081	#define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE__SHIFT 0x1e
1982	2082	#define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE__SHIFT 0x1f
1983		-#define SQ_CONFIG__UNUSED_MASK 0x0000007FL
	2083	+#define SQ_CONFIG__DISABLE_BARRIER_WAITCNT_MASK 0x00000001L
	2084	+#define SQ_CONFIG__UNUSED_MASK 0x0000007EL
1984	2085	#define SQ_CONFIG__OVERRIDE_ALU_BUSY_MASK 0x00000080L
1985	2086	#define SQ_CONFIG__DEBUG_EN_MASK 0x00000100L
1986	2087	#define SQ_CONFIG__DEBUG_SINGLE_MEMOP_MASK 0x00000200L
..	..	@@ -6562,7 +6663,6 @@
6562	6663	#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
6563	6664	#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
6564	6665
6565		-
6566	6666	// addressBlock: gc_utcl2_vml2pfdec
6567	6667	//VM_L2_CNTL
6568	6668	#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0
..	..	@@ -6892,7 +6992,22 @@
6892	6992	#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
6893	6993	#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
6894	6994	#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
6895		-
	6995	+//VM_L2_MEM_ECC_INDEX
	6996	+#define VM_L2_MEM_ECC_INDEX__INDEX__SHIFT 0x0
	6997	+#define VM_L2_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL
	6998	+//VM_L2_WALKER_MEM_ECC_INDEX
	6999	+#define VM_L2_WALKER_MEM_ECC_INDEX__INDEX__SHIFT 0x0
	7000	+#define VM_L2_WALKER_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL
	7001	+//VM_L2_MEM_ECC_CNT
	7002	+#define VM_L2_MEM_ECC_CNT__SEC_COUNT__SHIFT 0xc
	7003	+#define VM_L2_MEM_ECC_CNT__DED_COUNT__SHIFT 0xe
	7004	+#define VM_L2_MEM_ECC_CNT__SEC_COUNT_MASK 0x00003000L
	7005	+#define VM_L2_MEM_ECC_CNT__DED_COUNT_MASK 0x0000C000L
	7006	+//VM_L2_WALKER_MEM_ECC_CNT
	7007	+#define VM_L2_WALKER_MEM_ECC_CNT__SEC_COUNT__SHIFT 0xc
	7008	+#define VM_L2_WALKER_MEM_ECC_CNT__DED_COUNT__SHIFT 0xe
	7009	+#define VM_L2_WALKER_MEM_ECC_CNT__SEC_COUNT_MASK 0x00003000L
	7010	+#define VM_L2_WALKER_MEM_ECC_CNT__DED_COUNT_MASK 0x0000C000L
6896	7011
6897	7012	// addressBlock: gc_utcl2_vml2vcdec
6898	7013	//VM_CONTEXT0_CNTL
..	..	@@ -8626,10 +8741,16 @@
8626	8741	#define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT 0x4
8627	8742	#define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT 0x6
8628	8743	#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT 0x9
	8744	+#define TCP_ADDR_CONFIG__ENABLE64KHASH__SHIFT 0xb
	8745	+#define TCP_ADDR_CONFIG__ENABLE2MHASH__SHIFT 0xc
	8746	+#define TCP_ADDR_CONFIG__ENABLE1GHASH__SHIFT 0xd
8629	8747	#define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0x0000000FL
8630	8748	#define TCP_ADDR_CONFIG__NUM_BANKS_MASK 0x00000030L
8631	8749	#define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK 0x000001C0L
8632	8750	#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK 0x00000200L
	8751	+#define TCP_ADDR_CONFIG__ENABLE64KHASH_MASK 0x00000800L
	8752	+#define TCP_ADDR_CONFIG__ENABLE2MHASH_MASK 0x00001000L
	8753	+#define TCP_ADDR_CONFIG__ENABLE1GHASH_MASK 0x00002000L
8633	8754	//TCP_CREDIT
8634	8755	#define TCP_CREDIT__LFIFO_CREDIT__SHIFT 0x0
8635	8756	#define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x10
..	..	@@ -9033,11 +9154,15 @@
9033	9154	#define TCC_EDC_CNT2__SRC_FIFO_NEXT_RAM_SED_COUNT__SHIFT 0x4
9034	9155	#define TCC_EDC_CNT2__LATENCY_FIFO_NEXT_RAM_SED_COUNT__SHIFT 0x6
9035	9156	#define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SED_COUNT__SHIFT 0x8
	9157	+#define TCC_EDC_CNT2__WRRET_TAG_WRITE_RETURN_SED_COUNT__SHIFT 0xa
	9158	+#define TCC_EDC_CNT2__ATOMIC_RETURN_BUFFER_SED_COUNT__SHIFT 0xc
9036	9159	#define TCC_EDC_CNT2__WRITE_RETURN_SED_COUNT_MASK 0x00000003L
9037	9160	#define TCC_EDC_CNT2__WRITE_CACHE_READ_SED_COUNT_MASK 0x0000000CL
9038	9161	#define TCC_EDC_CNT2__SRC_FIFO_NEXT_RAM_SED_COUNT_MASK 0x00000030L
9039	9162	#define TCC_EDC_CNT2__LATENCY_FIFO_NEXT_RAM_SED_COUNT_MASK 0x000000C0L
9040	9163	#define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SED_COUNT_MASK 0x00000300L
	9164	+#define TCC_EDC_CNT2__WRRET_TAG_WRITE_RETURN_SED_COUNT_MASK 0x00000C00L
	9165	+#define TCC_EDC_CNT2__ATOMIC_RETURN_BUFFER_SED_COUNT_MASK 0x00003000L
9041	9166	//TCC_REDUNDANCY
9042	9167	#define TCC_REDUNDANCY__MC_SEL0__SHIFT 0x0
9043	9168	#define TCC_REDUNDANCY__MC_SEL1__SHIFT 0x1
..	..	@@ -28225,6 +28350,33 @@
28225	28350
28226	28351
28227	28352	// addressBlock: sqind
	28353	+//SQ_DEBUG_STS_GLOBAL
	28354	+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0x000000ffL
	28355	+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x00000000
	28356	+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0x0000ff00L
	28357	+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x00000008
	28358	+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK 0xff000000L
	28359	+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT 0x00000018
	28360	+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK 0x00ff0000L
	28361	+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT 0x00000010
	28362	+#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK 0x0000000fL
	28363	+#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT 0x00000000
	28364	+#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK 0x000000f0L
	28365	+#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT 0x00000004
	28366	+#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x00000001L
	28367	+#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x00000000
	28368	+#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x00000002L
	28369	+#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x00000001
	28370	+#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK 0x0000fff0L
	28371	+#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT 0x00000004
	28372	+#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK 0x0fff0000L
	28373	+#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT 0x00000010
	28374	+
	28375	+//SQ_DEBUG_STS_LOCAL
	28376	+#define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L
	28377	+#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x00000000
	28378	+#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x000003f0L
	28379	+#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x00000004
28228	28380	//SQ_WAVE_MODE
28229	28381	#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0
28230	28382	#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4
..	..	@@ -29818,6 +29970,60 @@
29818	29970	#define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0
29819	29971	#define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL
29820	29972
	29973	+//TA_EDC_CNT
	29974	+#define TA_EDC_CNT__TA_FS_DFIFO_SEC_COUNT__SHIFT 0x0
	29975	+#define TA_EDC_CNT__TA_FS_DFIFO_DED_COUNT__SHIFT 0x2
	29976	+#define TA_EDC_CNT__TA_FS_AFIFO_SED_COUNT__SHIFT 0x4
	29977	+#define TA_EDC_CNT__TA_FL_LFIFO_SED_COUNT__SHIFT 0x6
	29978	+#define TA_EDC_CNT__TA_FX_LFIFO_SED_COUNT__SHIFT 0x8
	29979	+#define TA_EDC_CNT__TA_FS_CFIFO_SED_COUNT__SHIFT 0xa
	29980	+#define TA_EDC_CNT__TA_FS_DFIFO_SEC_COUNT_MASK 0x00000003L
	29981	+#define TA_EDC_CNT__TA_FS_DFIFO_DED_COUNT_MASK 0x0000000CL
	29982	+#define TA_EDC_CNT__TA_FS_AFIFO_SED_COUNT_MASK 0x00000030L
	29983	+#define TA_EDC_CNT__TA_FL_LFIFO_SED_COUNT_MASK 0x000000C0L
	29984	+#define TA_EDC_CNT__TA_FX_LFIFO_SED_COUNT_MASK 0x00000300L
	29985	+#define TA_EDC_CNT__TA_FS_CFIFO_SED_COUNT_MASK 0x00000C00L
29821	29986
	29987	+//TCI_EDC_CNT
	29988	+#define TCI_EDC_CNT__WRITE_RAM_SED_COUNT__SHIFT 0x0
	29989	+#define TCI_EDC_CNT__WRITE_RAM_SED_COUNT_MASK 0x00000003L
	29990	+
	29991	+//TCP_EDC_CNT_NEW
	29992	+#define TCP_EDC_CNT_NEW__CACHE_RAM_SEC_COUNT__SHIFT 0x0
	29993	+#define TCP_EDC_CNT_NEW__CACHE_RAM_DED_COUNT__SHIFT 0x2
	29994	+#define TCP_EDC_CNT_NEW__LFIFO_RAM_SEC_COUNT__SHIFT 0x4
	29995	+#define TCP_EDC_CNT_NEW__LFIFO_RAM_DED_COUNT__SHIFT 0x6
	29996	+#define TCP_EDC_CNT_NEW__CMD_FIFO_SED_COUNT__SHIFT 0x8
	29997	+#define TCP_EDC_CNT_NEW__VM_FIFO_SEC_COUNT__SHIFT 0xa
	29998	+#define TCP_EDC_CNT_NEW__VM_FIFO_DED_COUNT__SHIFT 0xc
	29999	+#define TCP_EDC_CNT_NEW__DB_RAM_SED_COUNT__SHIFT 0xe
	30000	+#define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_SEC_COUNT__SHIFT 0x10
	30001	+#define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_DED_COUNT__SHIFT 0x12
	30002	+#define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_SEC_COUNT__SHIFT 0x14
	30003	+#define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_DED_COUNT__SHIFT 0x16
	30004	+#define TCP_EDC_CNT_NEW__CACHE_RAM_SEC_COUNT_MASK 0x00000003L
	30005	+#define TCP_EDC_CNT_NEW__CACHE_RAM_DED_COUNT_MASK 0x0000000CL
	30006	+#define TCP_EDC_CNT_NEW__LFIFO_RAM_SEC_COUNT_MASK 0x00000030L
	30007	+#define TCP_EDC_CNT_NEW__LFIFO_RAM_DED_COUNT_MASK 0x000000C0L
	30008	+#define TCP_EDC_CNT_NEW__CMD_FIFO_SED_COUNT_MASK 0x00000300L
	30009	+#define TCP_EDC_CNT_NEW__VM_FIFO_SEC_COUNT_MASK 0x00000C00L
	30010	+#define TCP_EDC_CNT_NEW__VM_FIFO_DED_COUNT_MASK 0x00003000L
	30011	+#define TCP_EDC_CNT_NEW__DB_RAM_SED_COUNT_MASK 0x0000C000L
	30012	+#define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_SEC_COUNT_MASK 0x00030000L
	30013	+#define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_DED_COUNT_MASK 0x000C0000L
	30014	+#define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_SEC_COUNT_MASK 0x00300000L
	30015	+#define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_DED_COUNT_MASK 0x00C00000L
	30016	+
	30017	+//TD_EDC_CNT
	30018	+#define TD_EDC_CNT__SS_FIFO_LO_SEC_COUNT__SHIFT 0x0
	30019	+#define TD_EDC_CNT__SS_FIFO_LO_DED_COUNT__SHIFT 0x2
	30020	+#define TD_EDC_CNT__SS_FIFO_HI_SEC_COUNT__SHIFT 0x4
	30021	+#define TD_EDC_CNT__SS_FIFO_HI_DED_COUNT__SHIFT 0x6
	30022	+#define TD_EDC_CNT__CS_FIFO_SED_COUNT__SHIFT 0x8
	30023	+#define TD_EDC_CNT__SS_FIFO_LO_SEC_COUNT_MASK 0x00000003L
	30024	+#define TD_EDC_CNT__SS_FIFO_LO_DED_COUNT_MASK 0x0000000CL
	30025	+#define TD_EDC_CNT__SS_FIFO_HI_SEC_COUNT_MASK 0x00000030L
	30026	+#define TD_EDC_CNT__SS_FIFO_HI_DED_COUNT_MASK 0x000000C0L
	30027	+#define TD_EDC_CNT__CS_FIFO_SED_COUNT_MASK 0x00000300L
29822	30028
29823	30029	#endif