~hc/RK356X_SDK_RELEASE.git

..	..	@@ -21,7 +21,12 @@
21	21	#ifndef _gc_9_0_OFFSET_HEADER
22	22	#define _gc_9_0_OFFSET_HEADER
23	23
24		-
	24	+#define mmSQ_DEBUG_STS_GLOBAL 0x0309
	25	+#define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
	26	+#define mmSQ_DEBUG_STS_GLOBAL2 0x0310
	27	+#define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
	28	+#define mmSQ_DEBUG_STS_GLOBAL3 0x0311
	29	+#define mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0
25	30
26	31	// addressBlock: gc_grbmdec
27	32	// base address: 0x8000
..	..	@@ -829,6 +834,8 @@
829	834	#define mmTD_CNTL_BASE_IDX 0
830	835	#define mmTD_STATUS 0x0526
831	836	#define mmTD_STATUS_BASE_IDX 0
	837	+#define mmTD_EDC_CNT 0x052e
	838	+#define mmTD_EDC_CNT_BASE_IDX 0
832	839	#define mmTD_DSM_CNTL 0x052f
833	840	#define mmTD_DSM_CNTL_BASE_IDX 0
834	841	#define mmTD_DSM_CNTL2 0x0530
..	..	@@ -845,6 +852,8 @@
845	852	#define mmTA_STATUS_BASE_IDX 0
846	853	#define mmTA_SCRATCH 0x0564
847	854	#define mmTA_SCRATCH_BASE_IDX 0
	855	+#define mmTA_EDC_CNT 0x0586
	856	+#define mmTA_EDC_CNT_BASE_IDX 0
848	857
849	858
850	859	// addressBlock: gc_gdsdec
..	..	@@ -1051,6 +1060,13 @@
1051	1060	#define mmGC_USER_RB_BACKEND_DISABLE_BASE_IDX 0
1052	1061
1053	1062
	1063	+// addressBlock: gc_ea_gceadec2
	1064	+// base address: 0x9c00
	1065	+#define mmGCEA_EDC_CNT 0x0706
	1066	+#define mmGCEA_EDC_CNT_BASE_IDX 0
	1067	+#define mmGCEA_EDC_CNT2 0x0707
	1068	+#define mmGCEA_EDC_CNT2_BASE_IDX 0
	1069	+
1054	1070	// addressBlock: gc_rmi_rmidec
1055	1071	// base address: 0x9e00
1056	1072	#define mmRMI_GENERAL_CNTL 0x0780
..	..	@@ -1135,7 +1151,14 @@
1135	1151	#define mmATC_L2_MEM_POWER_LS_BASE_IDX 0
1136	1152	#define mmATC_L2_CGTT_CLK_CTRL 0x080c
1137	1153	#define mmATC_L2_CGTT_CLK_CTRL_BASE_IDX 0
1138		-
	1154	+#define mmATC_L2_CACHE_4K_EDC_INDEX 0x080e
	1155	+#define mmATC_L2_CACHE_4K_EDC_INDEX_BASE_IDX 0
	1156	+#define mmATC_L2_CACHE_2M_EDC_INDEX 0x080f
	1157	+#define mmATC_L2_CACHE_2M_EDC_INDEX_BASE_IDX 0
	1158	+#define mmATC_L2_CACHE_4K_EDC_CNT 0x0810
	1159	+#define mmATC_L2_CACHE_4K_EDC_CNT_BASE_IDX 0
	1160	+#define mmATC_L2_CACHE_2M_EDC_CNT 0x0811
	1161	+#define mmATC_L2_CACHE_2M_EDC_CNT_BASE_IDX 0
1139	1162
1140	1163	// addressBlock: gc_utcl2_vml2pfdec
1141	1164	// base address: 0xa100
..	..	@@ -1195,7 +1218,14 @@
1195	1218	#define mmVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0
1196	1219	#define mmVM_L2_CGTT_CLK_CTRL 0x085e
1197	1220	#define mmVM_L2_CGTT_CLK_CTRL_BASE_IDX 0
1198		-
	1221	+#define mmVM_L2_MEM_ECC_INDEX 0x0860
	1222	+#define mmVM_L2_MEM_ECC_INDEX_BASE_IDX 0
	1223	+#define mmVM_L2_WALKER_MEM_ECC_INDEX 0x0861
	1224	+#define mmVM_L2_WALKER_MEM_ECC_INDEX_BASE_IDX 0
	1225	+#define mmVM_L2_MEM_ECC_CNT 0x0862
	1226	+#define mmVM_L2_MEM_ECC_CNT_BASE_IDX 0
	1227	+#define mmVM_L2_WALKER_MEM_ECC_CNT 0x0863
	1228	+#define mmVM_L2_WALKER_MEM_ECC_CNT_BASE_IDX 0
1199	1229
1200	1230	// addressBlock: gc_utcl2_vml2vcdec
1201	1231	// base address: 0xa200
..	..	@@ -1689,6 +1719,8 @@
1689	1719	#define mmTCP_BUFFER_ADDR_HASH_CNTL_BASE_IDX 0
1690	1720	#define mmTCP_EDC_CNT 0x0b17
1691	1721	#define mmTCP_EDC_CNT_BASE_IDX 0
	1722	+#define mmTCP_EDC_CNT_NEW 0x0b18
	1723	+#define mmTCP_EDC_CNT_NEW_BASE_IDX 0
1692	1724	#define mmTC_CFG_L1_LOAD_POLICY0 0x0b1a
1693	1725	#define mmTC_CFG_L1_LOAD_POLICY0_BASE_IDX 0
1694	1726	#define mmTC_CFG_L1_LOAD_POLICY1 0x0b1b
..	..	@@ -1709,6 +1741,8 @@
1709	1741	#define mmTC_CFG_L1_VOLATILE_BASE_IDX 0
1710	1742	#define mmTC_CFG_L2_VOLATILE 0x0b23
1711	1743	#define mmTC_CFG_L2_VOLATILE_BASE_IDX 0
	1744	+#define mmTCI_EDC_CNT 0x0b60
	1745	+#define mmTCI_EDC_CNT_BASE_IDX 0
1712	1746	#define mmTCI_STATUS 0x0b61
1713	1747	#define mmTCI_STATUS_BASE_IDX 0
1714	1748	#define mmTCI_CNTL_1 0x0b62
..	..	@@ -2195,6 +2229,14 @@
2195	2229	#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX 0
2196	2230	#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3 0x0e1a
2197	2231	#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX 0
	2232	+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE4 0x0e25
	2233	+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE4_BASE_IDX 0
	2234	+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE5 0x0e26
	2235	+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE5_BASE_IDX 0
	2236	+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE6 0x0e27
	2237	+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE6_BASE_IDX 0
	2238	+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE7 0x0e28
	2239	+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE7_BASE_IDX 0
2198	2240	#define mmCOMPUTE_RESTART_X 0x0e1b
2199	2241	#define mmCOMPUTE_RESTART_X_BASE_IDX 0
2200	2242	#define mmCOMPUTE_RESTART_Y 0x0e1c
..	..	@@ -2449,6 +2491,8 @@
2449	2491	#define mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX 0
2450	2492	#define mmGB_EDC_MODE 0x107e
2451	2493	#define mmGB_EDC_MODE_BASE_IDX 0
	2494	+#define mmCP_DEBUG 0x107f
	2495	+#define mmCP_DEBUG_BASE_IDX 0
2452	2496	#define mmCP_CPF_DEBUG 0x1080
2453	2497	#define mmCP_PQ_WPTR_POLL_CNTL 0x1083
2454	2498	#define mmCP_PQ_WPTR_POLL_CNTL_BASE_IDX 0
..	..	@@ -2592,6 +2636,24 @@
2592	2636	#define mmCP_RB_DOORBELL_CONTROL_SCH_7_BASE_IDX 0
2593	2637	#define mmCP_RB_DOORBELL_CLEAR 0x1188
2594	2638	#define mmCP_RB_DOORBELL_CLEAR_BASE_IDX 0
	2639	+#define mmCPF_EDC_TAG_CNT 0x1189
	2640	+#define mmCPF_EDC_TAG_CNT_BASE_IDX 0
	2641	+#define mmCPF_EDC_ROQ_CNT 0x118a
	2642	+#define mmCPF_EDC_ROQ_CNT_BASE_IDX 0
	2643	+#define mmCPG_EDC_TAG_CNT 0x118b
	2644	+#define mmCPG_EDC_TAG_CNT_BASE_IDX 0
	2645	+#define mmCPG_EDC_DMA_CNT 0x118d
	2646	+#define mmCPG_EDC_DMA_CNT_BASE_IDX 0
	2647	+#define mmCPC_EDC_SCRATCH_CNT 0x118e
	2648	+#define mmCPC_EDC_SCRATCH_CNT_BASE_IDX 0
	2649	+#define mmCPC_EDC_UCODE_CNT 0x118f
	2650	+#define mmCPC_EDC_UCODE_CNT_BASE_IDX 0
	2651	+#define mmDC_EDC_STATE_CNT 0x1191
	2652	+#define mmDC_EDC_STATE_CNT_BASE_IDX 0
	2653	+#define mmDC_EDC_CSINVOC_CNT 0x1192
	2654	+#define mmDC_EDC_CSINVOC_CNT_BASE_IDX 0
	2655	+#define mmDC_EDC_RESTORE_CNT 0x1193
	2656	+#define mmDC_EDC_RESTORE_CNT_BASE_IDX 0
2595	2657	#define mmCP_GFX_MQD_CONTROL 0x11a0
2596	2658	#define mmCP_GFX_MQD_CONTROL_BASE_IDX 0
2597	2659	#define mmCP_GFX_MQD_BASE_ADDR 0x11a1
..	..	@@ -7031,6 +7093,7 @@
7031	7093
7032	7094	// addressBlock: sqind
7033	7095	// base address: 0x0
	7096	+#define ixSQ_DEBUG_STS_LOCAL 0x0008
7034	7097	#define ixSQ_WAVE_MODE 0x0011
7035	7098	#define ixSQ_WAVE_STATUS 0x0012
7036	7099	#define ixSQ_WAVE_TRAPSTS 0x0013