~hc/RK356X_SDK_RELEASE.git

..	..	@@ -23,32 +23,35 @@
23	23	*
24	24	*/
25	25
	26	+#include <linux/slab.h>
	27	+
26	28	#include "dm_services.h"
27	29	#include "dc.h"
28	30
	31	+#include "dcn10_init.h"
	32	+
29	33	#include "resource.h"
30	34	#include "include/irq_service_interface.h"
31		-#include "dcn10/dcn10_resource.h"
32		-
33		-#include "dcn10/dcn10_ipp.h"
34		-#include "dcn10/dcn10_mpc.h"
	35	+#include "dcn10_resource.h"
	36	+#include "dcn10_ipp.h"
	37	+#include "dcn10_mpc.h"
35	38	#include "irq/dcn10/irq_service_dcn10.h"
36		-#include "dcn10/dcn10_dpp.h"
	39	+#include "dcn10_dpp.h"
37	40	#include "dcn10_optc.h"
38		-#include "dcn10/dcn10_hw_sequencer.h"
	41	+#include "dcn10_hw_sequencer.h"
39	42	#include "dce110/dce110_hw_sequencer.h"
40		-#include "dcn10/dcn10_opp.h"
41		-#include "dcn10/dcn10_link_encoder.h"
42		-#include "dcn10/dcn10_stream_encoder.h"
43		-#include "dce/dce_clocks.h"
	43	+#include "dcn10_opp.h"
	44	+#include "dcn10_link_encoder.h"
	45	+#include "dcn10_stream_encoder.h"
44	46	#include "dce/dce_clock_source.h"
45	47	#include "dce/dce_audio.h"
46	48	#include "dce/dce_hwseq.h"
47		-#include "../virtual/virtual_stream_encoder.h"
	49	+#include "virtual/virtual_stream_encoder.h"
48	50	#include "dce110/dce110_resource.h"
49	51	#include "dce112/dce112_resource.h"
50	52	#include "dcn10_hubp.h"
51	53	#include "dcn10_hubbub.h"
	54	+#include "dce/dce_panel_cntl.h"
52	55
53	56	#include "soc15_hw_ip.h"
54	57	#include "vega10_ip_offset.h"
..	..	@@ -65,11 +68,12 @@
65	68	#include "dce/dce_abm.h"
66	69	#include "dce/dce_dmcu.h"
67	70	#include "dce/dce_aux.h"
	71	+#include "dce/dce_i2c.h"
68	72
69	73	const struct _vcs_dpi_ip_params_st dcn1_0_ip = {
70	74	.rob_buffer_size_kbytes = 64,
71	75	.det_buffer_size_kbytes = 164,
72		- .dpte_buffer_size_in_pte_reqs = 42,
	76	+ .dpte_buffer_size_in_pte_reqs_luma = 42,
73	77	.dpp_output_buffer_pixels = 2560,
74	78	.opp_output_buffer_lines = 1,
75	79	.pixel_chunk_size_kbytes = 8,
..	..	@@ -151,7 +155,8 @@
151	155	DCN10_CLK_SRC_PLL1,
152	156	DCN10_CLK_SRC_PLL2,
153	157	DCN10_CLK_SRC_PLL3,
154		- DCN10_CLK_SRC_TOTAL
	158	+ DCN10_CLK_SRC_TOTAL,
	159	+ DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3
155	160	};
156	161
157	162	/* begin *********************
..	..	@@ -176,6 +181,14 @@
176	181	#define SRII(reg_name, block, id)\
177	182	.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
178	183	mm ## block ## id ## _ ## reg_name
	184	+
	185	+#define VUPDATE_SRII(reg_name, block, id)\
	186	+ .reg_name[id] = BASE(mm ## reg_name ## 0 ## _ ## block ## id ## _BASE_IDX) + \
	187	+ mm ## reg_name ## 0 ## _ ## block ## id
	188	+
	189	+/* set field/register/bitfield name */
	190	+#define SFRB(field_name, reg_name, bitfield, post_fix)\
	191	+ .field_name = reg_name ## __ ## bitfield ## post_fix
179	192
180	193	/* NBIO */
181	194	#define NBIO_BASE_INNER(seg) \
..	..	@@ -268,7 +281,7 @@
268	281	DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
269	282	};
270	283
271		-static const struct dce_aduio_mask audio_mask = {
	284	+static const struct dce_audio_mask audio_mask = {
272	285	DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
273	286	};
274	287
..	..	@@ -315,6 +328,26 @@
315	328
316	329	static const struct dcn10_link_enc_mask le_mask = {
317	330	LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK)
	331	+};
	332	+
	333	+static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
	334	+ { DCN_PANEL_CNTL_REG_LIST() }
	335	+};
	336	+
	337	+static const struct dce_panel_cntl_shift panel_cntl_shift = {
	338	+ DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
	339	+};
	340	+
	341	+static const struct dce_panel_cntl_mask panel_cntl_mask = {
	342	+ DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
	343	+};
	344	+
	345	+static const struct dce110_aux_registers_shift aux_shift = {
	346	+ DCN10_AUX_MASK_SH_LIST(__SHIFT)
	347	+};
	348	+
	349	+static const struct dce110_aux_registers_mask aux_mask = {
	350	+ DCN10_AUX_MASK_SH_LIST(_MASK)
318	351	};
319	352
320	353	#define ipp_regs(id)\
..	..	@@ -407,11 +440,13 @@
407	440	};
408	441
409	442	static const struct dcn_mpc_shift mpc_shift = {
410		- MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
	443	+ MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT),\
	444	+ SFRB(CUR_VUPDATE_LOCK_SET, CUR0_VUPDATE_LOCK_SET0, CUR0_VUPDATE_LOCK_SET, __SHIFT)
411	445	};
412	446
413	447	static const struct dcn_mpc_mask mpc_mask = {
414		- MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK),
	448	+ MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK),\
	449	+ SFRB(CUR_VUPDATE_LOCK_SET, CUR0_VUPDATE_LOCK_SET0, CUR0_VUPDATE_LOCK_SET, _MASK)
415	450	};
416	451
417	452	#define tg_regs(id)\
..	..	@@ -432,7 +467,6 @@
432	467	TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
433	468	};
434	469
435		-
436	470	static const struct bios_registers bios_regs = {
437	471	NBIO_SR(BIOS_SCRATCH_3),
438	472	NBIO_SR(BIOS_SCRATCH_6)
..	..	@@ -442,7 +476,6 @@
442	476	[id] = {\
443	477	HUBP_REG_LIST_DCN10(id)\
444	478	}
445		-
446	479
447	480	static const struct dcn_mi_registers hubp_regs[] = {
448	481	hubp_regs(0),
..	..	@@ -459,7 +492,6 @@
459	492	HUBP_MASK_SH_LIST_DCN10(_MASK)
460	493	};
461	494
462		-
463	495	static const struct dcn_hubbub_registers hubbub_reg = {
464	496	HUBBUB_REG_LIST_DCN10(0)
465	497	};
..	..	@@ -471,6 +503,28 @@
471	503	static const struct dcn_hubbub_mask hubbub_mask = {
472	504	HUBBUB_MASK_SH_LIST_DCN10(_MASK)
473	505	};
	506	+
	507	+static int map_transmitter_id_to_phy_instance(
	508	+ enum transmitter transmitter)
	509	+{
	510	+ switch (transmitter) {
	511	+ case TRANSMITTER_UNIPHY_A:
	512	+ return 0;
	513	+ break;
	514	+ case TRANSMITTER_UNIPHY_B:
	515	+ return 1;
	516	+ break;
	517	+ case TRANSMITTER_UNIPHY_C:
	518	+ return 2;
	519	+ break;
	520	+ case TRANSMITTER_UNIPHY_D:
	521	+ return 3;
	522	+ break;
	523	+ default:
	524	+ ASSERT(0);
	525	+ return 0;
	526	+ }
	527	+}
474	528
475	529	#define clk_src_regs(index, pllid)\
476	530	[index] = {\
..	..	@@ -492,7 +546,6 @@
492	546	CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
493	547	};
494	548
495		-
496	549	static const struct resource_caps res_cap = {
497	550	.num_timing_generator = 4,
498	551	.num_opp = 4,
..	..	@@ -500,11 +553,48 @@
500	553	.num_audio = 4,
501	554	.num_stream_encoder = 4,
502	555	.num_pll = 4,
	556	+ .num_ddc = 4,
	557	+};
	558	+
	559	+static const struct resource_caps rv2_res_cap = {
	560	+ .num_timing_generator = 3,
	561	+ .num_opp = 3,
	562	+ .num_video_plane = 3,
	563	+ .num_audio = 3,
	564	+ .num_stream_encoder = 3,
	565	+ .num_pll = 3,
	566	+ .num_ddc = 4,
	567	+};
	568	+
	569	+static const struct dc_plane_cap plane_cap = {
	570	+ .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
	571	+ .blends_with_above = true,
	572	+ .blends_with_below = true,
	573	+ .per_pixel_alpha = true,
	574	+
	575	+ .pixel_format_support = {
	576	+ .argb8888 = true,
	577	+ .nv12 = true,
	578	+ .fp16 = true,
	579	+ .p010 = true
	580	+ },
	581	+
	582	+ .max_upscale_factor = {
	583	+ .argb8888 = 16000,
	584	+ .nv12 = 16000,
	585	+ .fp16 = 1
	586	+ },
	587	+
	588	+ .max_downscale_factor = {
	589	+ .argb8888 = 250,
	590	+ .nv12 = 250,
	591	+ .fp16 = 1
	592	+ }
503	593	};
504	594
505	595	static const struct dc_debug_options debug_defaults_drv = {
506	596	.sanity_checks = true,
507		- .disable_dmcu = true,
	597	+ .disable_dmcu = false,
508	598	.force_abm_enable = false,
509	599	.timing_trace = false,
510	600	.clock_trace = true,
..	..	@@ -518,8 +608,8 @@
518	608	.disable_pplib_clock_request = false,
519	609	.disable_pplib_wm_range = false,
520	610	.pplib_wm_report_mode = WM_REPORT_DEFAULT,
521		- .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
522		- .force_single_disp_pipe_split = true,
	611	+ .pipe_split_policy = MPC_SPLIT_AVOID,
	612	+ .force_single_disp_pipe_split = false,
523	613	.disable_dcc = DCC_ENABLE,
524	614	.voltage_align_fclk = true,
525	615	.disable_stereo_support = true,
..	..	@@ -528,16 +618,18 @@
528	618	.az_endpoint_mute_only = true,
529	619	.recovery_enabled = false, /enable this by default after testing./
530	620	.max_downscale_src_width = 3840,
	621	+ .underflow_assert_delay_us = 0xFFFFFFFF,
531	622	};
532	623
533	624	static const struct dc_debug_options debug_defaults_diags = {
534		- .disable_dmcu = true,
	625	+ .disable_dmcu = false,
535	626	.force_abm_enable = false,
536	627	.timing_trace = true,
537	628	.clock_trace = true,
538	629	.disable_stutter = true,
539	630	.disable_pplib_clock_request = true,
540		- .disable_pplib_wm_range = true
	631	+ .disable_pplib_wm_range = true,
	632	+ .underflow_assert_delay_us = 0xFFFFFFFF,
541	633	};
542	634
543	635	static void dcn10_dpp_destroy(struct dpp **dpp)
..	..	@@ -594,7 +686,7 @@
594	686	return &opp->base;
595	687	}
596	688
597		-struct aux_engine *dcn10_aux_engine_create(
	689	+struct dce_aux *dcn10_aux_engine_create(
598	690	struct dc_context *ctx,
599	691	uint32_t inst)
600	692	{
..	..	@@ -606,11 +698,47 @@
606	698
607	699	dce110_aux_engine_construct(aux_engine, ctx, inst,
608	700	SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
609		- &aux_engine_regs[inst]);
	701	+ &aux_engine_regs[inst],
	702	+ &aux_mask,
	703	+ &aux_shift,
	704	+ ctx->dc->caps.extended_aux_timeout_support);
610	705
611	706	return &aux_engine->base;
612	707	}
	708	+#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
613	709
	710	+static const struct dce_i2c_registers i2c_hw_regs[] = {
	711	+ i2c_inst_regs(1),
	712	+ i2c_inst_regs(2),
	713	+ i2c_inst_regs(3),
	714	+ i2c_inst_regs(4),
	715	+ i2c_inst_regs(5),
	716	+ i2c_inst_regs(6),
	717	+};
	718	+
	719	+static const struct dce_i2c_shift i2c_shifts = {
	720	+ I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
	721	+};
	722	+
	723	+static const struct dce_i2c_mask i2c_masks = {
	724	+ I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
	725	+};
	726	+
	727	+struct dce_i2c_hw *dcn10_i2c_hw_create(
	728	+ struct dc_context *ctx,
	729	+ uint32_t inst)
	730	+{
	731	+ struct dce_i2c_hw *dce_i2c_hw =
	732	+ kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
	733	+
	734	+ if (!dce_i2c_hw)
	735	+ return NULL;
	736	+
	737	+ dcn1_i2c_hw_construct(dce_i2c_hw, ctx, inst,
	738	+ &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
	739	+
	740	+ return dce_i2c_hw;
	741	+}
614	742	static struct mpc dcn10_mpc_create(struct dc_context ctx)
615	743	{
616	744	struct dcn10_mpc *mpc10 = kzalloc(sizeof(struct dcn10_mpc),
..	..	@@ -630,18 +758,18 @@
630	758
631	759	static struct hubbub dcn10_hubbub_create(struct dc_context ctx)
632	760	{
633		- struct hubbub *hubbub = kzalloc(sizeof(struct hubbub),
	761	+ struct dcn10_hubbub *dcn10_hubbub = kzalloc(sizeof(struct dcn10_hubbub),
634	762	GFP_KERNEL);
635	763
636		- if (!hubbub)
	764	+ if (!dcn10_hubbub)
637	765	return NULL;
638	766
639		- hubbub1_construct(hubbub, ctx,
	767	+ hubbub1_construct(&dcn10_hubbub->base, ctx,
640	768	&hubbub_reg,
641	769	&hubbub_shift,
642	770	&hubbub_mask);
643	771
644		- return hubbub;
	772	+ return &dcn10_hubbub->base;
645	773	}
646	774
647	775	static struct timing_generator *dcn10_timing_generator_create(
..	..	@@ -669,12 +797,12 @@
669	797	static const struct encoder_feature_support link_enc_feature = {
670	798	.max_hdmi_deep_color = COLOR_DEPTH_121212,
671	799	.max_hdmi_pixel_clock = 600000,
672		- .ycbcr420_supported = true,
	800	+ .hdmi_ycbcr420_supported = true,
	801	+ .dp_ycbcr420_supported = true,
673	802	.flags.bits.IS_HBR2_CAPABLE = true,
674	803	.flags.bits.IS_HBR3_CAPABLE = true,
675	804	.flags.bits.IS_TPS3_CAPABLE = true,
676		- .flags.bits.IS_TPS4_CAPABLE = true,
677		- .flags.bits.IS_YCBCR_CAPABLE = true
	805	+ .flags.bits.IS_TPS4_CAPABLE = true
678	806	};
679	807
680	808	struct link_encoder *dcn10_link_encoder_create(
..	..	@@ -682,20 +810,41 @@
682	810	{
683	811	struct dcn10_link_encoder *enc10 =
684	812	kzalloc(sizeof(struct dcn10_link_encoder), GFP_KERNEL);
	813	+ int link_regs_id;
685	814
686	815	if (!enc10)
687	816	return NULL;
688	817
	818	+ link_regs_id =
	819	+ map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
	820	+
689	821	dcn10_link_encoder_construct(enc10,
690	822	enc_init_data,
691	823	&link_enc_feature,
692		- &link_enc_regs[enc_init_data->transmitter],
	824	+ &link_enc_regs[link_regs_id],
693	825	&link_enc_aux_regs[enc_init_data->channel - 1],
694	826	&link_enc_hpd_regs[enc_init_data->hpd_source],
695	827	&le_shift,
696	828	&le_mask);
697	829
698	830	return &enc10->base;
	831	+}
	832	+
	833	+static struct panel_cntl dcn10_panel_cntl_create(const struct panel_cntl_init_data init_data)
	834	+{
	835	+ struct dce_panel_cntl *panel_cntl =
	836	+ kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
	837	+
	838	+ if (!panel_cntl)
	839	+ return NULL;
	840	+
	841	+ dce_panel_cntl_construct(panel_cntl,
	842	+ init_data,
	843	+ &panel_cntl_regs[init_data->inst],
	844	+ &panel_cntl_shift,
	845	+ &panel_cntl_mask);
	846	+
	847	+ return &panel_cntl->base;
699	848	}
700	849
701	850	struct clock_source *dcn10_clock_source_create(
..	..	@@ -711,12 +860,13 @@
711	860	if (!clk_src)
712	861	return NULL;
713	862
714		- if (dce110_clk_src_construct(clk_src, ctx, bios, id,
	863	+ if (dce112_clk_src_construct(clk_src, ctx, bios, id,
715	864	regs, &cs_shift, &cs_mask)) {
716	865	clk_src->base.dp_clk_src = dp_clk_src;
717	866	return &clk_src->base;
718	867	}
719	868
	869	+ kfree(clk_src);
720	870	BREAK_TO_DEBUGGER();
721	871	return NULL;
722	872	}
..	..	@@ -801,27 +951,24 @@
801	951	*clk_src = NULL;
802	952	}
803	953
804		-static struct pp_smu_funcs_rv dcn10_pp_smu_create(struct dc_context ctx)
	954	+static struct pp_smu_funcs dcn10_pp_smu_create(struct dc_context ctx)
805	955	{
806		- struct pp_smu_funcs_rv pp_smu = kzalloc(sizeof(pp_smu), GFP_KERNEL);
	956	+ struct pp_smu_funcs pp_smu = kzalloc(sizeof(pp_smu), GFP_KERNEL);
807	957
808	958	if (!pp_smu)
809	959	return pp_smu;
810	960
811		- dm_pp_get_funcs_rv(ctx, pp_smu);
	961	+ dm_pp_get_funcs(ctx, pp_smu);
812	962	return pp_smu;
813	963	}
814	964
815		-static void destruct(struct dcn10_resource_pool *pool)
	965	+static void dcn10_resource_destruct(struct dcn10_resource_pool *pool)
816	966	{
817	967	unsigned int i;
818	968
819	969	for (i = 0; i < pool->base.stream_enc_count; i++) {
820	970	if (pool->base.stream_enc[i] != NULL) {
821		- /* TODO: free dcn version of stream encoder once implemented
822		- * rather than using virtual stream encoder
823		- */
824		- kfree(pool->base.stream_enc[i]);
	971	+ kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
825	972	pool->base.stream_enc[i] = NULL;
826	973	}
827	974	}
..	..	@@ -859,13 +1006,20 @@
859	1006	kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
860	1007	pool->base.timing_generators[i] = NULL;
861	1008	}
862		-
863		- if (pool->base.engines[i] != NULL)
864		- pool->base.engines[i]->funcs->destroy_engine(&pool->base.engines[i]);
865	1009	}
866	1010
867		- for (i = 0; i < pool->base.stream_enc_count; i++)
868		- kfree(pool->base.stream_enc[i]);
	1011	+ for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
	1012	+ if (pool->base.engines[i] != NULL)
	1013	+ dce110_engine_destroy(&pool->base.engines[i]);
	1014	+ if (pool->base.hw_i2cs[i] != NULL) {
	1015	+ kfree(pool->base.hw_i2cs[i]);
	1016	+ pool->base.hw_i2cs[i] = NULL;
	1017	+ }
	1018	+ if (pool->base.sw_i2cs[i] != NULL) {
	1019	+ kfree(pool->base.sw_i2cs[i]);
	1020	+ pool->base.sw_i2cs[i] = NULL;
	1021	+ }
	1022	+ }
869	1023
870	1024	for (i = 0; i < pool->base.audio_count; i++) {
871	1025	if (pool->base.audios[i])
..	..	@@ -890,9 +1044,6 @@
890	1044	if (pool->base.dmcu != NULL)
891	1045	dce_dmcu_destroy(&pool->base.dmcu);
892	1046
893		- if (pool->base.dccg != NULL)
894		- dce_dccg_destroy(&pool->base.dccg);
895		-
896	1047	kfree(pool->base.pp_smu);
897	1048	}
898	1049
..	..	@@ -916,8 +1067,8 @@
916	1067	struct pixel_clk_params *pixel_clk_params)
917	1068	{
918	1069	const struct dc_stream_state *stream = pipe_ctx->stream;
919		- pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz;
920		- pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id;
	1070	+ pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
	1071	+ pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
921	1072	pixel_clk_params->signal_type = pipe_ctx->stream->signal;
922	1073	pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
923	1074	/* TODO: un-hardcode*/
..	..	@@ -933,7 +1084,9 @@
933	1084	pixel_clk_params->color_depth = COLOR_DEPTH_888;
934	1085
935	1086	if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
936		- pixel_clk_params->requested_pix_clk /= 2;
	1087	+ pixel_clk_params->requested_pix_clk_100hz /= 2;
	1088	+ if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
	1089	+ pixel_clk_params->requested_pix_clk_100hz *= 2;
937	1090
938	1091	}
939	1092
..	..	@@ -968,24 +1121,6 @@
968	1121	{
969	1122	struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
970	1123
971		- /TODO Seems unneeded anymore /
972		- /* if (old_context && resource_is_stream_unchanged(old_context, stream)) {
973		- if (stream != NULL && old_context->streams[i] != NULL) {
974		- todo: shouldn't have to copy missing parameter here
975		- resource_build_bit_depth_reduction_params(stream,
976		- &stream->bit_depth_params);
977		- stream->clamping.pixel_encoding =
978		- stream->timing.pixel_encoding;
979		-
980		- resource_build_bit_depth_reduction_params(stream,
981		- &stream->bit_depth_params);
982		- build_clamping_params(stream);
983		-
984		- continue;
985		- }
986		- }
987		- */
988		-
989	1124	if (!pipe_ctx)
990	1125	return DC_ERROR_UNEXPECTED;
991	1126
..	..	@@ -1019,7 +1154,7 @@
1019	1154	{
1020	1155	struct resource_context *res_ctx = &context->res_ctx;
1021	1156	struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
1022		- struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool);
	1157	+ struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe);
1023	1158
1024	1159	if (!head_pipe) {
1025	1160	ASSERT(0);
..	..	@@ -1056,7 +1191,7 @@
1056	1191	{
1057	1192	struct dcn10_resource_pool dcn10_pool = TO_DCN10_RES_POOL(pool);
1058	1193
1059		- destruct(dcn10_pool);
	1194	+ dcn10_resource_destruct(dcn10_pool);
1060	1195	kfree(dcn10_pool);
1061	1196	*pool = NULL;
1062	1197	}
..	..	@@ -1071,6 +1206,114 @@
1071	1206	return DC_OK;
1072	1207	}
1073	1208
	1209	+static enum dc_status dcn10_validate_global(struct dc dc, struct dc_state context)
	1210	+{
	1211	+ int i, j;
	1212	+ bool video_down_scaled = false;
	1213	+ bool video_large = false;
	1214	+ bool desktop_large = false;
	1215	+ bool dcc_disabled = false;
	1216	+ bool mpo_enabled = false;
	1217	+
	1218	+ for (i = 0; i < context->stream_count; i++) {
	1219	+ if (context->stream_status[i].plane_count == 0)
	1220	+ continue;
	1221	+
	1222	+ if (context->stream_status[i].plane_count > 2)
	1223	+ return DC_FAIL_UNSUPPORTED_1;
	1224	+
	1225	+ if (context->stream_status[i].plane_count > 1)
	1226	+ mpo_enabled = true;
	1227	+
	1228	+ for (j = 0; j < context->stream_status[i].plane_count; j++) {
	1229	+ struct dc_plane_state *plane =
	1230	+ context->stream_status[i].plane_states[j];
	1231	+
	1232	+
	1233	+ if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
	1234	+
	1235	+ if (plane->src_rect.width > plane->dst_rect.width \|\|
	1236	+ plane->src_rect.height > plane->dst_rect.height)
	1237	+ video_down_scaled = true;
	1238	+
	1239	+ if (plane->src_rect.width >= 3840)
	1240	+ video_large = true;
	1241	+
	1242	+ } else {
	1243	+ if (plane->src_rect.width >= 3840)
	1244	+ desktop_large = true;
	1245	+ if (!plane->dcc.enable)
	1246	+ dcc_disabled = true;
	1247	+ }
	1248	+ }
	1249	+ }
	1250	+
	1251	+ /* Disable MPO in multi-display configurations. */
	1252	+ if (context->stream_count > 1 && mpo_enabled)
	1253	+ return DC_FAIL_UNSUPPORTED_1;
	1254	+
	1255	+ /*
	1256	+ * Workaround: On DCN10 there is UMC issue that causes underflow when
	1257	+ * playing 4k video on 4k desktop with video downscaled and single channel
	1258	+ * memory
	1259	+ */
	1260	+ if (video_large && desktop_large && video_down_scaled && dcc_disabled &&
	1261	+ dc->dcn_soc->number_of_channels == 1)
	1262	+ return DC_FAIL_SURFACE_VALIDATE;
	1263	+
	1264	+ return DC_OK;
	1265	+}
	1266	+
	1267	+static enum dc_status dcn10_patch_unknown_plane_state(struct dc_plane_state *plane_state)
	1268	+{
	1269	+ enum dc_status result = DC_OK;
	1270	+
	1271	+ enum surface_pixel_format surf_pix_format = plane_state->format;
	1272	+ unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
	1273	+
	1274	+ enum swizzle_mode_values swizzle = DC_SW_LINEAR;
	1275	+
	1276	+ if (bpp == 64)
	1277	+ swizzle = DC_SW_64KB_D;
	1278	+ else
	1279	+ swizzle = DC_SW_64KB_S;
	1280	+
	1281	+ plane_state->tiling_info.gfx9.swizzle = swizzle;
	1282	+ return result;
	1283	+}
	1284	+
	1285	+struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link(
	1286	+ struct resource_context *res_ctx,
	1287	+ const struct resource_pool *pool,
	1288	+ struct dc_stream_state *stream)
	1289	+{
	1290	+ int i;
	1291	+ int j = -1;
	1292	+ struct dc_link *link = stream->link;
	1293	+
	1294	+ for (i = 0; i < pool->stream_enc_count; i++) {
	1295	+ if (!res_ctx->is_stream_enc_acquired[i] &&
	1296	+ pool->stream_enc[i]) {
	1297	+ /* Store first available for MST second display
	1298	+ * in daisy chain use case
	1299	+ */
	1300	+ j = i;
	1301	+ if (pool->stream_enc[i]->id ==
	1302	+ link->link_enc->preferred_engine)
	1303	+ return pool->stream_enc[i];
	1304	+ }
	1305	+ }
	1306	+
	1307	+ /*
	1308	+ * For CZ and later, we can allow DIG FE and BE to differ for all display types
	1309	+ */
	1310	+
	1311	+ if (j >= 0)
	1312	+ return pool->stream_enc[j];
	1313	+
	1314	+ return NULL;
	1315	+}
	1316	+
1074	1317	static const struct dc_cap_funcs cap_funcs = {
1075	1318	.get_dcc_compression_cap = dcn10_get_dcc_compression_cap
1076	1319	};
..	..	@@ -1078,10 +1321,14 @@
1078	1321	static const struct resource_funcs dcn10_res_pool_funcs = {
1079	1322	.destroy = dcn10_destroy_resource_pool,
1080	1323	.link_enc_create = dcn10_link_encoder_create,
	1324	+ .panel_cntl_create = dcn10_panel_cntl_create,
1081	1325	.validate_bandwidth = dcn_validate_bandwidth,
1082	1326	.acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer,
1083	1327	.validate_plane = dcn10_validate_plane,
1084		- .add_stream_to_ctx = dcn10_add_stream_to_ctx
	1328	+ .validate_global = dcn10_validate_global,
	1329	+ .add_stream_to_ctx = dcn10_add_stream_to_ctx,
	1330	+ .patch_unknown_plane_state = dcn10_patch_unknown_plane_state,
	1331	+ .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link
1085	1332	};
1086	1333
1087	1334	static uint32_t read_pipe_fuses(struct dc_context *ctx)
..	..	@@ -1092,7 +1339,7 @@
1092	1339	return value;
1093	1340	}
1094	1341
1095		-static bool construct(
	1342	+static bool dcn10_resource_construct(
1096	1343	uint8_t num_virtual_links,
1097	1344	struct dc *dc,
1098	1345	struct dcn10_resource_pool *pool)
..	..	@@ -1104,7 +1351,10 @@
1104	1351
1105	1352	ctx->dc_bios->regs = &bios_regs;
1106	1353
1107		- pool->base.res_cap = &res_cap;
	1354	+ if (ctx->dce_version == DCN_VERSION_1_01)
	1355	+ pool->base.res_cap = &rv2_res_cap;
	1356	+ else
	1357	+ pool->base.res_cap = &res_cap;
1108	1358	pool->base.funcs = &dcn10_res_pool_funcs;
1109	1359
1110	1360	/*
..	..	@@ -1120,6 +1370,8 @@
1120	1370	/* max pipe num for ASIC before check pipe fuses */
1121	1371	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1122	1372
	1373	+ if (dc->ctx->dce_version == DCN_VERSION_1_01)
	1374	+ pool->base.pipe_count = 3;
1123	1375	dc->caps.max_video_width = 3840;
1124	1376	dc->caps.max_downscale_ratio = 200;
1125	1377	dc->caps.i2c_speed_in_khz = 100;
..	..	@@ -1127,8 +1379,44 @@
1127	1379	dc->caps.max_slave_planes = 1;
1128	1380	dc->caps.is_apu = true;
1129	1381	dc->caps.post_blend_color_processing = false;
	1382	+ dc->caps.extended_aux_timeout_support = false;
	1383	+
1130	1384	/* Raven DP PHY HBR2 eye diagram pattern is not stable. Use TP4 */
1131	1385	dc->caps.force_dp_tps4_for_cp2520 = true;
	1386	+
	1387	+ /* Color pipeline capabilities */
	1388	+ dc->caps.color.dpp.dcn_arch = 1;
	1389	+ dc->caps.color.dpp.input_lut_shared = 1;
	1390	+ dc->caps.color.dpp.icsc = 1;
	1391	+ dc->caps.color.dpp.dgam_ram = 1;
	1392	+ dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
	1393	+ dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
	1394	+ dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
	1395	+ dc->caps.color.dpp.dgam_rom_caps.pq = 0;
	1396	+ dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
	1397	+ dc->caps.color.dpp.post_csc = 0;
	1398	+ dc->caps.color.dpp.gamma_corr = 0;
	1399	+
	1400	+ dc->caps.color.dpp.hw_3d_lut = 0;
	1401	+ dc->caps.color.dpp.ogam_ram = 1; // RGAM on DCN1
	1402	+ dc->caps.color.dpp.ogam_rom_caps.srgb = 1;
	1403	+ dc->caps.color.dpp.ogam_rom_caps.bt2020 = 1;
	1404	+ dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
	1405	+ dc->caps.color.dpp.ogam_rom_caps.pq = 0;
	1406	+ dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
	1407	+ dc->caps.color.dpp.ocsc = 1;
	1408	+
	1409	+ /* no post-blend color operations */
	1410	+ dc->caps.color.mpc.gamut_remap = 0;
	1411	+ dc->caps.color.mpc.num_3dluts = 0;
	1412	+ dc->caps.color.mpc.shared_3d_lut = 0;
	1413	+ dc->caps.color.mpc.ogam_ram = 0;
	1414	+ dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
	1415	+ dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
	1416	+ dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
	1417	+ dc->caps.color.mpc.ogam_rom_caps.pq = 0;
	1418	+ dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
	1419	+ dc->caps.color.mpc.ocsc = 0;
1132	1420
1133	1421	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1134	1422	dc->debug = debug_defaults_drv;
..	..	@@ -1151,12 +1439,18 @@
1151	1439	dcn10_clock_source_create(ctx, ctx->dc_bios,
1152	1440	CLOCK_SOURCE_COMBO_PHY_PLL2,
1153	1441	&clk_src_regs[2], false);
1154		- pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
1155		- dcn10_clock_source_create(ctx, ctx->dc_bios,
1156		- CLOCK_SOURCE_COMBO_PHY_PLL3,
1157		- &clk_src_regs[3], false);
	1442	+
	1443	+ if (dc->ctx->dce_version == DCN_VERSION_1_0) {
	1444	+ pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
	1445	+ dcn10_clock_source_create(ctx, ctx->dc_bios,
	1446	+ CLOCK_SOURCE_COMBO_PHY_PLL3,
	1447	+ &clk_src_regs[3], false);
	1448	+ }
1158	1449
1159	1450	pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL;
	1451	+
	1452	+ if (dc->ctx->dce_version == DCN_VERSION_1_01)
	1453	+ pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL;
1160	1454
1161	1455	pool->base.dp_clock_source =
1162	1456	dcn10_clock_source_create(ctx, ctx->dc_bios,
..	..	@@ -1170,13 +1464,6 @@
1170	1464	BREAK_TO_DEBUGGER();
1171	1465	goto fail;
1172	1466	}
1173		- }
1174		-
1175		- pool->base.dccg = dcn1_dccg_create(ctx);
1176		- if (pool->base.dccg == NULL) {
1177		- dm_error("DC: failed to create display clock!\n");
1178		- BREAK_TO_DEBUGGER();
1179		- goto fail;
1180	1467	}
1181	1468
1182	1469	pool->base.dmcu = dcn10_dmcu_create(ctx,
..	..	@@ -1199,10 +1486,20 @@
1199	1486	goto fail;
1200	1487	}
1201	1488
1202		- dml_init_instance(&dc->dml, DML_PROJECT_RAVEN1);
	1489	+ dml_init_instance(&dc->dml, &dcn1_0_soc, &dcn1_0_ip, DML_PROJECT_RAVEN1);
1203	1490	memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults));
1204	1491	memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults));
1205	1492
	1493	+ if (dc->ctx->dce_version == DCN_VERSION_1_01) {
	1494	+ struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc;
	1495	+ struct dcn_ip_params *dcn_ip = dc->dcn_ip;
	1496	+ struct display_mode_lib *dml = &dc->dml;
	1497	+
	1498	+ dml->ip.max_num_dpp = 3;
	1499	+ /* TODO how to handle 23.84? */
	1500	+ dcn_soc->dram_clock_change_latency = 23;
	1501	+ dcn_ip->max_num_dpp = 3;
	1502	+ }
1206	1503	if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
1207	1504	dc->dcn_soc->urgent_latency = 3;
1208	1505	dc->debug.disable_dmcu = true;
..	..	@@ -1226,6 +1523,14 @@
1226	1523	}
1227	1524
1228	1525	pool->base.pp_smu = dcn10_pp_smu_create(ctx);
	1526	+
	1527	+ /*
	1528	+ * Right now SMU/PPLIB and DAL all have the AZ D3 force PME notification *
	1529	+ * implemented. So AZ D3 should work.For issue 197007. *
	1530	+ */
	1531	+ if (pool->base.pp_smu != NULL
	1532	+ && pool->base.pp_smu->rv_funcs.set_pme_wa_enable != NULL)
	1533	+ dc->debug.az_endpoint_mute_only = false;
1229	1534
1230	1535	if (!dc->debug.disable_pplib_clock_request)
1231	1536	dcn_bw_update_from_pplib(dc);
..	..	@@ -1292,7 +1597,11 @@
1292	1597	dm_error("DC: failed to create tg!\n");
1293	1598	goto fail;
1294	1599	}
	1600	+ /* check next valid pipe */
	1601	+ j++;
	1602	+ }
1295	1603
	1604	+ for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1296	1605	pool->base.engines[i] = dcn10_aux_engine_create(ctx, i);
1297	1606	if (pool->base.engines[i] == NULL) {
1298	1607	BREAK_TO_DEBUGGER();
..	..	@@ -1300,9 +1609,14 @@
1300	1609	"DC:failed to create aux engine!!\n");
1301	1610	goto fail;
1302	1611	}
1303		-
1304		- /* check next valid pipe */
1305		- j++;
	1612	+ pool->base.hw_i2cs[i] = dcn10_i2c_hw_create(ctx, i);
	1613	+ if (pool->base.hw_i2cs[i] == NULL) {
	1614	+ BREAK_TO_DEBUGGER();
	1615	+ dm_error(
	1616	+ "DC:failed to create hw i2c!!\n");
	1617	+ goto fail;
	1618	+ }
	1619	+ pool->base.sw_i2cs[i] = NULL;
1306	1620	}
1307	1621
1308	1622	/* valid pipe num */
..	..	@@ -1337,19 +1651,22 @@
1337	1651	dcn10_hw_sequencer_construct(dc);
1338	1652	dc->caps.max_planes = pool->base.pipe_count;
1339	1653
	1654	+ for (i = 0; i < dc->caps.max_planes; ++i)
	1655	+ dc->caps.planes[i] = plane_cap;
	1656	+
1340	1657	dc->cap_funcs = cap_funcs;
1341	1658
1342	1659	return true;
1343	1660
1344	1661	fail:
1345	1662
1346		- destruct(pool);
	1663	+ dcn10_resource_destruct(pool);
1347	1664
1348	1665	return false;
1349	1666	}
1350	1667
1351	1668	struct resource_pool *dcn10_create_resource_pool(
1352		- uint8_t num_virtual_links,
	1669	+ const struct dc_init_data *init_data,
1353	1670	struct dc *dc)
1354	1671	{
1355	1672	struct dcn10_resource_pool *pool =
..	..	@@ -1358,7 +1675,7 @@
1358	1675	if (!pool)
1359	1676	return NULL;
1360	1677
1361		- if (construct(num_virtual_links, dc, pool))
	1678	+ if (dcn10_resource_construct(init_data->num_virtual_links, dc, pool))
1362	1679	return &pool->base;
1363	1680
1364	1681	kfree(pool);