add new system file

hc

2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
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@@ -23,6 +23,8 @@
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  *
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  */
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+#include <linux/slab.h>
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+
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 #include "dm_services.h"
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 #include "dcn10_opp.h"
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 #include "reg_helper.h"
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@@ -166,7 +168,10 @@
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 		REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 0);
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 		break;
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 	case PIXEL_ENCODING_YCBCR422:
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-		REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 1);
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+		REG_UPDATE_3(FMT_CONTROL,
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+				FMT_PIXEL_ENCODING, 1,
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+				FMT_SUBSAMPLING_MODE, 2,
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+				FMT_CBCR_BIT_REDUCTION_BYPASS, 0);
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 		break;
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 	case PIXEL_ENCODING_YCBCR420:
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 		REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 2);
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@@ -234,6 +239,9 @@
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 	REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
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 			FMT_DYNAMIC_EXP_EN, 0,
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 			FMT_DYNAMIC_EXP_MODE, 0);
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+
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+	if (opp->dyn_expansion == DYN_EXPANSION_DISABLE)
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+		return;
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 	/*00 - 10-bit -> 12-bit dynamic expansion*/
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 	/*01 - 8-bit  -> 12-bit dynamic expansion*/
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@@ -365,6 +373,9 @@
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 	 */
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 	REG_UPDATE(OPPBUF_CONTROL, OPPBUF_PIXEL_REPETITION, oppbuf->pixel_repetition);
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+	/* Controls the number of padded pixels at the end of a segment */
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+	if (REG(OPPBUF_CONTROL1))
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+		REG_UPDATE(OPPBUF_CONTROL1, OPPBUF_NUM_SEGMENT_PADDED_PIXELS, oppbuf->num_segment_padded_pixels);
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 }
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 void opp1_pipe_clock_control(struct output_pixel_processor *opp, bool enable)
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@@ -391,6 +402,8 @@
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 		.opp_program_bit_depth_reduction = opp1_program_bit_depth_reduction,
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 		.opp_program_stereo = opp1_program_stereo,
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 		.opp_pipe_clock_control = opp1_pipe_clock_control,
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+		.opp_set_disp_pattern_generator = NULL,
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+		.dpg_is_blanked = NULL,
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 		.opp_destroy = opp1_destroy
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 };
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