add new system file

hc

2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
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@@ -49,6 +49,17 @@
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 	SRI(CURSOR_HOT_SPOT, CURSOR, id), \
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 	SRI(CURSOR_DST_OFFSET, CURSOR, id)
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+#define IPP_REG_LIST_DCN20(id) \
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+	IPP_REG_LIST_DCN(id), \
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+	SRI(CURSOR_SETTINGS, HUBPREQ, id), \
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+	SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id), \
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+	SRI(CURSOR_SURFACE_ADDRESS, CURSOR0_, id), \
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+	SRI(CURSOR_SIZE, CURSOR0_, id), \
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+	SRI(CURSOR_CONTROL, CURSOR0_, id), \
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+	SRI(CURSOR_POSITION, CURSOR0_, id), \
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+	SRI(CURSOR_HOT_SPOT, CURSOR0_, id), \
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+	SRI(CURSOR_DST_OFFSET, CURSOR0_, id)
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+
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 #define CURSOR0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT	0x4
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 #define CURSOR0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK		0x00000010L
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 #define CURSOR1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT	0x4
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@@ -91,6 +102,25 @@
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 	IPP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
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 	IPP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \
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 	IPP_SF(CNVC_CFG0_FORMAT_CONTROL, OUTPUT_FP, mask_sh)
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+
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+#define IPP_MASK_SH_LIST_DCN20(mask_sh) \
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+	IPP_MASK_SH_LIST_DCN(mask_sh), \
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+	IPP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \
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+	IPP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
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+	IPP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
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+	IPP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
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+	IPP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
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+	IPP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \
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+	IPP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
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+	IPP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
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+	IPP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
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+	IPP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
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+	IPP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
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+	IPP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \
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+	IPP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \
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+	IPP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
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+	IPP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
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+	IPP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh)
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 #define IPP_DCN10_REG_FIELD_LIST(type) \
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 	type CNVC_SURFACE_PIXEL_FORMAT; \
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@@ -162,4 +192,11 @@
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 	const struct dcn10_ipp_shift *ipp_shift,
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 	const struct dcn10_ipp_mask *ipp_mask);
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+void dcn20_ipp_construct(struct dcn10_ipp *ippn10,
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+	struct dc_context *ctx,
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+	int inst,
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+	const struct dcn10_ipp_registers *regs,
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+	const struct dcn10_ipp_shift *ipp_shift,
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+	const struct dcn10_ipp_mask *ipp_mask);
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+
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 #endif /* _DCN10_IPP_H_ */