forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
....@@ -23,6 +23,8 @@
2323  *
2424  */
2525 
26
+#include <linux/slab.h>
27
+
2628 #include "dce/dce_8_0_d.h"
2729 #include "dce/dce_8_0_sh_mask.h"
2830 
....@@ -40,22 +42,22 @@
4042 #include "dce/dce_mem_input.h"
4143 #include "dce/dce_link_encoder.h"
4244 #include "dce/dce_stream_encoder.h"
43
-#include "dce/dce_mem_input.h"
4445 #include "dce/dce_ipp.h"
4546 #include "dce/dce_transform.h"
4647 #include "dce/dce_opp.h"
47
-#include "dce/dce_clocks.h"
4848 #include "dce/dce_clock_source.h"
4949 #include "dce/dce_audio.h"
5050 #include "dce/dce_hwseq.h"
5151 #include "dce80/dce80_hw_sequencer.h"
5252 #include "dce100/dce100_resource.h"
53
+#include "dce/dce_panel_cntl.h"
5354 
5455 #include "reg_helper.h"
5556 
5657 #include "dce/dce_dmcu.h"
5758 #include "dce/dce_aux.h"
5859 #include "dce/dce_abm.h"
60
+#include "dce/dce_i2c.h"
5961 /* TODO remove this include */
6062 
6163 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
....@@ -77,6 +79,7 @@
7779 
7880 #ifndef mmBIOS_SCRATCH_2
7981 	#define mmBIOS_SCRATCH_2 0x05CB
82
+	#define mmBIOS_SCRATCH_3 0x05CC
8083 	#define mmBIOS_SCRATCH_6 0x05CF
8184 #endif
8285 
....@@ -152,19 +155,6 @@
152155 /* set register offset with instance */
153156 #define SRI(reg_name, block, id)\
154157 	.reg_name = mm ## block ## id ## _ ## reg_name
155
-
156
-
157
-static const struct dccg_registers disp_clk_regs = {
158
-		CLK_COMMON_REG_LIST_DCE_BASE()
159
-};
160
-
161
-static const struct dccg_shift disp_clk_shift = {
162
-		CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
163
-};
164
-
165
-static const struct dccg_mask disp_clk_mask = {
166
-		CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
167
-};
168158 
169159 #define ipp_regs(id)\
170160 [id] = {\
....@@ -277,6 +267,18 @@
277267 		SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
278268 };
279269 
270
+static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
271
+	{ DCE_PANEL_CNTL_REG_LIST() }
272
+};
273
+
274
+static const struct dce_panel_cntl_shift panel_cntl_shift = {
275
+	DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
276
+};
277
+
278
+static const struct dce_panel_cntl_mask panel_cntl_mask = {
279
+	DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
280
+};
281
+
280282 #define opp_regs(id)\
281283 [id] = {\
282284 	OPP_DCE_80_REG_LIST(id),\
....@@ -297,6 +299,14 @@
297299 
298300 static const struct dce_opp_mask opp_mask = {
299301 	OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK)
302
+};
303
+
304
+static const struct dce110_aux_registers_shift aux_shift = {
305
+	DCE10_AUX_MASK_SH_LIST(__SHIFT)
306
+};
307
+
308
+static const struct dce110_aux_registers_mask aux_mask = {
309
+	DCE10_AUX_MASK_SH_LIST(_MASK)
300310 };
301311 
302312 #define aux_engine_regs(id)\
....@@ -333,7 +343,7 @@
333343 		AUD_COMMON_MASK_SH_LIST(__SHIFT)
334344 };
335345 
336
-static const struct dce_aduio_mask audio_mask = {
346
+static const struct dce_audio_mask audio_mask = {
337347 		AUD_COMMON_MASK_SH_LIST(_MASK)
338348 };
339349 
....@@ -358,6 +368,7 @@
358368 };
359369 
360370 static const struct bios_registers bios_regs = {
371
+	.BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
361372 	.BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
362373 };
363374 
....@@ -366,6 +377,7 @@
366377 		.num_audio = 6,
367378 		.num_stream_encoder = 6,
368379 		.num_pll = 3,
380
+		.num_ddc = 6,
369381 };
370382 
371383 static const struct resource_caps res_cap_81 = {
....@@ -373,6 +385,7 @@
373385 		.num_audio = 7,
374386 		.num_stream_encoder = 7,
375387 		.num_pll = 3,
388
+		.num_ddc = 6,
376389 };
377390 
378391 static const struct resource_caps res_cap_83 = {
....@@ -380,6 +393,29 @@
380393 		.num_audio = 6,
381394 		.num_stream_encoder = 6,
382395 		.num_pll = 2,
396
+		.num_ddc = 2,
397
+};
398
+
399
+static const struct dc_plane_cap plane_cap = {
400
+	.type = DC_PLANE_TYPE_DCE_RGB,
401
+
402
+	.pixel_format_support = {
403
+			.argb8888 = true,
404
+			.nv12 = false,
405
+			.fp16 = false
406
+	},
407
+
408
+	.max_upscale_factor = {
409
+			.argb8888 = 16000,
410
+			.nv12 = 1,
411
+			.fp16 = 1
412
+	},
413
+
414
+	.max_downscale_factor = {
415
+			.argb8888 = 250,
416
+			.nv12 = 1,
417
+			.fp16 = 1
418
+	}
383419 };
384420 
385421 static const struct dce_dmcu_registers dmcu_regs = {
....@@ -415,6 +451,37 @@
415451 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
416452 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
417453 #endif
454
+
455
+static int map_transmitter_id_to_phy_instance(
456
+	enum transmitter transmitter)
457
+{
458
+	switch (transmitter) {
459
+	case TRANSMITTER_UNIPHY_A:
460
+		return 0;
461
+	break;
462
+	case TRANSMITTER_UNIPHY_B:
463
+		return 1;
464
+	break;
465
+	case TRANSMITTER_UNIPHY_C:
466
+		return 2;
467
+	break;
468
+	case TRANSMITTER_UNIPHY_D:
469
+		return 3;
470
+	break;
471
+	case TRANSMITTER_UNIPHY_E:
472
+		return 4;
473
+	break;
474
+	case TRANSMITTER_UNIPHY_F:
475
+		return 5;
476
+	break;
477
+	case TRANSMITTER_UNIPHY_G:
478
+		return 6;
479
+	break;
480
+	default:
481
+		ASSERT(0);
482
+		return 0;
483
+	}
484
+}
418485 
419486 static void read_dce_straps(
420487 	struct dc_context *ctx,
....@@ -464,7 +531,7 @@
464531 	return &opp->base;
465532 }
466533 
467
-struct aux_engine *dce80_aux_engine_create(
534
+struct dce_aux *dce80_aux_engine_create(
468535 	struct dc_context *ctx,
469536 	uint32_t inst)
470537 {
....@@ -476,11 +543,61 @@
476543 
477544 	dce110_aux_engine_construct(aux_engine, ctx, inst,
478545 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
479
-				    &aux_engine_regs[inst]);
546
+				    &aux_engine_regs[inst],
547
+					&aux_mask,
548
+					&aux_shift,
549
+					ctx->dc->caps.extended_aux_timeout_support);
480550 
481551 	return &aux_engine->base;
482552 }
553
+#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
483554 
555
+static const struct dce_i2c_registers i2c_hw_regs[] = {
556
+		i2c_inst_regs(1),
557
+		i2c_inst_regs(2),
558
+		i2c_inst_regs(3),
559
+		i2c_inst_regs(4),
560
+		i2c_inst_regs(5),
561
+		i2c_inst_regs(6),
562
+};
563
+
564
+static const struct dce_i2c_shift i2c_shifts = {
565
+		I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
566
+};
567
+
568
+static const struct dce_i2c_mask i2c_masks = {
569
+		I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
570
+};
571
+
572
+struct dce_i2c_hw *dce80_i2c_hw_create(
573
+	struct dc_context *ctx,
574
+	uint32_t inst)
575
+{
576
+	struct dce_i2c_hw *dce_i2c_hw =
577
+		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
578
+
579
+	if (!dce_i2c_hw)
580
+		return NULL;
581
+
582
+	dce_i2c_hw_construct(dce_i2c_hw, ctx, inst,
583
+				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
584
+
585
+	return dce_i2c_hw;
586
+}
587
+
588
+struct dce_i2c_sw *dce80_i2c_sw_create(
589
+	struct dc_context *ctx)
590
+{
591
+	struct dce_i2c_sw *dce_i2c_sw =
592
+		kzalloc(sizeof(struct dce_i2c_sw), GFP_KERNEL);
593
+
594
+	if (!dce_i2c_sw)
595
+		return NULL;
596
+
597
+	dce_i2c_sw_construct(dce_i2c_sw, ctx);
598
+
599
+	return dce_i2c_sw;
600
+}
484601 static struct stream_encoder *dce80_stream_encoder_create(
485602 	enum engine_id eng_id,
486603 	struct dc_context *ctx)
....@@ -599,8 +716,7 @@
599716 		.max_hdmi_deep_color = COLOR_DEPTH_121212,
600717 		.max_hdmi_pixel_clock = 297000,
601718 		.flags.bits.IS_HBR2_CAPABLE = true,
602
-		.flags.bits.IS_TPS3_CAPABLE = true,
603
-		.flags.bits.IS_YCBCR_CAPABLE = true
719
+		.flags.bits.IS_TPS3_CAPABLE = true
604720 };
605721 
606722 struct link_encoder *dce80_link_encoder_create(
....@@ -608,17 +724,38 @@
608724 {
609725 	struct dce110_link_encoder *enc110 =
610726 		kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
727
+	int link_regs_id;
611728 
612729 	if (!enc110)
613730 		return NULL;
614731 
732
+	link_regs_id =
733
+		map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
734
+
615735 	dce110_link_encoder_construct(enc110,
616736 				      enc_init_data,
617737 				      &link_enc_feature,
618
-				      &link_enc_regs[enc_init_data->transmitter],
738
+				      &link_enc_regs[link_regs_id],
619739 				      &link_enc_aux_regs[enc_init_data->channel - 1],
620740 				      &link_enc_hpd_regs[enc_init_data->hpd_source]);
621741 	return &enc110->base;
742
+}
743
+
744
+static struct panel_cntl *dce80_panel_cntl_create(const struct panel_cntl_init_data *init_data)
745
+{
746
+	struct dce_panel_cntl *panel_cntl =
747
+		kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
748
+
749
+	if (!panel_cntl)
750
+		return NULL;
751
+
752
+	dce_panel_cntl_construct(panel_cntl,
753
+			init_data,
754
+			&panel_cntl_regs[init_data->inst],
755
+			&panel_cntl_shift,
756
+			&panel_cntl_mask);
757
+
758
+	return &panel_cntl->base;
622759 }
623760 
624761 struct clock_source *dce80_clock_source_create(
....@@ -640,6 +777,7 @@
640777 		return &clk_src->base;
641778 	}
642779 
780
+	kfree(clk_src);
643781 	BREAK_TO_DEBUGGER();
644782 	return NULL;
645783 }
....@@ -665,7 +803,7 @@
665803 	return &ipp->base;
666804 }
667805 
668
-static void destruct(struct dce110_resource_pool *pool)
806
+static void dce80_resource_destruct(struct dce110_resource_pool *pool)
669807 {
670808 	unsigned int i;
671809 
....@@ -688,9 +826,19 @@
688826 			kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
689827 			pool->base.timing_generators[i] = NULL;
690828 		}
829
+	}
691830 
831
+	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
692832 		if (pool->base.engines[i] != NULL)
693833 			dce110_engine_destroy(&pool->base.engines[i]);
834
+		if (pool->base.hw_i2cs[i] != NULL) {
835
+			kfree(pool->base.hw_i2cs[i]);
836
+			pool->base.hw_i2cs[i] = NULL;
837
+		}
838
+		if (pool->base.sw_i2cs[i] != NULL) {
839
+			kfree(pool->base.sw_i2cs[i]);
840
+			pool->base.sw_i2cs[i] = NULL;
841
+		}
694842 	}
695843 
696844 	for (i = 0; i < pool->base.stream_enc_count; i++) {
....@@ -719,9 +867,6 @@
719867 		}
720868 	}
721869 
722
-	if (pool->base.dccg != NULL)
723
-		dce_dccg_destroy(&pool->base.dccg);
724
-
725870 	if (pool->base.irqs != NULL) {
726871 		dal_irq_service_destroy(&pool->base.irqs);
727872 	}
....@@ -729,11 +874,25 @@
729874 
730875 bool dce80_validate_bandwidth(
731876 	struct dc *dc,
732
-	struct dc_state *context)
877
+	struct dc_state *context,
878
+	bool fast_validate)
733879 {
734
-	/* TODO implement when needed but for now hardcode max value*/
735
-	context->bw.dce.dispclk_khz = 681000;
736
-	context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER;
880
+	int i;
881
+	bool at_least_one_pipe = false;
882
+
883
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
884
+		if (context->res_ctx.pipe_ctx[i].stream)
885
+			at_least_one_pipe = true;
886
+	}
887
+
888
+	if (at_least_one_pipe) {
889
+		/* TODO implement when needed but for now hardcode max value*/
890
+		context->bw_ctx.bw.dce.dispclk_khz = 681000;
891
+		context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
892
+	} else {
893
+		context->bw_ctx.bw.dce.dispclk_khz = 0;
894
+		context->bw_ctx.bw.dce.yclk_khz = 0;
895
+	}
737896 
738897 	return true;
739898 }
....@@ -772,7 +931,7 @@
772931 {
773932 	struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
774933 
775
-	destruct(dce110_pool);
934
+	dce80_resource_destruct(dce110_pool);
776935 	kfree(dce110_pool);
777936 	*pool = NULL;
778937 }
....@@ -780,10 +939,12 @@
780939 static const struct resource_funcs dce80_res_pool_funcs = {
781940 	.destroy = dce80_destroy_resource_pool,
782941 	.link_enc_create = dce80_link_encoder_create,
942
+	.panel_cntl_create = dce80_panel_cntl_create,
783943 	.validate_bandwidth = dce80_validate_bandwidth,
784944 	.validate_plane = dce100_validate_plane,
785945 	.add_stream_to_ctx = dce100_add_stream_to_ctx,
786
-	.validate_global = dce80_validate_global
946
+	.validate_global = dce80_validate_global,
947
+	.find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link
787948 };
788949 
789950 static bool dce80_construct(
....@@ -793,9 +954,7 @@
793954 {
794955 	unsigned int i;
795956 	struct dc_context *ctx = dc->ctx;
796
-	struct dc_firmware_info info;
797957 	struct dc_bios *bp;
798
-	struct dm_pp_static_clock_info static_clk_info = {0};
799958 
800959 	ctx->dc_bios->regs = &bios_regs;
801960 
....@@ -813,6 +972,7 @@
813972 	dc->caps.i2c_speed_in_khz = 40;
814973 	dc->caps.max_cursor_size = 128;
815974 	dc->caps.dual_link_dvi = true;
975
+	dc->caps.extended_aux_timeout_support = false;
816976 
817977 	/*************************************************
818978 	 *  Create resources                             *
....@@ -820,8 +980,7 @@
820980 
821981 	bp = ctx->dc_bios;
822982 
823
-	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
824
-		info.external_clock_source_frequency_for_dp != 0) {
983
+	if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
825984 		pool->base.dp_clock_source =
826985 				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
827986 
....@@ -858,16 +1017,6 @@
8581017 		}
8591018 	}
8601019 
861
-	pool->base.dccg = dce_dccg_create(ctx,
862
-			&disp_clk_regs,
863
-			&disp_clk_shift,
864
-			&disp_clk_mask);
865
-	if (pool->base.dccg == NULL) {
866
-		dm_error("DC: failed to create display clock!\n");
867
-		BREAK_TO_DEBUGGER();
868
-		goto res_create_fail;
869
-	}
870
-
8711020 	pool->base.dmcu = dce_dmcu_create(ctx,
8721021 			&dmcu_regs,
8731022 			&dmcu_shift,
....@@ -887,9 +1036,6 @@
8871036 		BREAK_TO_DEBUGGER();
8881037 		goto res_create_fail;
8891038 	}
890
-	if (dm_pp_get_static_clocks(ctx, &static_clk_info))
891
-		pool->base.dccg->max_clks_state =
892
-					static_clk_info.max_clocks_state;
8931039 
8941040 	{
8951041 		struct irq_service_init_data init_data;
....@@ -935,7 +1081,9 @@
9351081 			dm_error("DC: failed to create output pixel processor!\n");
9361082 			goto res_create_fail;
9371083 		}
1084
+	}
9381085 
1086
+	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
9391087 		pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
9401088 		if (pool->base.engines[i] == NULL) {
9411089 			BREAK_TO_DEBUGGER();
....@@ -943,9 +1091,27 @@
9431091 				"DC:failed to create aux engine!!\n");
9441092 			goto res_create_fail;
9451093 		}
1094
+		pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);
1095
+		if (pool->base.hw_i2cs[i] == NULL) {
1096
+			BREAK_TO_DEBUGGER();
1097
+			dm_error(
1098
+				"DC:failed to create i2c engine!!\n");
1099
+			goto res_create_fail;
1100
+		}
1101
+		pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx);
1102
+		if (pool->base.sw_i2cs[i] == NULL) {
1103
+			BREAK_TO_DEBUGGER();
1104
+			dm_error(
1105
+				"DC:failed to create sw i2c!!\n");
1106
+			goto res_create_fail;
1107
+		}
9461108 	}
9471109 
9481110 	dc->caps.max_planes =  pool->base.pipe_count;
1111
+
1112
+	for (i = 0; i < dc->caps.max_planes; ++i)
1113
+		dc->caps.planes[i] = plane_cap;
1114
+
9491115 	dc->caps.disable_dp_clk_share = true;
9501116 
9511117 	if (!resource_construct(num_virtual_links, dc, &pool->base,
....@@ -958,7 +1124,7 @@
9581124 	return true;
9591125 
9601126 res_create_fail:
961
-	destruct(pool);
1127
+	dce80_resource_destruct(pool);
9621128 	return false;
9631129 }
9641130 
....@@ -975,6 +1141,7 @@
9751141 	if (dce80_construct(num_virtual_links, dc, pool))
9761142 		return &pool->base;
9771143 
1144
+	kfree(pool);
9781145 	BREAK_TO_DEBUGGER();
9791146 	return NULL;
9801147 }
....@@ -986,9 +1153,7 @@
9861153 {
9871154 	unsigned int i;
9881155 	struct dc_context *ctx = dc->ctx;
989
-	struct dc_firmware_info info;
9901156 	struct dc_bios *bp;
991
-	struct dm_pp_static_clock_info static_clk_info = {0};
9921157 
9931158 	ctx->dc_bios->regs = &bios_regs;
9941159 
....@@ -1013,8 +1178,7 @@
10131178 
10141179 	bp = ctx->dc_bios;
10151180 
1016
-	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
1017
-		info.external_clock_source_frequency_for_dp != 0) {
1181
+	if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
10181182 		pool->base.dp_clock_source =
10191183 				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
10201184 
....@@ -1051,16 +1215,6 @@
10511215 		}
10521216 	}
10531217 
1054
-	pool->base.dccg = dce_dccg_create(ctx,
1055
-			&disp_clk_regs,
1056
-			&disp_clk_shift,
1057
-			&disp_clk_mask);
1058
-	if (pool->base.dccg == NULL) {
1059
-		dm_error("DC: failed to create display clock!\n");
1060
-		BREAK_TO_DEBUGGER();
1061
-		goto res_create_fail;
1062
-	}
1063
-
10641218 	pool->base.dmcu = dce_dmcu_create(ctx,
10651219 			&dmcu_regs,
10661220 			&dmcu_shift,
....@@ -1080,10 +1234,6 @@
10801234 		BREAK_TO_DEBUGGER();
10811235 		goto res_create_fail;
10821236 	}
1083
-
1084
-	if (dm_pp_get_static_clocks(ctx, &static_clk_info))
1085
-		pool->base.dccg->max_clks_state =
1086
-					static_clk_info.max_clocks_state;
10871237 
10881238 	{
10891239 		struct irq_service_init_data init_data;
....@@ -1131,7 +1281,35 @@
11311281 		}
11321282 	}
11331283 
1284
+	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1285
+		pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
1286
+		if (pool->base.engines[i] == NULL) {
1287
+			BREAK_TO_DEBUGGER();
1288
+			dm_error(
1289
+				"DC:failed to create aux engine!!\n");
1290
+			goto res_create_fail;
1291
+		}
1292
+		pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);
1293
+		if (pool->base.hw_i2cs[i] == NULL) {
1294
+			BREAK_TO_DEBUGGER();
1295
+			dm_error(
1296
+				"DC:failed to create i2c engine!!\n");
1297
+			goto res_create_fail;
1298
+		}
1299
+		pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx);
1300
+		if (pool->base.sw_i2cs[i] == NULL) {
1301
+			BREAK_TO_DEBUGGER();
1302
+			dm_error(
1303
+				"DC:failed to create sw i2c!!\n");
1304
+			goto res_create_fail;
1305
+		}
1306
+	}
1307
+
11341308 	dc->caps.max_planes =  pool->base.pipe_count;
1309
+
1310
+	for (i = 0; i < dc->caps.max_planes; ++i)
1311
+		dc->caps.planes[i] = plane_cap;
1312
+
11351313 	dc->caps.disable_dp_clk_share = true;
11361314 
11371315 	if (!resource_construct(num_virtual_links, dc, &pool->base,
....@@ -1144,7 +1322,7 @@
11441322 	return true;
11451323 
11461324 res_create_fail:
1147
-	destruct(pool);
1325
+	dce80_resource_destruct(pool);
11481326 	return false;
11491327 }
11501328 
....@@ -1161,6 +1339,7 @@
11611339 	if (dce81_construct(num_virtual_links, dc, pool))
11621340 		return &pool->base;
11631341 
1342
+	kfree(pool);
11641343 	BREAK_TO_DEBUGGER();
11651344 	return NULL;
11661345 }
....@@ -1172,9 +1351,7 @@
11721351 {
11731352 	unsigned int i;
11741353 	struct dc_context *ctx = dc->ctx;
1175
-	struct dc_firmware_info info;
11761354 	struct dc_bios *bp;
1177
-	struct dm_pp_static_clock_info static_clk_info = {0};
11781355 
11791356 	ctx->dc_bios->regs = &bios_regs;
11801357 
....@@ -1199,8 +1376,7 @@
11991376 
12001377 	bp = ctx->dc_bios;
12011378 
1202
-	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
1203
-		info.external_clock_source_frequency_for_dp != 0) {
1379
+	if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
12041380 		pool->base.dp_clock_source =
12051381 				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
12061382 
....@@ -1233,16 +1409,6 @@
12331409 		}
12341410 	}
12351411 
1236
-	pool->base.dccg = dce_dccg_create(ctx,
1237
-			&disp_clk_regs,
1238
-			&disp_clk_shift,
1239
-			&disp_clk_mask);
1240
-	if (pool->base.dccg == NULL) {
1241
-		dm_error("DC: failed to create display clock!\n");
1242
-		BREAK_TO_DEBUGGER();
1243
-		goto res_create_fail;
1244
-	}
1245
-
12461412 	pool->base.dmcu = dce_dmcu_create(ctx,
12471413 			&dmcu_regs,
12481414 			&dmcu_shift,
....@@ -1262,10 +1428,6 @@
12621428 		BREAK_TO_DEBUGGER();
12631429 		goto res_create_fail;
12641430 	}
1265
-
1266
-	if (dm_pp_get_static_clocks(ctx, &static_clk_info))
1267
-		pool->base.dccg->max_clks_state =
1268
-					static_clk_info.max_clocks_state;
12691431 
12701432 	{
12711433 		struct irq_service_init_data init_data;
....@@ -1313,7 +1475,35 @@
13131475 		}
13141476 	}
13151477 
1478
+	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1479
+		pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
1480
+		if (pool->base.engines[i] == NULL) {
1481
+			BREAK_TO_DEBUGGER();
1482
+			dm_error(
1483
+				"DC:failed to create aux engine!!\n");
1484
+			goto res_create_fail;
1485
+		}
1486
+		pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);
1487
+		if (pool->base.hw_i2cs[i] == NULL) {
1488
+			BREAK_TO_DEBUGGER();
1489
+			dm_error(
1490
+				"DC:failed to create i2c engine!!\n");
1491
+			goto res_create_fail;
1492
+		}
1493
+		pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx);
1494
+		if (pool->base.sw_i2cs[i] == NULL) {
1495
+			BREAK_TO_DEBUGGER();
1496
+			dm_error(
1497
+				"DC:failed to create sw i2c!!\n");
1498
+			goto res_create_fail;
1499
+		}
1500
+	}
1501
+
13161502 	dc->caps.max_planes =  pool->base.pipe_count;
1503
+
1504
+	for (i = 0; i < dc->caps.max_planes; ++i)
1505
+		dc->caps.planes[i] = plane_cap;
1506
+
13171507 	dc->caps.disable_dp_clk_share = true;
13181508 
13191509 	if (!resource_construct(num_virtual_links, dc, &pool->base,
....@@ -1326,7 +1516,7 @@
13261516 	return true;
13271517 
13281518 res_create_fail:
1329
-	destruct(pool);
1519
+	dce80_resource_destruct(pool);
13301520 	return false;
13311521 }
13321522