forked from ~ljy/RK356X_SDK_RELEASE
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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
....@@ -23,6 +23,8 @@
2323  *
2424  */
2525 
26
+#include <linux/slab.h>
27
+
2628 #include "dm_services.h"
2729 
2830 #include "link_encoder.h"
....@@ -34,7 +36,6 @@
3436 #include "dce110/dce110_timing_generator.h"
3537 
3638 #include "irq/dce110/irq_service_dce110.h"
37
-
3839 #include "dce/dce_mem_input.h"
3940 #include "dce/dce_transform.h"
4041 #include "dce/dce_link_encoder.h"
....@@ -42,7 +43,6 @@
4243 #include "dce/dce_audio.h"
4344 #include "dce/dce_opp.h"
4445 #include "dce/dce_ipp.h"
45
-#include "dce/dce_clocks.h"
4646 #include "dce/dce_clock_source.h"
4747 
4848 #include "dce/dce_hwseq.h"
....@@ -50,6 +50,8 @@
5050 #include "dce/dce_abm.h"
5151 #include "dce/dce_dmcu.h"
5252 #include "dce/dce_aux.h"
53
+#include "dce/dce_i2c.h"
54
+#include "dce/dce_panel_cntl.h"
5355 
5456 #include "reg_helper.h"
5557 
....@@ -75,6 +77,7 @@
7577 
7678 #ifndef mmBIOS_SCRATCH_2
7779 	#define mmBIOS_SCRATCH_2 0x05CB
80
+	#define mmBIOS_SCRATCH_3 0x05CC
7881 	#define mmBIOS_SCRATCH_6 0x05CF
7982 #endif
8083 
....@@ -146,19 +149,6 @@
146149 #define SRI(reg_name, block, id)\
147150 	.reg_name = mm ## block ## id ## _ ## reg_name
148151 
149
-
150
-static const struct dccg_registers disp_clk_regs = {
151
-		CLK_COMMON_REG_LIST_DCE_BASE()
152
-};
153
-
154
-static const struct dccg_shift disp_clk_shift = {
155
-		CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
156
-};
157
-
158
-static const struct dccg_mask disp_clk_mask = {
159
-		CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
160
-};
161
-
162152 static const struct dce_dmcu_registers dmcu_regs = {
163153 		DMCU_DCE110_COMMON_REG_LIST()
164154 };
....@@ -181,6 +171,14 @@
181171 
182172 static const struct dce_abm_mask abm_mask = {
183173 		ABM_MASK_SH_LIST_DCE110(_MASK)
174
+};
175
+
176
+static const struct dce110_aux_registers_shift aux_shift = {
177
+	DCE_AUX_MASK_SH_LIST(__SHIFT)
178
+};
179
+
180
+static const struct dce110_aux_registers_mask aux_mask = {
181
+	DCE_AUX_MASK_SH_LIST(_MASK)
184182 };
185183 
186184 #define ipp_regs(id)\
....@@ -239,6 +237,18 @@
239237 		aux_regs(3),
240238 		aux_regs(4),
241239 		aux_regs(5)
240
+};
241
+
242
+static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
243
+	{ DCE_PANEL_CNTL_REG_LIST() }
244
+};
245
+
246
+static const struct dce_panel_cntl_shift panel_cntl_shift = {
247
+	DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
248
+};
249
+
250
+static const struct dce_panel_cntl_mask panel_cntl_mask = {
251
+	DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
242252 };
243253 
244254 #define hpd_regs(id)\
....@@ -348,7 +358,7 @@
348358 		AUD_COMMON_MASK_SH_LIST(__SHIFT)
349359 };
350360 
351
-static const struct dce_aduio_mask audio_mask = {
361
+static const struct dce_audio_mask audio_mask = {
352362 		AUD_COMMON_MASK_SH_LIST(_MASK)
353363 };
354364 
....@@ -375,6 +385,7 @@
375385 };
376386 
377387 static const struct bios_registers bios_regs = {
388
+	.BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
378389 	.BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
379390 };
380391 
....@@ -383,6 +394,7 @@
383394 		.num_audio = 6,
384395 		.num_stream_encoder = 6,
385396 		.num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
397
+		.num_ddc = 6,
386398 };
387399 
388400 static const struct resource_caps polaris_11_resource_cap = {
....@@ -390,6 +402,31 @@
390402 		.num_audio = 5,
391403 		.num_stream_encoder = 5,
392404 		.num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
405
+		.num_ddc = 5,
406
+};
407
+
408
+static const struct dc_plane_cap plane_cap = {
409
+	.type = DC_PLANE_TYPE_DCE_RGB,
410
+
411
+	.pixel_format_support = {
412
+			.argb8888 = true,
413
+			.nv12 = false,
414
+			.fp16 = true
415
+	},
416
+
417
+	.max_upscale_factor = {
418
+			.argb8888 = 16000,
419
+			.nv12 = 1,
420
+			.fp16 = 1
421
+	},
422
+
423
+	.max_downscale_factor = {
424
+			.argb8888 = 250,
425
+			.nv12 = 1,
426
+			.fp16 = 1
427
+	},
428
+	64,
429
+	64
393430 };
394431 
395432 #define CTX  ctx
....@@ -402,6 +439,37 @@
402439 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
403440 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
404441 #endif
442
+
443
+static int map_transmitter_id_to_phy_instance(
444
+	enum transmitter transmitter)
445
+{
446
+	switch (transmitter) {
447
+	case TRANSMITTER_UNIPHY_A:
448
+		return 0;
449
+	break;
450
+	case TRANSMITTER_UNIPHY_B:
451
+		return 1;
452
+	break;
453
+	case TRANSMITTER_UNIPHY_C:
454
+		return 2;
455
+	break;
456
+	case TRANSMITTER_UNIPHY_D:
457
+		return 3;
458
+	break;
459
+	case TRANSMITTER_UNIPHY_E:
460
+		return 4;
461
+	break;
462
+	case TRANSMITTER_UNIPHY_F:
463
+		return 5;
464
+	break;
465
+	case TRANSMITTER_UNIPHY_G:
466
+		return 6;
467
+	break;
468
+	default:
469
+		ASSERT(0);
470
+		return 0;
471
+	}
472
+}
405473 
406474 static void read_dce_straps(
407475 	struct dc_context *ctx,
....@@ -548,12 +616,12 @@
548616 static const struct encoder_feature_support link_enc_feature = {
549617 		.max_hdmi_deep_color = COLOR_DEPTH_121212,
550618 		.max_hdmi_pixel_clock = 600000,
551
-		.ycbcr420_supported = true,
619
+		.hdmi_ycbcr420_supported = true,
620
+		.dp_ycbcr420_supported = false,
552621 		.flags.bits.IS_HBR2_CAPABLE = true,
553622 		.flags.bits.IS_HBR3_CAPABLE = true,
554623 		.flags.bits.IS_TPS3_CAPABLE = true,
555
-		.flags.bits.IS_TPS4_CAPABLE = true,
556
-		.flags.bits.IS_YCBCR_CAPABLE = true
624
+		.flags.bits.IS_TPS4_CAPABLE = true
557625 };
558626 
559627 struct link_encoder *dce112_link_encoder_create(
....@@ -561,17 +629,38 @@
561629 {
562630 	struct dce110_link_encoder *enc110 =
563631 		kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
632
+	int link_regs_id;
564633 
565634 	if (!enc110)
566635 		return NULL;
567636 
637
+	link_regs_id =
638
+		map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
639
+
568640 	dce110_link_encoder_construct(enc110,
569641 				      enc_init_data,
570642 				      &link_enc_feature,
571
-				      &link_enc_regs[enc_init_data->transmitter],
643
+				      &link_enc_regs[link_regs_id],
572644 				      &link_enc_aux_regs[enc_init_data->channel - 1],
573645 				      &link_enc_hpd_regs[enc_init_data->hpd_source]);
574646 	return &enc110->base;
647
+}
648
+
649
+static struct panel_cntl *dce112_panel_cntl_create(const struct panel_cntl_init_data *init_data)
650
+{
651
+	struct dce_panel_cntl *panel_cntl =
652
+		kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
653
+
654
+	if (!panel_cntl)
655
+		return NULL;
656
+
657
+	dce_panel_cntl_construct(panel_cntl,
658
+			init_data,
659
+			&panel_cntl_regs[init_data->inst],
660
+			&panel_cntl_shift,
661
+			&panel_cntl_mask);
662
+
663
+	return &panel_cntl->base;
575664 }
576665 
577666 static struct input_pixel_processor *dce112_ipp_create(
....@@ -604,7 +693,7 @@
604693 	return &opp->base;
605694 }
606695 
607
-struct aux_engine *dce112_aux_engine_create(
696
+struct dce_aux *dce112_aux_engine_create(
608697 	struct dc_context *ctx,
609698 	uint32_t inst)
610699 {
....@@ -616,11 +705,47 @@
616705 
617706 	dce110_aux_engine_construct(aux_engine, ctx, inst,
618707 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
619
-				    &aux_engine_regs[inst]);
708
+				    &aux_engine_regs[inst],
709
+					&aux_mask,
710
+					&aux_shift,
711
+					ctx->dc->caps.extended_aux_timeout_support);
620712 
621713 	return &aux_engine->base;
622714 }
715
+#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
623716 
717
+static const struct dce_i2c_registers i2c_hw_regs[] = {
718
+		i2c_inst_regs(1),
719
+		i2c_inst_regs(2),
720
+		i2c_inst_regs(3),
721
+		i2c_inst_regs(4),
722
+		i2c_inst_regs(5),
723
+		i2c_inst_regs(6),
724
+};
725
+
726
+static const struct dce_i2c_shift i2c_shifts = {
727
+		I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
728
+};
729
+
730
+static const struct dce_i2c_mask i2c_masks = {
731
+		I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
732
+};
733
+
734
+struct dce_i2c_hw *dce112_i2c_hw_create(
735
+	struct dc_context *ctx,
736
+	uint32_t inst)
737
+{
738
+	struct dce_i2c_hw *dce_i2c_hw =
739
+		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
740
+
741
+	if (!dce_i2c_hw)
742
+		return NULL;
743
+
744
+	dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst,
745
+				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
746
+
747
+	return dce_i2c_hw;
748
+}
624749 struct clock_source *dce112_clock_source_create(
625750 	struct dc_context *ctx,
626751 	struct dc_bios *bios,
....@@ -634,12 +759,13 @@
634759 	if (!clk_src)
635760 		return NULL;
636761 
637
-	if (dce110_clk_src_construct(clk_src, ctx, bios, id,
762
+	if (dce112_clk_src_construct(clk_src, ctx, bios, id,
638763 			regs, &cs_shift, &cs_mask)) {
639764 		clk_src->base.dp_clk_src = dp_clk_src;
640765 		return &clk_src->base;
641766 	}
642767 
768
+	kfree(clk_src);
643769 	BREAK_TO_DEBUGGER();
644770 	return NULL;
645771 }
....@@ -650,16 +776,13 @@
650776 	*clk_src = NULL;
651777 }
652778 
653
-static void destruct(struct dce110_resource_pool *pool)
779
+static void dce112_resource_destruct(struct dce110_resource_pool *pool)
654780 {
655781 	unsigned int i;
656782 
657783 	for (i = 0; i < pool->base.pipe_count; i++) {
658784 		if (pool->base.opps[i] != NULL)
659785 			dce110_opp_destroy(&pool->base.opps[i]);
660
-
661
-		if (pool->base.engines[i] != NULL)
662
-			dce110_engine_destroy(&pool->base.engines[i]);
663786 
664787 		if (pool->base.transforms[i] != NULL)
665788 			dce112_transform_destroy(&pool->base.transforms[i]);
....@@ -676,7 +799,19 @@
676799 			kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
677800 			pool->base.timing_generators[i] = NULL;
678801 		}
802
+	}
679803 
804
+	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
805
+		if (pool->base.engines[i] != NULL)
806
+			dce110_engine_destroy(&pool->base.engines[i]);
807
+		if (pool->base.hw_i2cs[i] != NULL) {
808
+			kfree(pool->base.hw_i2cs[i]);
809
+			pool->base.hw_i2cs[i] = NULL;
810
+		}
811
+		if (pool->base.sw_i2cs[i] != NULL) {
812
+			kfree(pool->base.sw_i2cs[i]);
813
+			pool->base.sw_i2cs[i] = NULL;
814
+		}
680815 	}
681816 
682817 	for (i = 0; i < pool->base.stream_enc_count; i++) {
....@@ -705,9 +840,6 @@
705840 	if (pool->base.dmcu != NULL)
706841 		dce_dmcu_destroy(&pool->base.dmcu);
707842 
708
-	if (pool->base.dccg != NULL)
709
-		dce_dccg_destroy(&pool->base.dccg);
710
-
711843 	if (pool->base.irqs != NULL) {
712844 		dal_irq_service_destroy(&pool->base.irqs);
713845 	}
....@@ -718,7 +850,7 @@
718850 		const struct resource_pool *pool,
719851 		const struct dc_stream_state *const stream)
720852 {
721
-	switch (stream->sink->link->link_enc->transmitter) {
853
+	switch (stream->link->link_enc->transmitter) {
722854 	case TRANSMITTER_UNIPHY_A:
723855 		return pool->clock_sources[DCE112_CLK_SRC_PLL0];
724856 	case TRANSMITTER_UNIPHY_B:
....@@ -757,7 +889,8 @@
757889 
758890 bool dce112_validate_bandwidth(
759891 	struct dc *dc,
760
-	struct dc_state *context)
892
+	struct dc_state *context,
893
+	bool fast_validate)
761894 {
762895 	bool result = false;
763896 
....@@ -771,7 +904,7 @@
771904 			dc->bw_vbios,
772905 			context->res_ctx.pipe_ctx,
773906 			dc->res_pool->pipe_count,
774
-			&context->bw.dce))
907
+			&context->bw_ctx.bw.dce))
775908 		result = true;
776909 
777910 	if (!result)
....@@ -779,8 +912,8 @@
779912 			"%s: Bandwidth validation failed!",
780913 			__func__);
781914 
782
-	if (memcmp(&dc->current_state->bw.dce,
783
-			&context->bw.dce, sizeof(context->bw.dce))) {
915
+	if (memcmp(&dc->current_state->bw_ctx.bw.dce,
916
+			&context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) {
784917 
785918 		DC_LOG_BANDWIDTH_CALCS(
786919 			"%s: finish,\n"
....@@ -794,34 +927,34 @@
794927 			"sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n"
795928 			,
796929 			__func__,
797
-			context->bw.dce.nbp_state_change_wm_ns[0].b_mark,
798
-			context->bw.dce.nbp_state_change_wm_ns[0].a_mark,
799
-			context->bw.dce.urgent_wm_ns[0].b_mark,
800
-			context->bw.dce.urgent_wm_ns[0].a_mark,
801
-			context->bw.dce.stutter_exit_wm_ns[0].b_mark,
802
-			context->bw.dce.stutter_exit_wm_ns[0].a_mark,
803
-			context->bw.dce.nbp_state_change_wm_ns[1].b_mark,
804
-			context->bw.dce.nbp_state_change_wm_ns[1].a_mark,
805
-			context->bw.dce.urgent_wm_ns[1].b_mark,
806
-			context->bw.dce.urgent_wm_ns[1].a_mark,
807
-			context->bw.dce.stutter_exit_wm_ns[1].b_mark,
808
-			context->bw.dce.stutter_exit_wm_ns[1].a_mark,
809
-			context->bw.dce.nbp_state_change_wm_ns[2].b_mark,
810
-			context->bw.dce.nbp_state_change_wm_ns[2].a_mark,
811
-			context->bw.dce.urgent_wm_ns[2].b_mark,
812
-			context->bw.dce.urgent_wm_ns[2].a_mark,
813
-			context->bw.dce.stutter_exit_wm_ns[2].b_mark,
814
-			context->bw.dce.stutter_exit_wm_ns[2].a_mark,
815
-			context->bw.dce.stutter_mode_enable,
816
-			context->bw.dce.cpuc_state_change_enable,
817
-			context->bw.dce.cpup_state_change_enable,
818
-			context->bw.dce.nbp_state_change_enable,
819
-			context->bw.dce.all_displays_in_sync,
820
-			context->bw.dce.dispclk_khz,
821
-			context->bw.dce.sclk_khz,
822
-			context->bw.dce.sclk_deep_sleep_khz,
823
-			context->bw.dce.yclk_khz,
824
-			context->bw.dce.blackout_recovery_time_us);
930
+			context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark,
931
+			context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark,
932
+			context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark,
933
+			context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark,
934
+			context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark,
935
+			context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark,
936
+			context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].b_mark,
937
+			context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].a_mark,
938
+			context->bw_ctx.bw.dce.urgent_wm_ns[1].b_mark,
939
+			context->bw_ctx.bw.dce.urgent_wm_ns[1].a_mark,
940
+			context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].b_mark,
941
+			context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].a_mark,
942
+			context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].b_mark,
943
+			context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].a_mark,
944
+			context->bw_ctx.bw.dce.urgent_wm_ns[2].b_mark,
945
+			context->bw_ctx.bw.dce.urgent_wm_ns[2].a_mark,
946
+			context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].b_mark,
947
+			context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].a_mark,
948
+			context->bw_ctx.bw.dce.stutter_mode_enable,
949
+			context->bw_ctx.bw.dce.cpuc_state_change_enable,
950
+			context->bw_ctx.bw.dce.cpup_state_change_enable,
951
+			context->bw_ctx.bw.dce.nbp_state_change_enable,
952
+			context->bw_ctx.bw.dce.all_displays_in_sync,
953
+			context->bw_ctx.bw.dce.dispclk_khz,
954
+			context->bw_ctx.bw.dce.sclk_khz,
955
+			context->bw_ctx.bw.dce.sclk_deep_sleep_khz,
956
+			context->bw_ctx.bw.dce.yclk_khz,
957
+			context->bw_ctx.bw.dce.blackout_recovery_time_us);
825958 	}
826959 	return result;
827960 }
....@@ -840,7 +973,7 @@
840973 		return DC_ERROR_UNEXPECTED;
841974 
842975 	if (dc_is_dp_signal(pipe_ctx->stream->signal)
843
-		|| pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
976
+		|| dc_is_virtual_signal(pipe_ctx->stream->signal))
844977 		pipe_ctx->clock_source =
845978 				dc->res_pool->dp_clock_source;
846979 	else
....@@ -884,7 +1017,7 @@
8841017 		struct dc_state *new_ctx,
8851018 		struct dc_stream_state *dc_stream)
8861019 {
887
-	enum dc_status result = DC_ERROR_UNEXPECTED;
1020
+	enum dc_status result;
8881021 
8891022 	result = resource_map_pool_resources(dc, new_ctx, dc_stream);
8901023 
....@@ -912,7 +1045,7 @@
9121045 {
9131046 	struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
9141047 
915
-	destruct(dce110_pool);
1048
+	dce112_resource_destruct(dce110_pool);
9161049 	kfree(dce110_pool);
9171050 	*pool = NULL;
9181051 }
....@@ -920,10 +1053,12 @@
9201053 static const struct resource_funcs dce112_res_pool_funcs = {
9211054 	.destroy = dce112_destroy_resource_pool,
9221055 	.link_enc_create = dce112_link_encoder_create,
1056
+	.panel_cntl_create = dce112_panel_cntl_create,
9231057 	.validate_bandwidth = dce112_validate_bandwidth,
9241058 	.validate_plane = dce100_validate_plane,
9251059 	.add_stream_to_ctx = dce112_add_stream_to_ctx,
926
-	.validate_global = dce112_validate_global
1060
+	.validate_global = dce112_validate_global,
1061
+	.find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link
9271062 };
9281063 
9291064 static void bw_calcs_data_update_from_pplib(struct dc *dc)
....@@ -932,6 +1067,10 @@
9321067 	struct dm_pp_clock_levels_with_latency mem_clks = {0};
9331068 	struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0};
9341069 	struct dm_pp_clock_levels clks = {0};
1070
+	int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ;
1071
+
1072
+	if (dc->bw_vbios && dc->bw_vbios->memory_type == bw_def_hbm)
1073
+		memory_type_multiplier = MEMORY_TYPE_HBM;
9351074 
9361075 	/*do system clock  TODO PPLIB: after PPLIB implement,
9371076 	 * then remove old way
....@@ -971,12 +1110,12 @@
9711110 				&clks);
9721111 
9731112 		dc->bw_vbios->low_yclk = bw_frc_to_fixed(
974
-			clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER, 1000);
1113
+			clks.clocks_in_khz[0] * memory_type_multiplier, 1000);
9751114 		dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
976
-			clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER,
1115
+			clks.clocks_in_khz[clks.num_levels>>1] * memory_type_multiplier,
9771116 			1000);
9781117 		dc->bw_vbios->high_yclk = bw_frc_to_fixed(
979
-			clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER,
1118
+			clks.clocks_in_khz[clks.num_levels-1] * memory_type_multiplier,
9801119 			1000);
9811120 
9821121 		return;
....@@ -1012,12 +1151,12 @@
10121151 	 * YCLK = UMACLK*m_memoryTypeMultiplier
10131152 	 */
10141153 	dc->bw_vbios->low_yclk = bw_frc_to_fixed(
1015
-		mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000);
1154
+		mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000);
10161155 	dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
1017
-		mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER,
1156
+		mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * memory_type_multiplier,
10181157 		1000);
10191158 	dc->bw_vbios->high_yclk = bw_frc_to_fixed(
1020
-		mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER,
1159
+		mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier,
10211160 		1000);
10221161 
10231162 	/* Now notify PPLib/SMU about which Watermarks sets they should select
....@@ -1080,14 +1219,13 @@
10801219 		return &polaris_10_resource_cap;
10811220 }
10821221 
1083
-static bool construct(
1222
+static bool dce112_resource_construct(
10841223 	uint8_t num_virtual_links,
10851224 	struct dc *dc,
10861225 	struct dce110_resource_pool *pool)
10871226 {
10881227 	unsigned int i;
10891228 	struct dc_context *ctx = dc->ctx;
1090
-	struct dm_pp_static_clock_info static_clk_info = {0};
10911229 
10921230 	ctx->dc_bios->regs = &bios_regs;
10931231 
....@@ -1104,7 +1242,7 @@
11041242 	dc->caps.i2c_speed_in_khz = 100;
11051243 	dc->caps.max_cursor_size = 128;
11061244 	dc->caps.dual_link_dvi = true;
1107
-
1245
+	dc->caps.extended_aux_timeout_support = false;
11081246 
11091247 	/*************************************************
11101248 	 *  Create resources                             *
....@@ -1155,16 +1293,6 @@
11551293 		}
11561294 	}
11571295 
1158
-	pool->base.dccg = dce112_dccg_create(ctx,
1159
-			&disp_clk_regs,
1160
-			&disp_clk_shift,
1161
-			&disp_clk_mask);
1162
-	if (pool->base.dccg == NULL) {
1163
-		dm_error("DC: failed to create display clock!\n");
1164
-		BREAK_TO_DEBUGGER();
1165
-		goto res_create_fail;
1166
-	}
1167
-
11681296 	pool->base.dmcu = dce_dmcu_create(ctx,
11691297 			&dmcu_regs,
11701298 			&dmcu_shift,
....@@ -1184,13 +1312,6 @@
11841312 		BREAK_TO_DEBUGGER();
11851313 		goto res_create_fail;
11861314 	}
1187
-
1188
-	/* get static clock information for PPLIB or firmware, save
1189
-	 * max_clock_state
1190
-	 */
1191
-	if (dm_pp_get_static_clocks(ctx, &static_clk_info))
1192
-		pool->base.dccg->max_clks_state =
1193
-				static_clk_info.max_clocks_state;
11941315 
11951316 	{
11961317 		struct irq_service_init_data init_data;
....@@ -1245,6 +1366,9 @@
12451366 				"DC:failed to create output pixel processor!\n");
12461367 			goto res_create_fail;
12471368 		}
1369
+	}
1370
+
1371
+	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
12481372 		pool->base.engines[i] = dce112_aux_engine_create(ctx, i);
12491373 		if (pool->base.engines[i] == NULL) {
12501374 			BREAK_TO_DEBUGGER();
....@@ -1252,6 +1376,14 @@
12521376 				"DC:failed to create aux engine!!\n");
12531377 			goto res_create_fail;
12541378 		}
1379
+		pool->base.hw_i2cs[i] = dce112_i2c_hw_create(ctx, i);
1380
+		if (pool->base.hw_i2cs[i] == NULL) {
1381
+			BREAK_TO_DEBUGGER();
1382
+			dm_error(
1383
+				"DC:failed to create i2c engine!!\n");
1384
+			goto res_create_fail;
1385
+		}
1386
+		pool->base.sw_i2cs[i] = NULL;
12551387 	}
12561388 
12571389 	if (!resource_construct(num_virtual_links, dc, &pool->base,
....@@ -1259,6 +1391,9 @@
12591391 		goto res_create_fail;
12601392 
12611393 	dc->caps.max_planes =  pool->base.pipe_count;
1394
+
1395
+	for (i = 0; i < dc->caps.max_planes; ++i)
1396
+		dc->caps.planes[i] = plane_cap;
12621397 
12631398 	/* Create hardware sequencer */
12641399 	dce112_hw_sequencer_construct(dc);
....@@ -1270,7 +1405,7 @@
12701405 	return true;
12711406 
12721407 res_create_fail:
1273
-	destruct(pool);
1408
+	dce112_resource_destruct(pool);
12741409 	return false;
12751410 }
12761411 
....@@ -1284,7 +1419,7 @@
12841419 	if (!pool)
12851420 		return NULL;
12861421 
1287
-	if (construct(num_virtual_links, dc, pool))
1422
+	if (dce112_resource_construct(num_virtual_links, dc, pool))
12881423 		return &pool->base;
12891424 
12901425 	kfree(pool);