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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
....@@ -22,6 +22,9 @@
2222  * Authors: AMD
2323  *
2424  */
25
+
26
+#include <linux/slab.h>
27
+
2528 #include "dm_services.h"
2629 
2730 #include "link_encoder.h"
....@@ -35,16 +38,15 @@
3538 #include "irq/dce110/irq_service_dce110.h"
3639 #include "dce/dce_link_encoder.h"
3740 #include "dce/dce_stream_encoder.h"
38
-
3941 #include "dce/dce_mem_input.h"
4042 #include "dce/dce_ipp.h"
4143 #include "dce/dce_transform.h"
4244 #include "dce/dce_opp.h"
43
-#include "dce/dce_clocks.h"
4445 #include "dce/dce_clock_source.h"
4546 #include "dce/dce_audio.h"
4647 #include "dce/dce_hwseq.h"
4748 #include "dce100/dce100_hw_sequencer.h"
49
+#include "dce/dce_panel_cntl.h"
4850 
4951 #include "reg_helper.h"
5052 
....@@ -54,6 +56,7 @@
5456 #include "dce/dce_dmcu.h"
5557 #include "dce/dce_aux.h"
5658 #include "dce/dce_abm.h"
59
+#include "dce/dce_i2c.h"
5760 
5861 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
5962 #include "gmc/gmc_8_2_d.h"
....@@ -75,6 +78,7 @@
7578 
7679 #ifndef mmBIOS_SCRATCH_2
7780 	#define mmBIOS_SCRATCH_2 0x05CB
81
+	#define mmBIOS_SCRATCH_3 0x05CC
7882 	#define mmBIOS_SCRATCH_6 0x05CF
7983 #endif
8084 
....@@ -134,19 +138,6 @@
134138 /* set register offset with instance */
135139 #define SRI(reg_name, block, id)\
136140 	.reg_name = mm ## block ## id ## _ ## reg_name
137
-
138
-
139
-static const struct dccg_registers disp_clk_regs = {
140
-		CLK_COMMON_REG_LIST_DCE_BASE()
141
-};
142
-
143
-static const struct dccg_shift disp_clk_shift = {
144
-		CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
145
-};
146
-
147
-static const struct dccg_mask disp_clk_mask = {
148
-		CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
149
-};
150141 
151142 #define ipp_regs(id)\
152143 [id] = {\
....@@ -259,6 +250,18 @@
259250 		SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
260251 };
261252 
253
+static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
254
+	{ DCE_PANEL_CNTL_REG_LIST() }
255
+};
256
+
257
+static const struct dce_panel_cntl_shift panel_cntl_shift = {
258
+	DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
259
+};
260
+
261
+static const struct dce_panel_cntl_mask panel_cntl_mask = {
262
+	DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
263
+};
264
+
262265 #define opp_regs(id)\
263266 [id] = {\
264267 	OPP_DCE_100_REG_LIST(id),\
....@@ -314,7 +317,7 @@
314317 		AUD_COMMON_MASK_SH_LIST(__SHIFT)
315318 };
316319 
317
-static const struct dce_aduio_mask audio_mask = {
320
+static const struct dce_audio_mask audio_mask = {
318321 		AUD_COMMON_MASK_SH_LIST(_MASK)
319322 };
320323 
....@@ -364,6 +367,7 @@
364367 #define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03
365368 
366369 static const struct bios_registers bios_regs = {
370
+	.BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
367371 	.BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
368372 };
369373 
....@@ -371,7 +375,30 @@
371375 	.num_timing_generator = 6,
372376 	.num_audio = 6,
373377 	.num_stream_encoder = 6,
374
-	.num_pll = 3
378
+	.num_pll = 3,
379
+	.num_ddc = 6,
380
+};
381
+
382
+static const struct dc_plane_cap plane_cap = {
383
+	.type = DC_PLANE_TYPE_DCE_RGB,
384
+
385
+	.pixel_format_support = {
386
+			.argb8888 = true,
387
+			.nv12 = false,
388
+			.fp16 = false
389
+	},
390
+
391
+	.max_upscale_factor = {
392
+			.argb8888 = 16000,
393
+			.nv12 = 1,
394
+			.fp16 = 1
395
+	},
396
+
397
+	.max_downscale_factor = {
398
+			.argb8888 = 250,
399
+			.nv12 = 1,
400
+			.fp16 = 1
401
+	}
375402 };
376403 
377404 #define CTX  ctx
....@@ -384,6 +411,37 @@
384411 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
385412 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
386413 #endif
414
+
415
+static int map_transmitter_id_to_phy_instance(
416
+	enum transmitter transmitter)
417
+{
418
+	switch (transmitter) {
419
+	case TRANSMITTER_UNIPHY_A:
420
+		return 0;
421
+	break;
422
+	case TRANSMITTER_UNIPHY_B:
423
+		return 1;
424
+	break;
425
+	case TRANSMITTER_UNIPHY_C:
426
+		return 2;
427
+	break;
428
+	case TRANSMITTER_UNIPHY_D:
429
+		return 3;
430
+	break;
431
+	case TRANSMITTER_UNIPHY_E:
432
+		return 4;
433
+	break;
434
+	case TRANSMITTER_UNIPHY_F:
435
+		return 5;
436
+	break;
437
+	case TRANSMITTER_UNIPHY_G:
438
+		return 6;
439
+	break;
440
+	default:
441
+		ASSERT(0);
442
+		return 0;
443
+	}
444
+}
387445 
388446 static void read_dce_straps(
389447 	struct dc_context *ctx,
....@@ -492,6 +550,14 @@
492550 		.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
493551 };
494552 
553
+static const struct dce110_aux_registers_shift aux_shift = {
554
+	DCE10_AUX_MASK_SH_LIST(__SHIFT)
555
+};
556
+
557
+static const struct dce110_aux_registers_mask aux_mask = {
558
+	DCE10_AUX_MASK_SH_LIST(_MASK)
559
+};
560
+
495561 static struct mem_input *dce100_mem_input_create(
496562 	struct dc_context *ctx,
497563 	uint32_t inst)
....@@ -549,8 +615,7 @@
549615 		.max_hdmi_deep_color = COLOR_DEPTH_121212,
550616 		.max_hdmi_pixel_clock = 300000,
551617 		.flags.bits.IS_HBR2_CAPABLE = true,
552
-		.flags.bits.IS_TPS3_CAPABLE = true,
553
-		.flags.bits.IS_YCBCR_CAPABLE = true
618
+		.flags.bits.IS_TPS3_CAPABLE = true
554619 };
555620 
556621 struct link_encoder *dce100_link_encoder_create(
....@@ -558,17 +623,38 @@
558623 {
559624 	struct dce110_link_encoder *enc110 =
560625 		kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
626
+	int link_regs_id;
561627 
562628 	if (!enc110)
563629 		return NULL;
564630 
631
+	link_regs_id =
632
+		map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
633
+
565634 	dce110_link_encoder_construct(enc110,
566635 				      enc_init_data,
567636 				      &link_enc_feature,
568
-				      &link_enc_regs[enc_init_data->transmitter],
637
+				      &link_enc_regs[link_regs_id],
569638 				      &link_enc_aux_regs[enc_init_data->channel - 1],
570639 				      &link_enc_hpd_regs[enc_init_data->hpd_source]);
571640 	return &enc110->base;
641
+}
642
+
643
+static struct panel_cntl *dce100_panel_cntl_create(const struct panel_cntl_init_data *init_data)
644
+{
645
+	struct dce_panel_cntl *panel_cntl =
646
+		kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
647
+
648
+	if (!panel_cntl)
649
+		return NULL;
650
+
651
+	dce_panel_cntl_construct(panel_cntl,
652
+			init_data,
653
+			&panel_cntl_regs[init_data->inst],
654
+			&panel_cntl_shift,
655
+			&panel_cntl_mask);
656
+
657
+	return &panel_cntl->base;
572658 }
573659 
574660 struct output_pixel_processor *dce100_opp_create(
....@@ -586,7 +672,7 @@
586672 	return &opp->base;
587673 }
588674 
589
-struct aux_engine *dce100_aux_engine_create(
675
+struct dce_aux *dce100_aux_engine_create(
590676 	struct dc_context *ctx,
591677 	uint32_t inst)
592678 {
....@@ -598,11 +684,47 @@
598684 
599685 	dce110_aux_engine_construct(aux_engine, ctx, inst,
600686 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
601
-				    &aux_engine_regs[inst]);
687
+				    &aux_engine_regs[inst],
688
+					&aux_mask,
689
+					&aux_shift,
690
+					ctx->dc->caps.extended_aux_timeout_support);
602691 
603692 	return &aux_engine->base;
604693 }
694
+#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
605695 
696
+static const struct dce_i2c_registers i2c_hw_regs[] = {
697
+		i2c_inst_regs(1),
698
+		i2c_inst_regs(2),
699
+		i2c_inst_regs(3),
700
+		i2c_inst_regs(4),
701
+		i2c_inst_regs(5),
702
+		i2c_inst_regs(6),
703
+};
704
+
705
+static const struct dce_i2c_shift i2c_shifts = {
706
+		I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
707
+};
708
+
709
+static const struct dce_i2c_mask i2c_masks = {
710
+		I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
711
+};
712
+
713
+struct dce_i2c_hw *dce100_i2c_hw_create(
714
+	struct dc_context *ctx,
715
+	uint32_t inst)
716
+{
717
+	struct dce_i2c_hw *dce_i2c_hw =
718
+		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
719
+
720
+	if (!dce_i2c_hw)
721
+		return NULL;
722
+
723
+	dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst,
724
+				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
725
+
726
+	return dce_i2c_hw;
727
+}
606728 struct clock_source *dce100_clock_source_create(
607729 	struct dc_context *ctx,
608730 	struct dc_bios *bios,
....@@ -622,6 +744,7 @@
622744 		return &clk_src->base;
623745 	}
624746 
747
+	kfree(clk_src);
625748 	BREAK_TO_DEBUGGER();
626749 	return NULL;
627750 }
....@@ -632,7 +755,7 @@
632755 	*clk_src = NULL;
633756 }
634757 
635
-static void destruct(struct dce110_resource_pool *pool)
758
+static void dce100_resource_destruct(struct dce110_resource_pool *pool)
636759 {
637760 	unsigned int i;
638761 
....@@ -655,10 +778,19 @@
655778 			kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
656779 			pool->base.timing_generators[i] = NULL;
657780 		}
781
+	}
658782 
783
+	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
659784 		if (pool->base.engines[i] != NULL)
660785 			dce110_engine_destroy(&pool->base.engines[i]);
661
-
786
+		if (pool->base.hw_i2cs[i] != NULL) {
787
+			kfree(pool->base.hw_i2cs[i]);
788
+			pool->base.hw_i2cs[i] = NULL;
789
+		}
790
+		if (pool->base.sw_i2cs[i] != NULL) {
791
+			kfree(pool->base.sw_i2cs[i]);
792
+			pool->base.sw_i2cs[i] = NULL;
793
+		}
662794 	}
663795 
664796 	for (i = 0; i < pool->base.stream_enc_count; i++) {
....@@ -678,9 +810,6 @@
678810 		if (pool->base.audios[i] != NULL)
679811 			dce_aud_destroy(&pool->base.audios[i]);
680812 	}
681
-
682
-	if (pool->base.dccg != NULL)
683
-		dce_dccg_destroy(&pool->base.dccg);
684813 
685814 	if (pool->base.abm != NULL)
686815 				dce_abm_destroy(&pool->base.abm);
....@@ -711,7 +840,8 @@
711840 
712841 bool dce100_validate_bandwidth(
713842 	struct dc  *dc,
714
-	struct dc_state *context)
843
+	struct dc_state *context,
844
+	bool fast_validate)
715845 {
716846 	int i;
717847 	bool at_least_one_pipe = false;
....@@ -723,11 +853,11 @@
723853 
724854 	if (at_least_one_pipe) {
725855 		/* TODO implement when needed but for now hardcode max value*/
726
-		context->bw.dce.dispclk_khz = 681000;
727
-		context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER;
856
+		context->bw_ctx.bw.dce.dispclk_khz = 681000;
857
+		context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
728858 	} else {
729
-		context->bw.dce.dispclk_khz = 0;
730
-		context->bw.dce.yclk_khz = 0;
859
+		context->bw_ctx.bw.dce.dispclk_khz = 0;
860
+		context->bw_ctx.bw.dce.yclk_khz = 0;
731861 	}
732862 
733863 	return true;
....@@ -785,7 +915,7 @@
785915 {
786916 	struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
787917 
788
-	destruct(dce110_pool);
918
+	dce100_resource_destruct(dce110_pool);
789919 	kfree(dce110_pool);
790920 	*pool = NULL;
791921 }
....@@ -799,25 +929,66 @@
799929 	return DC_FAIL_SURFACE_VALIDATE;
800930 }
801931 
932
+struct stream_encoder *dce100_find_first_free_match_stream_enc_for_link(
933
+		struct resource_context *res_ctx,
934
+		const struct resource_pool *pool,
935
+		struct dc_stream_state *stream)
936
+{
937
+	int i;
938
+	int j = -1;
939
+	struct dc_link *link = stream->link;
940
+
941
+	for (i = 0; i < pool->stream_enc_count; i++) {
942
+		if (!res_ctx->is_stream_enc_acquired[i] &&
943
+				pool->stream_enc[i]) {
944
+			/* Store first available for MST second display
945
+			 * in daisy chain use case
946
+			 */
947
+			j = i;
948
+			if (pool->stream_enc[i]->id ==
949
+					link->link_enc->preferred_engine)
950
+				return pool->stream_enc[i];
951
+		}
952
+	}
953
+
954
+	/*
955
+	 * below can happen in cases when stream encoder is acquired:
956
+	 * 1) for second MST display in chain, so preferred engine already
957
+	 * acquired;
958
+	 * 2) for another link, which preferred engine already acquired by any
959
+	 * MST configuration.
960
+	 *
961
+	 * If signal is of DP type and preferred engine not found, return last available
962
+	 *
963
+	 * TODO - This is just a patch up and a generic solution is
964
+	 * required for non DP connectors.
965
+	 */
966
+
967
+	if (j >= 0 && link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT)
968
+		return pool->stream_enc[j];
969
+
970
+	return NULL;
971
+}
972
+
802973 static const struct resource_funcs dce100_res_pool_funcs = {
803974 	.destroy = dce100_destroy_resource_pool,
804975 	.link_enc_create = dce100_link_encoder_create,
976
+	.panel_cntl_create = dce100_panel_cntl_create,
805977 	.validate_bandwidth = dce100_validate_bandwidth,
806978 	.validate_plane = dce100_validate_plane,
807979 	.add_stream_to_ctx = dce100_add_stream_to_ctx,
808
-	.validate_global = dce100_validate_global
980
+	.validate_global = dce100_validate_global,
981
+	.find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link
809982 };
810983 
811
-static bool construct(
984
+static bool dce100_resource_construct(
812985 	uint8_t num_virtual_links,
813986 	struct dc  *dc,
814987 	struct dce110_resource_pool *pool)
815988 {
816989 	unsigned int i;
817990 	struct dc_context *ctx = dc->ctx;
818
-	struct dc_firmware_info info;
819991 	struct dc_bios *bp;
820
-	struct dm_pp_static_clock_info static_clk_info = {0};
821992 
822993 	ctx->dc_bios->regs = &bios_regs;
823994 
....@@ -827,8 +998,7 @@
827998 
828999 	bp = ctx->dc_bios;
8291000 
830
-	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
831
-		info.external_clock_source_frequency_for_dp != 0) {
1001
+	if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
8321002 		pool->base.dp_clock_source =
8331003 				dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
8341004 
....@@ -865,16 +1035,6 @@
8651035 		}
8661036 	}
8671037 
868
-	pool->base.dccg = dce_dccg_create(ctx,
869
-			&disp_clk_regs,
870
-			&disp_clk_shift,
871
-			&disp_clk_mask);
872
-	if (pool->base.dccg == NULL) {
873
-		dm_error("DC: failed to create display clock!\n");
874
-		BREAK_TO_DEBUGGER();
875
-		goto res_create_fail;
876
-	}
877
-
8781038 	pool->base.dmcu = dce_dmcu_create(ctx,
8791039 			&dmcu_regs,
8801040 			&dmcu_shift,
....@@ -895,12 +1055,6 @@
8951055 		goto res_create_fail;
8961056 	}
8971057 
898
-	/* get static clock information for PPLIB or firmware, save
899
-	 * max_clock_state
900
-	 */
901
-	if (dm_pp_get_static_clocks(ctx, &static_clk_info))
902
-		pool->base.dccg->max_clks_state =
903
-					static_clk_info.max_clocks_state;
9041058 	{
9051059 		struct irq_service_init_data init_data;
9061060 		init_data.ctx = dc->ctx;
....@@ -920,6 +1074,8 @@
9201074 	dc->caps.max_cursor_size = 128;
9211075 	dc->caps.dual_link_dvi = true;
9221076 	dc->caps.disable_dp_clk_share = true;
1077
+	dc->caps.extended_aux_timeout_support = false;
1078
+
9231079 	for (i = 0; i < pool->base.pipe_count; i++) {
9241080 		pool->base.timing_generators[i] =
9251081 			dce100_timing_generator_create(
....@@ -963,6 +1119,9 @@
9631119 				"DC: failed to create output pixel processor!\n");
9641120 			goto res_create_fail;
9651121 		}
1122
+	}
1123
+
1124
+	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
9661125 		pool->base.engines[i] = dce100_aux_engine_create(ctx, i);
9671126 		if (pool->base.engines[i] == NULL) {
9681127 			BREAK_TO_DEBUGGER();
....@@ -970,9 +1129,20 @@
9701129 				"DC:failed to create aux engine!!\n");
9711130 			goto res_create_fail;
9721131 		}
1132
+		pool->base.hw_i2cs[i] = dce100_i2c_hw_create(ctx, i);
1133
+		if (pool->base.hw_i2cs[i] == NULL) {
1134
+			BREAK_TO_DEBUGGER();
1135
+			dm_error(
1136
+				"DC:failed to create i2c engine!!\n");
1137
+			goto res_create_fail;
1138
+		}
1139
+		pool->base.sw_i2cs[i] = NULL;
9731140 	}
9741141 
9751142 	dc->caps.max_planes =  pool->base.pipe_count;
1143
+
1144
+	for (i = 0; i < dc->caps.max_planes; ++i)
1145
+		dc->caps.planes[i] = plane_cap;
9761146 
9771147 	if (!resource_construct(num_virtual_links, dc, &pool->base,
9781148 			&res_create_funcs))
....@@ -983,7 +1153,7 @@
9831153 	return true;
9841154 
9851155 res_create_fail:
986
-	destruct(pool);
1156
+	dce100_resource_destruct(pool);
9871157 
9881158 	return false;
9891159 }
....@@ -998,7 +1168,7 @@
9981168 	if (!pool)
9991169 		return NULL;
10001170 
1001
-	if (construct(num_virtual_links, dc, pool))
1171
+	if (dce100_resource_construct(num_virtual_links, dc, pool))
10021172 		return &pool->base;
10031173 
10041174 	kfree(pool);