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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/gpu/drm/amd/display/dc/dc_stream.h
....@@ -32,31 +32,126 @@
3232 /*******************************************************************************
3333  * Stream Interfaces
3434  ******************************************************************************/
35
+struct timing_sync_info {
36
+	int group_id;
37
+	int group_size;
38
+	bool master;
39
+};
3540 
3641 struct dc_stream_status {
3742 	int primary_otg_inst;
3843 	int stream_enc_inst;
3944 	int plane_count;
45
+	int audio_inst;
46
+	struct timing_sync_info timing_sync_info;
4047 	struct dc_plane_state *plane_states[MAX_SURFACE_NUM];
48
+};
4149 
42
-	/*
43
-	 * link this stream passes through
50
+// TODO: References to this needs to be removed..
51
+struct freesync_context {
52
+	bool dummy;
53
+};
54
+
55
+enum hubp_dmdata_mode {
56
+	DMDATA_SW_MODE,
57
+	DMDATA_HW_MODE
58
+};
59
+
60
+struct dc_dmdata_attributes {
61
+	/* Specifies whether dynamic meta data will be updated by software
62
+	 * or has to be fetched by hardware (DMA mode)
4463 	 */
45
-	struct dc_link *link;
64
+	enum hubp_dmdata_mode dmdata_mode;
65
+	/* Specifies if current dynamic meta data is to be used only for the current frame */
66
+	bool dmdata_repeat;
67
+	/* Specifies the size of Dynamic Metadata surface in byte.  Size of 0 means no Dynamic metadata is fetched */
68
+	uint32_t dmdata_size;
69
+	/* Specifies if a new dynamic meta data should be fetched for an upcoming frame */
70
+	bool dmdata_updated;
71
+	/* If hardware mode is used, the base address where DMDATA surface is located */
72
+	PHYSICAL_ADDRESS_LOC address;
73
+	/* Specifies whether QOS level will be provided by TTU or it will come from DMDATA_QOS_LEVEL */
74
+	bool dmdata_qos_mode;
75
+	/* If qos_mode = 1, this is the QOS value to be used: */
76
+	uint32_t dmdata_qos_level;
77
+	/* Specifies the value in unit of REFCLK cycles to be added to the
78
+	 * current time to produce the Amortized deadline for Dynamic Metadata chunk request
79
+	 */
80
+	uint32_t dmdata_dl_delta;
81
+	/* An unbounded array of uint32s, represents software dmdata to be loaded */
82
+	uint32_t *dmdata_sw_data;
83
+};
84
+
85
+struct dc_writeback_info {
86
+	bool wb_enabled;
87
+	int dwb_pipe_inst;
88
+	struct dc_dwb_params dwb_params;
89
+	struct mcif_buf_params mcif_buf_params;
90
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
91
+	struct mcif_warmup_params mcif_warmup_params;
92
+	/* the plane that is the input to TOP_MUX for MPCC that is the DWB source */
93
+	struct dc_plane_state *writeback_source_plane;
94
+	/* source MPCC instance.  for use by internally by dc */
95
+	int mpcc_inst;
96
+#endif
97
+};
98
+
99
+struct dc_writeback_update {
100
+	unsigned int num_wb_info;
101
+	struct dc_writeback_info writeback_info[MAX_DWB_PIPES];
102
+};
103
+
104
+enum vertical_interrupt_ref_point {
105
+	START_V_UPDATE = 0,
106
+	START_V_SYNC,
107
+	INVALID_POINT
108
+
109
+	//For now, only v_update interrupt is used.
110
+	//START_V_BLANK,
111
+	//START_V_ACTIVE
112
+};
113
+
114
+struct periodic_interrupt_config {
115
+	enum vertical_interrupt_ref_point ref_point;
116
+	int lines_offset;
117
+};
118
+
119
+union stream_update_flags {
120
+	struct {
121
+		uint32_t scaling:1;
122
+		uint32_t out_tf:1;
123
+		uint32_t out_csc:1;
124
+		uint32_t abm_level:1;
125
+		uint32_t dpms_off:1;
126
+		uint32_t gamut_remap:1;
127
+		uint32_t wb_update:1;
128
+		uint32_t dsc_changed : 1;
129
+	} bits;
130
+
131
+	uint32_t raw;
46132 };
47133 
48134 struct dc_stream_state {
135
+	// sink is deprecated, new code should not reference
136
+	// this pointer
49137 	struct dc_sink *sink;
138
+
139
+	struct dc_link *link;
140
+	struct dc_panel_patch sink_patches;
141
+	union display_content_support content_support;
50142 	struct dc_crtc_timing timing;
51
-	struct dc_crtc_timing_adjust timing_adjust;
52
-	struct vrr_params vrr_params;
143
+	struct dc_crtc_timing_adjust adjust;
144
+	struct dc_info_packet vrr_infopacket;
145
+	struct dc_info_packet vsc_infopacket;
146
+	struct dc_info_packet vsp_infopacket;
53147 
54148 	struct rect src; /* composition area */
55149 	struct rect dst; /* stream addressable area */
56150 
57
-	struct audio_info audio_info;
58
-
151
+	// TODO: References to this needs to be removed..
59152 	struct freesync_context freesync_ctx;
153
+
154
+	struct audio_info audio_info;
60155 
61156 	struct dc_info_packet hdr_static_metadata;
62157 	PHYSICAL_ADDRESS_LOC dmdata_address;
....@@ -71,19 +166,20 @@
71166 
72167 	enum view_3d_format view_format;
73168 
169
+	bool use_vsc_sdp_for_colorimetry;
74170 	bool ignore_msa_timing_param;
75
-
76
-	unsigned long long periodic_fn_vsync_delta;
171
+	bool converter_disable_audio;
172
+	uint8_t qs_bit;
173
+	uint8_t qy_bit;
77174 
78175 	/* TODO: custom INFO packets */
79176 	/* TODO: ABM info (DMCU) */
80
-	/* PSR info */
81
-	unsigned char psr_version;
82177 	/* TODO: CEA VIC */
83178 
84179 	/* DMCU info */
85180 	unsigned int abm_level;
86
-	unsigned int bl_pwm_level;
181
+
182
+	struct periodic_interrupt_config periodic_interrupt;
87183 
88184 	/* from core_stream struct */
89185 	struct dc_context *ctx;
....@@ -96,7 +192,7 @@
96192 	enum signal_type signal;
97193 	bool dpms_off;
98194 
99
-	struct dc_stream_status status;
195
+	void *dm_stream_context;
100196 
101197 	struct dc_cursor_attributes cursor_attributes;
102198 	struct dc_cursor_position cursor_position;
....@@ -107,19 +203,67 @@
107203 
108204 	struct crtc_trigger_info triggered_crtc_reset;
109205 
206
+	/* writeback */
207
+	unsigned int num_wb_info;
208
+	struct dc_writeback_info writeback_info[MAX_DWB_PIPES];
209
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
210
+	const struct dc_transfer_func *func_shaper;
211
+	const struct dc_3dlut *lut3d_func;
212
+#endif
110213 	/* Computed state bits */
111214 	bool mode_changed : 1;
112215 
216
+	/* Output from DC when stream state is committed or altered
217
+	 * DC may only access these values during:
218
+	 * dc_commit_state, dc_commit_state_no_check, dc_commit_streams
219
+	 * values may not change outside of those calls
220
+	 */
221
+	struct {
222
+		// For interrupt management, some hardware instance
223
+		// offsets need to be exposed to DM
224
+		uint8_t otg_offset;
225
+	} out;
226
+
227
+	bool apply_edp_fast_boot_optimization;
228
+	bool apply_seamless_boot_optimization;
229
+
230
+	uint32_t stream_id;
231
+	bool is_dsc_enabled;
232
+	union stream_update_flags update_flags;
113233 };
114234 
235
+#define ABM_LEVEL_IMMEDIATE_DISABLE 255
236
+
115237 struct dc_stream_update {
238
+	struct dc_stream_state *stream;
239
+
116240 	struct rect src;
117241 	struct rect dst;
118242 	struct dc_transfer_func *out_transfer_func;
119243 	struct dc_info_packet *hdr_static_metadata;
120244 	unsigned int *abm_level;
121245 
122
-	unsigned long long *periodic_fn_vsync_delta;
246
+	struct periodic_interrupt_config *periodic_interrupt;
247
+
248
+	struct dc_info_packet *vrr_infopacket;
249
+	struct dc_info_packet *vsc_infopacket;
250
+	struct dc_info_packet *vsp_infopacket;
251
+
252
+	bool *dpms_off;
253
+	bool integer_scaling_update;
254
+
255
+	struct colorspace_transform *gamut_remap;
256
+	enum dc_color_space *output_color_space;
257
+	enum dc_dither_option *dither_option;
258
+
259
+	struct dc_csc_transform *output_csc_transform;
260
+
261
+	struct dc_writeback_update *wb_update;
262
+	struct dc_dsc_config *dsc_config;
263
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
264
+	struct dc_transfer_func *func_shaper;
265
+	struct dc_3dlut *lut3d_func;
266
+#endif
123267 };
124268 
125269 bool dc_is_stream_unchanged(
....@@ -143,7 +287,6 @@
143287 		int surface_count,
144288 		struct dc_stream_state *stream,
145289 		struct dc_stream_update *stream_update,
146
-		struct dc_plane_state **plane_states,
147290 		struct dc_state *state);
148291 /*
149292  * Log the current stream state.
....@@ -152,11 +295,19 @@
152295 
153296 uint8_t dc_get_current_stream_count(struct dc *dc);
154297 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i);
298
+struct dc_stream_state *dc_stream_find_from_link(const struct dc_link *link);
155299 
156300 /*
157301  * Return the current frame counter.
158302  */
159303 uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream);
304
+
305
+/*
306
+ * Send dp sdp message.
307
+ */
308
+bool dc_stream_send_dp_sdp(const struct dc_stream_state *stream,
309
+		const uint8_t *custom_sdp_message,
310
+		unsigned int sdp_message_size);
160311 
161312 /* TODO: Return parsed values rather than direct register read
162313  * This has a dependency on the caller (amdgpu_display_get_crtc_scanoutpos)
....@@ -203,6 +354,28 @@
203354 		int plane_count,
204355 		struct dc_state *context);
205356 
357
+bool dc_stream_add_writeback(struct dc *dc,
358
+		struct dc_stream_state *stream,
359
+		struct dc_writeback_info *wb_info);
360
+
361
+bool dc_stream_remove_writeback(struct dc *dc,
362
+		struct dc_stream_state *stream,
363
+		uint32_t dwb_pipe_inst);
364
+
365
+enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc,
366
+		struct dc_state *state,
367
+		struct dc_stream_state *stream);
368
+
369
+bool dc_stream_warmup_writeback(struct dc *dc,
370
+		int num_dwb,
371
+		struct dc_writeback_info *wb_info);
372
+
373
+bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream);
374
+
375
+bool dc_stream_set_dynamic_metadata(struct dc *dc,
376
+		struct dc_stream_state *stream,
377
+		struct dc_dmdata_attributes *dmdata_attr);
378
+
206379 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream);
207380 
208381 /*
....@@ -223,6 +396,8 @@
223396 	struct dc_stream_state *streams[],
224397 	uint8_t stream_count);
225398 
399
+/* Triggers multi-stream synchronization. */
400
+void dc_trigger_sync(struct dc *dc, struct dc_state *context);
226401 
227402 enum surface_update_type dc_check_update_surfaces_for_stream(
228403 		struct dc *dc,
....@@ -236,13 +411,24 @@
236411  */
237412 struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink);
238413 
239
-void update_stream_signal(struct dc_stream_state *stream);
414
+struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream);
415
+
416
+void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink);
240417 
241418 void dc_stream_retain(struct dc_stream_state *dc_stream);
242419 void dc_stream_release(struct dc_stream_state *dc_stream);
243420 
421
+struct dc_stream_status *dc_stream_get_status_from_state(
422
+	struct dc_state *state,
423
+	struct dc_stream_state *stream);
244424 struct dc_stream_status *dc_stream_get_status(
245425 	struct dc_stream_state *dc_stream);
426
+
427
+#ifndef TRIM_FSFT
428
+bool dc_optimize_timing_for_fsft(
429
+	struct dc_stream_state *pStream,
430
+	unsigned int max_input_rate_in_khz);
431
+#endif
246432 
247433 /*******************************************************************************
248434  * Cursor interfaces - To manages the cursor within a stream
....@@ -258,10 +444,8 @@
258444 
259445 
260446 bool dc_stream_adjust_vmin_vmax(struct dc *dc,
261
-				struct dc_stream_state **stream,
262
-				int num_streams,
263
-				int vmin,
264
-				int vmax);
447
+				struct dc_stream_state *stream,
448
+				struct dc_crtc_timing_adjust *adjust);
265449 
266450 bool dc_stream_get_crtc_position(struct dc *dc,
267451 				 struct dc_stream_state **stream,
....@@ -280,20 +464,22 @@
280464 		       uint32_t *g_y,
281465 		       uint32_t *b_cb);
282466 
283
-void dc_stream_set_static_screen_events(struct dc *dc,
467
+void dc_stream_set_static_screen_params(struct dc *dc,
284468 					struct dc_stream_state **stream,
285469 					int num_streams,
286
-					const struct dc_static_screen_events *events);
470
+					const struct dc_static_screen_params *params);
471
+
472
+void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream,
473
+		enum dc_dynamic_expansion option);
287474 
288475 void dc_stream_set_dither_option(struct dc_stream_state *stream,
289476 				 enum dc_dither_option option);
290477 
478
+bool dc_stream_set_gamut_remap(struct dc *dc,
479
+			       const struct dc_stream_state *stream);
291480 
292
-bool dc_stream_adjust_vmin_vmax(struct dc *dc,
293
-				struct dc_stream_state **stream,
294
-				int num_streams,
295
-				int vmin,
296
-				int vmax);
481
+bool dc_stream_program_csc_matrix(struct dc *dc,
482
+				  struct dc_stream_state *stream);
297483 
298484 bool dc_stream_get_crtc_position(struct dc *dc,
299485 				 struct dc_stream_state **stream,