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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
....@@ -26,8 +26,11 @@
2626 #ifndef __AMDGPU_DM_H__
2727 #define __AMDGPU_DM_H__
2828 
29
-#include <drm/drmP.h>
3029 #include <drm/drm_atomic.h>
30
+#include <drm/drm_connector.h>
31
+#include <drm/drm_crtc.h>
32
+#include <drm/drm_dp_mst_helper.h>
33
+#include <drm/drm_plane.h>
3134 
3235 /*
3336  * This file contains the definition for amdgpu_display_manager
....@@ -40,6 +43,9 @@
4043  */
4144 
4245 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31
46
+
47
+#define AMDGPU_DM_MAX_CRTC 6
48
+
4349 /*
4450 #include "include/amdgpu_dal_power_if.h"
4551 #include "amdgpu_dm_irq.h"
....@@ -47,88 +53,297 @@
4753 
4854 #include "irq_types.h"
4955 #include "signal_types.h"
56
+#include "amdgpu_dm_crc.h"
5057 
5158 /* Forward declarations */
5259 struct amdgpu_device;
5360 struct drm_device;
5461 struct amdgpu_dm_irq_handler_data;
5562 struct dc;
56
-
57
-struct amdgpu_dm_prev_state {
58
-	struct drm_framebuffer *fb;
59
-	int32_t x;
60
-	int32_t y;
61
-	struct drm_display_mode mode;
62
-};
63
+struct amdgpu_bo;
64
+struct dmub_srv;
6365 
6466 struct common_irq_params {
6567 	struct amdgpu_device *adev;
6668 	enum dc_irq_source irq_src;
6769 };
6870 
69
-struct irq_list_head {
70
-	struct list_head head;
71
-	/* In case this interrupt needs post-processing, 'work' will be queued*/
72
-	struct work_struct work;
73
-};
74
-
75
-struct dm_comressor_info {
71
+/**
72
+ * struct dm_compressor_info - Buffer info used by frame buffer compression
73
+ * @cpu_addr: MMIO cpu addr
74
+ * @bo_ptr: Pointer to the buffer object
75
+ * @gpu_addr: MMIO gpu addr
76
+ */
77
+struct dm_compressor_info {
7678 	void *cpu_addr;
7779 	struct amdgpu_bo *bo_ptr;
7880 	uint64_t gpu_addr;
7981 };
8082 
83
+/**
84
+ * struct amdgpu_dm_backlight_caps - Information about backlight
85
+ *
86
+ * Describe the backlight support for ACPI or eDP AUX.
87
+ */
88
+struct amdgpu_dm_backlight_caps {
89
+	/**
90
+	 * @ext_caps: Keep the data struct with all the information about the
91
+	 * display support for HDR.
92
+	 */
93
+	union dpcd_sink_ext_caps *ext_caps;
94
+	/**
95
+	 * @aux_min_input_signal: Min brightness value supported by the display
96
+	 */
97
+	u32 aux_min_input_signal;
98
+	/**
99
+	 * @aux_max_input_signal: Max brightness value supported by the display
100
+	 * in nits.
101
+	 */
102
+	u32 aux_max_input_signal;
103
+	/**
104
+	 * @min_input_signal: minimum possible input in range 0-255.
105
+	 */
106
+	int min_input_signal;
107
+	/**
108
+	 * @max_input_signal: maximum possible input in range 0-255.
109
+	 */
110
+	int max_input_signal;
111
+	/**
112
+	 * @caps_valid: true if these values are from the ACPI interface.
113
+	 */
114
+	bool caps_valid;
115
+	/**
116
+	 * @aux_support: Describes if the display supports AUX backlight.
117
+	 */
118
+	bool aux_support;
119
+};
81120 
121
+/**
122
+ * struct amdgpu_display_manager - Central amdgpu display manager device
123
+ *
124
+ * @dc: Display Core control structure
125
+ * @adev: AMDGPU base driver structure
126
+ * @ddev: DRM base driver structure
127
+ * @display_indexes_num: Max number of display streams supported
128
+ * @irq_handler_list_table_lock: Synchronizes access to IRQ tables
129
+ * @backlight_dev: Backlight control device
130
+ * @backlight_link: Link on which to control backlight
131
+ * @backlight_caps: Capabilities of the backlight device
132
+ * @freesync_module: Module handling freesync calculations
133
+ * @hdcp_workqueue: AMDGPU content protection queue
134
+ * @fw_dmcu: Reference to DMCU firmware
135
+ * @dmcu_fw_version: Version of the DMCU firmware
136
+ * @soc_bounding_box: SOC bounding box values provided by gpu_info FW
137
+ * @cached_state: Caches device atomic state for suspend/resume
138
+ * @cached_dc_state: Cached state of content streams
139
+ * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info
140
+ * @force_timing_sync: set via debugfs. When set, indicates that all connected
141
+ *		       displays will be forced to synchronize.
142
+ */
82143 struct amdgpu_display_manager {
83
-	struct dal *dal;
144
+
84145 	struct dc *dc;
146
+
147
+	/**
148
+	 * @dmub_srv:
149
+	 *
150
+	 * DMUB service, used for controlling the DMUB on hardware
151
+	 * that supports it. The pointer to the dmub_srv will be
152
+	 * NULL on hardware that does not support it.
153
+	 */
154
+	struct dmub_srv *dmub_srv;
155
+
156
+	/**
157
+	 * @dmub_fb_info:
158
+	 *
159
+	 * Framebuffer regions for the DMUB.
160
+	 */
161
+	struct dmub_srv_fb_info *dmub_fb_info;
162
+
163
+	/**
164
+	 * @dmub_fw:
165
+	 *
166
+	 * DMUB firmware, required on hardware that has DMUB support.
167
+	 */
168
+	const struct firmware *dmub_fw;
169
+
170
+	/**
171
+	 * @dmub_bo:
172
+	 *
173
+	 * Buffer object for the DMUB.
174
+	 */
175
+	struct amdgpu_bo *dmub_bo;
176
+
177
+	/**
178
+	 * @dmub_bo_gpu_addr:
179
+	 *
180
+	 * GPU virtual address for the DMUB buffer object.
181
+	 */
182
+	u64 dmub_bo_gpu_addr;
183
+
184
+	/**
185
+	 * @dmub_bo_cpu_addr:
186
+	 *
187
+	 * CPU address for the DMUB buffer object.
188
+	 */
189
+	void *dmub_bo_cpu_addr;
190
+
191
+	/**
192
+	 * @dmcub_fw_version:
193
+	 *
194
+	 * DMCUB firmware version.
195
+	 */
196
+	uint32_t dmcub_fw_version;
197
+
198
+	/**
199
+	 * @cgs_device:
200
+	 *
201
+	 * The Common Graphics Services device. It provides an interface for
202
+	 * accessing registers.
203
+	 */
85204 	struct cgs_device *cgs_device;
86205 
87
-	struct amdgpu_device *adev;	/*AMD base driver*/
88
-	struct drm_device *ddev;	/*DRM base driver*/
206
+	struct amdgpu_device *adev;
207
+	struct drm_device *ddev;
89208 	u16 display_indexes_num;
90209 
91
-	struct amdgpu_dm_prev_state prev_state;
92
-
93
-	/*
94
-	 * 'irq_source_handler_table' holds a list of handlers
95
-	 * per (DAL) IRQ source.
210
+	/**
211
+	 * @atomic_obj:
96212 	 *
97
-	 * Each IRQ source may need to be handled at different contexts.
98
-	 * By 'context' we mean, for example:
99
-	 * - The ISR context, which is the direct interrupt handler.
100
-	 * - The 'deferred' context - this is the post-processing of the
101
-	 *	interrupt, but at a lower priority.
213
+	 * In combination with &dm_atomic_state it helps manage
214
+	 * global atomic state that doesn't map cleanly into existing
215
+	 * drm resources, like &dc_context.
216
+	 */
217
+	struct drm_private_obj atomic_obj;
218
+
219
+	/**
220
+	 * @dc_lock:
221
+	 *
222
+	 * Guards access to DC functions that can issue register write
223
+	 * sequences.
224
+	 */
225
+	struct mutex dc_lock;
226
+
227
+	/**
228
+	 * @audio_lock:
229
+	 *
230
+	 * Guards access to audio instance changes.
231
+	 */
232
+	struct mutex audio_lock;
233
+
234
+	/**
235
+	 * @audio_component:
236
+	 *
237
+	 * Used to notify ELD changes to sound driver.
238
+	 */
239
+	struct drm_audio_component *audio_component;
240
+
241
+	/**
242
+	 * @audio_registered:
243
+	 *
244
+	 * True if the audio component has been registered
245
+	 * successfully, false otherwise.
246
+	 */
247
+	bool audio_registered;
248
+
249
+	/**
250
+	 * @irq_handler_list_low_tab:
251
+	 *
252
+	 * Low priority IRQ handler table.
253
+	 *
254
+	 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ
255
+	 * source. Low priority IRQ handlers are deferred to a workqueue to be
256
+	 * processed. Hence, they can sleep.
102257 	 *
103258 	 * Note that handlers are called in the same order as they were
104259 	 * registered (FIFO).
105260 	 */
106
-	struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];
261
+	struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];
262
+
263
+	/**
264
+	 * @irq_handler_list_high_tab:
265
+	 *
266
+	 * High priority IRQ handler table.
267
+	 *
268
+	 * It is a n*m table, same as &irq_handler_list_low_tab. However,
269
+	 * handlers in this table are not deferred and are called immediately.
270
+	 */
107271 	struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER];
108272 
273
+	/**
274
+	 * @pflip_params:
275
+	 *
276
+	 * Page flip IRQ parameters, passed to registered handlers when
277
+	 * triggered.
278
+	 */
109279 	struct common_irq_params
110280 	pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1];
111281 
282
+	/**
283
+	 * @vblank_params:
284
+	 *
285
+	 * Vertical blanking IRQ parameters, passed to registered handlers when
286
+	 * triggered.
287
+	 */
112288 	struct common_irq_params
113289 	vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1];
114290 
115
-	/* this spin lock synchronizes access to 'irq_handler_list_table' */
291
+	/**
292
+	 * @vupdate_params:
293
+	 *
294
+	 * Vertical update IRQ parameters, passed to registered handlers when
295
+	 * triggered.
296
+	 */
297
+	struct common_irq_params
298
+	vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1];
299
+
116300 	spinlock_t irq_handler_list_table_lock;
117301 
118302 	struct backlight_device *backlight_dev;
119303 
120304 	const struct dc_link *backlight_link;
121
-
122
-	struct work_struct mst_hotplug_work;
305
+	struct amdgpu_dm_backlight_caps backlight_caps;
123306 
124307 	struct mod_freesync *freesync_module;
308
+#ifdef CONFIG_DRM_AMD_DC_HDCP
309
+	struct hdcp_workqueue *hdcp_workqueue;
310
+#endif
311
+
312
+	struct drm_atomic_state *cached_state;
313
+	struct dc_state *cached_dc_state;
314
+
315
+	struct dm_compressor_info compressor;
316
+
317
+	const struct firmware *fw_dmcu;
318
+	uint32_t dmcu_fw_version;
319
+	/**
320
+	 * @soc_bounding_box:
321
+	 *
322
+	 * gpu_info FW provided soc bounding box struct or 0 if not
323
+	 * available in FW
324
+	 */
325
+	const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
125326 
126327 	/**
127
-	 * Caches device atomic state for suspend/resume
328
+	 * @mst_encoders:
329
+	 *
330
+	 * fake encoders used for DP MST.
128331 	 */
129
-	struct drm_atomic_state *cached_state;
332
+	struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC];
333
+	bool force_timing_sync;
334
+};
130335 
131
-	struct dm_comressor_info compressor;
336
+enum dsc_clock_force_state {
337
+	DSC_CLK_FORCE_DEFAULT = 0,
338
+	DSC_CLK_FORCE_ENABLE,
339
+	DSC_CLK_FORCE_DISABLE,
340
+};
341
+
342
+struct dsc_preferred_settings {
343
+	enum dsc_clock_force_state dsc_force_enable;
344
+	uint32_t dsc_num_slices_v;
345
+	uint32_t dsc_num_slices_h;
346
+	uint32_t dsc_bits_per_pixel;
132347 };
133348 
134349 struct amdgpu_dm_connector {
....@@ -157,7 +372,7 @@
157372 	struct amdgpu_dm_dp_aux dm_dp_aux;
158373 	struct drm_dp_mst_port *port;
159374 	struct amdgpu_dm_connector *mst_port;
160
-	struct amdgpu_encoder *mst_encoder;
375
+	struct drm_dp_aux *dsc_aux;
161376 
162377 	/* TODO see if we can merge with ddc_bus or make a dm_connector */
163378 	struct amdgpu_i2c_adapter *i2c;
....@@ -167,12 +382,18 @@
167382 	int max_vfreq ;
168383 	int pixel_clock_mhz;
169384 
170
-	/*freesync caps*/
171
-	struct mod_freesync_caps caps;
385
+	/* Audio instance - protected by audio_lock. */
386
+	int audio_inst;
172387 
173388 	struct mutex hpd_lock;
174389 
175390 	bool fake_enable;
391
+#ifdef CONFIG_DEBUG_FS
392
+	uint32_t debugfs_dpcd_address;
393
+	uint32_t debugfs_dpcd_size;
394
+#endif
395
+	bool force_yuv420_output;
396
+	struct dsc_preferred_settings dsc_settings;
176397 };
177398 
178399 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base)
....@@ -187,20 +408,37 @@
187408 struct dm_plane_state {
188409 	struct drm_plane_state base;
189410 	struct dc_plane_state *dc_state;
411
+	uint64_t tiling_flags;
412
+	bool tmz_surface;
190413 };
191414 
192415 struct dm_crtc_state {
193416 	struct drm_crtc_state base;
194417 	struct dc_stream_state *stream;
195418 
419
+	bool cm_has_degamma;
420
+	bool cm_is_degamma_srgb;
421
+
422
+	int update_type;
423
+	int active_planes;
424
+
196425 	int crc_skip_count;
197
-	bool crc_enabled;
426
+	enum amdgpu_dm_pipe_crc_source crc_src;
427
+
428
+	bool freesync_timing_changed;
429
+	bool freesync_vrr_info_changed;
430
+
431
+	bool vrr_supported;
432
+	struct mod_freesync_config freesync_config;
433
+	struct dc_info_packet vrr_infopacket;
434
+
435
+	int abm_level;
198436 };
199437 
200
-#define to_dm_crtc_state(x)    container_of(x, struct dm_crtc_state, base)
438
+#define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
201439 
202440 struct dm_atomic_state {
203
-	struct drm_atomic_state base;
441
+	struct drm_private_state base;
204442 
205443 	struct dc_state *context;
206444 };
....@@ -213,10 +451,11 @@
213451 	enum amdgpu_rmx_type scaling;
214452 	uint8_t underscan_vborder;
215453 	uint8_t underscan_hborder;
216
-	uint8_t max_bpc;
217454 	bool underscan_enable;
218
-	struct mod_freesync_user_enable user_enable;
219455 	bool freesync_capable;
456
+	uint8_t abm_level;
457
+	int vcpi_slots;
458
+	uint64_t pbn;
220459 };
221460 
222461 #define to_dm_connector_state(x)\
....@@ -249,30 +488,23 @@
249488 void dm_restore_drm_connector_state(struct drm_device *dev,
250489 				    struct drm_connector *connector);
251490 
252
-void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector,
253
-					   struct edid *edid);
491
+void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
492
+					struct edid *edid);
254493 
255
-void
256
-amdgpu_dm_remove_sink_from_freesync_module(struct drm_connector *connector);
257
-
258
-/* amdgpu_dm_crc.c */
259
-#ifdef CONFIG_DEBUG_FS
260
-int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name);
261
-void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc);
262
-#else
263
-#define amdgpu_dm_crtc_set_crc_source NULL
264
-#define amdgpu_dm_crtc_handle_crc_irq(x)
265
-#endif
494
+void amdgpu_dm_trigger_timing_sync(struct drm_device *dev);
266495 
267496 #define MAX_COLOR_LUT_ENTRIES 4096
268497 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */
269498 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256
270499 
271500 void amdgpu_dm_init_color_mod(void);
272
-int amdgpu_dm_set_degamma_lut(struct drm_crtc_state *crtc_state,
273
-			      struct dc_plane_state *dc_plane_state);
274
-void amdgpu_dm_set_ctm(struct dm_crtc_state *crtc);
275
-int amdgpu_dm_set_regamma_lut(struct dm_crtc_state *crtc);
501
+int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state);
502
+int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc);
503
+int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
504
+				      struct dc_plane_state *dc_plane_state);
505
+
506
+void amdgpu_dm_update_connector_after_detect(
507
+		struct amdgpu_dm_connector *aconnector);
276508 
277509 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;
278510