forked from ~ljy/RK356X_SDK_RELEASE

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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/gpio/gpio-hlwd.c
....@@ -48,13 +48,166 @@
4848 
4949 struct hlwd_gpio {
5050 	struct gpio_chip gpioc;
51
+	struct irq_chip irqc;
5152 	void __iomem *regs;
53
+	int irq;
54
+	u32 edge_emulation;
55
+	u32 rising_edge, falling_edge;
5256 };
57
+
58
+static void hlwd_gpio_irqhandler(struct irq_desc *desc)
59
+{
60
+	struct hlwd_gpio *hlwd =
61
+		gpiochip_get_data(irq_desc_get_handler_data(desc));
62
+	struct irq_chip *chip = irq_desc_get_chip(desc);
63
+	unsigned long flags;
64
+	unsigned long pending;
65
+	int hwirq;
66
+	u32 emulated_pending;
67
+
68
+	spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
69
+	pending = ioread32be(hlwd->regs + HW_GPIOB_INTFLAG);
70
+	pending &= ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
71
+
72
+	/* Treat interrupts due to edge trigger emulation separately */
73
+	emulated_pending = hlwd->edge_emulation & pending;
74
+	pending &= ~emulated_pending;
75
+	if (emulated_pending) {
76
+		u32 level, rising, falling;
77
+
78
+		level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
79
+		rising = level & emulated_pending;
80
+		falling = ~level & emulated_pending;
81
+
82
+		/* Invert the levels */
83
+		iowrite32be(level ^ emulated_pending,
84
+			    hlwd->regs + HW_GPIOB_INTLVL);
85
+
86
+		/* Ack all emulated-edge interrupts */
87
+		iowrite32be(emulated_pending, hlwd->regs + HW_GPIOB_INTFLAG);
88
+
89
+		/* Signal interrupts only on the correct edge */
90
+		rising &= hlwd->rising_edge;
91
+		falling &= hlwd->falling_edge;
92
+
93
+		/* Mark emulated interrupts as pending */
94
+		pending |= rising | falling;
95
+	}
96
+	spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
97
+
98
+	chained_irq_enter(chip, desc);
99
+
100
+	for_each_set_bit(hwirq, &pending, 32) {
101
+		int irq = irq_find_mapping(hlwd->gpioc.irq.domain, hwirq);
102
+
103
+		generic_handle_irq(irq);
104
+	}
105
+
106
+	chained_irq_exit(chip, desc);
107
+}
108
+
109
+static void hlwd_gpio_irq_ack(struct irq_data *data)
110
+{
111
+	struct hlwd_gpio *hlwd =
112
+		gpiochip_get_data(irq_data_get_irq_chip_data(data));
113
+
114
+	iowrite32be(BIT(data->hwirq), hlwd->regs + HW_GPIOB_INTFLAG);
115
+}
116
+
117
+static void hlwd_gpio_irq_mask(struct irq_data *data)
118
+{
119
+	struct hlwd_gpio *hlwd =
120
+		gpiochip_get_data(irq_data_get_irq_chip_data(data));
121
+	unsigned long flags;
122
+	u32 mask;
123
+
124
+	spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
125
+	mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
126
+	mask &= ~BIT(data->hwirq);
127
+	iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);
128
+	spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
129
+}
130
+
131
+static void hlwd_gpio_irq_unmask(struct irq_data *data)
132
+{
133
+	struct hlwd_gpio *hlwd =
134
+		gpiochip_get_data(irq_data_get_irq_chip_data(data));
135
+	unsigned long flags;
136
+	u32 mask;
137
+
138
+	spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
139
+	mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
140
+	mask |= BIT(data->hwirq);
141
+	iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);
142
+	spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
143
+}
144
+
145
+static void hlwd_gpio_irq_enable(struct irq_data *data)
146
+{
147
+	hlwd_gpio_irq_ack(data);
148
+	hlwd_gpio_irq_unmask(data);
149
+}
150
+
151
+static void hlwd_gpio_irq_setup_emulation(struct hlwd_gpio *hlwd, int hwirq,
152
+					  unsigned int flow_type)
153
+{
154
+	u32 level, state;
155
+
156
+	/* Set the trigger level to the inactive level */
157
+	level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
158
+	state = ioread32be(hlwd->regs + HW_GPIOB_IN) & BIT(hwirq);
159
+	level &= ~BIT(hwirq);
160
+	level |= state ^ BIT(hwirq);
161
+	iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
162
+
163
+	hlwd->edge_emulation |= BIT(hwirq);
164
+	hlwd->rising_edge &= ~BIT(hwirq);
165
+	hlwd->falling_edge &= ~BIT(hwirq);
166
+	if (flow_type & IRQ_TYPE_EDGE_RISING)
167
+		hlwd->rising_edge |= BIT(hwirq);
168
+	if (flow_type & IRQ_TYPE_EDGE_FALLING)
169
+		hlwd->falling_edge |= BIT(hwirq);
170
+}
171
+
172
+static int hlwd_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
173
+{
174
+	struct hlwd_gpio *hlwd =
175
+		gpiochip_get_data(irq_data_get_irq_chip_data(data));
176
+	unsigned long flags;
177
+	u32 level;
178
+
179
+	spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
180
+
181
+	hlwd->edge_emulation &= ~BIT(data->hwirq);
182
+
183
+	switch (flow_type) {
184
+	case IRQ_TYPE_LEVEL_HIGH:
185
+		level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
186
+		level |= BIT(data->hwirq);
187
+		iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
188
+		break;
189
+	case IRQ_TYPE_LEVEL_LOW:
190
+		level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
191
+		level &= ~BIT(data->hwirq);
192
+		iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
193
+		break;
194
+	case IRQ_TYPE_EDGE_RISING:
195
+	case IRQ_TYPE_EDGE_FALLING:
196
+	case IRQ_TYPE_EDGE_BOTH:
197
+		hlwd_gpio_irq_setup_emulation(hlwd, data->hwirq, flow_type);
198
+		break;
199
+	default:
200
+		spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
201
+		return -EINVAL;
202
+	}
203
+
204
+	spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
205
+	return 0;
206
+}
53207 
54208 static int hlwd_gpio_probe(struct platform_device *pdev)
55209 {
56210 	struct hlwd_gpio *hlwd;
57
-	struct resource *regs_resource;
58211 	u32 ngpios;
59212 	int res;
60213 
....@@ -62,8 +215,7 @@
62215 	if (!hlwd)
63216 		return -ENOMEM;
64217 
65
-	regs_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
66
-	hlwd->regs = devm_ioremap_resource(&pdev->dev, regs_resource);
218
+	hlwd->regs = devm_platform_ioremap_resource(pdev, 0);
67219 	if (IS_ERR(hlwd->regs))
68220 		return PTR_ERR(hlwd->regs);
69221 
....@@ -92,6 +244,44 @@
92244 		ngpios = 32;
93245 	hlwd->gpioc.ngpio = ngpios;
94246 
247
+	/* Mask and ack all interrupts */
248
+	iowrite32be(0, hlwd->regs + HW_GPIOB_INTMASK);
249
+	iowrite32be(0xffffffff, hlwd->regs + HW_GPIOB_INTFLAG);
250
+
251
+	/*
252
+	 * If this GPIO controller is not marked as an interrupt controller in
253
+	 * the DT, skip interrupt support.
254
+	 */
255
+	if (of_property_read_bool(pdev->dev.of_node, "interrupt-controller")) {
256
+		struct gpio_irq_chip *girq;
257
+
258
+		hlwd->irq = platform_get_irq(pdev, 0);
259
+		if (hlwd->irq < 0) {
260
+			dev_info(&pdev->dev, "platform_get_irq returned %d\n",
261
+				 hlwd->irq);
262
+			return hlwd->irq;
263
+		}
264
+
265
+		hlwd->irqc.name = dev_name(&pdev->dev);
266
+		hlwd->irqc.irq_mask = hlwd_gpio_irq_mask;
267
+		hlwd->irqc.irq_unmask = hlwd_gpio_irq_unmask;
268
+		hlwd->irqc.irq_enable = hlwd_gpio_irq_enable;
269
+		hlwd->irqc.irq_set_type = hlwd_gpio_irq_set_type;
270
+
271
+		girq = &hlwd->gpioc.irq;
272
+		girq->chip = &hlwd->irqc;
273
+		girq->parent_handler = hlwd_gpio_irqhandler;
274
+		girq->num_parents = 1;
275
+		girq->parents = devm_kcalloc(&pdev->dev, 1,
276
+					     sizeof(*girq->parents),
277
+					     GFP_KERNEL);
278
+		if (!girq->parents)
279
+			return -ENOMEM;
280
+		girq->parents[0] = hlwd->irq;
281
+		girq->default_type = IRQ_TYPE_NONE;
282
+		girq->handler = handle_level_irq;
283
+	}
284
+
95285 	return devm_gpiochip_add_data(&pdev->dev, &hlwd->gpioc, hlwd);
96286 }
97287