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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/gpio/gpio-104-idi-48.c
....@@ -1,15 +1,7 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * GPIO driver for the ACCES 104-IDI-48 family
34  * Copyright (C) 2015 William Breathitt Gray
4
- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License, version 2, as
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- * published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful, but
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- * WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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- * General Public License for more details.
135  *
146  * This driver supports the following ACCES devices: 104-IDI-48A,
157  * 104-IDI-48AC, 104-IDI-48B, and 104-IDI-48BC.
....@@ -61,7 +53,7 @@
6153 
6254 static int idi_48_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
6355 {
64
-	return 1;
56
+	return GPIO_LINE_DIRECTION_IN;
6557 }
6658 
6759 static int idi_48_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
....@@ -73,7 +65,7 @@
7365 {
7466 	struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
7567 	unsigned i;
76
-	const unsigned register_offset[6] = { 0, 1, 2, 4, 5, 6 };
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+	static const unsigned int register_offset[6] = { 0, 1, 2, 4, 5, 6 };
7769 	unsigned base_offset;
7870 	unsigned mask;
7971 
....@@ -93,42 +85,20 @@
9385 	unsigned long *bits)
9486 {
9587 	struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
96
-	size_t i;
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+	unsigned long offset;
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+	unsigned long gpio_mask;
9790 	static const size_t ports[] = { 0, 1, 2, 4, 5, 6 };
98
-	const unsigned int gpio_reg_size = 8;
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-	unsigned int bits_offset;
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-	size_t word_index;
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-	unsigned int word_offset;
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-	unsigned long word_mask;
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-	const unsigned long port_mask = GENMASK(gpio_reg_size - 1, 0);
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+	unsigned int port_addr;
10492 	unsigned long port_state;
10593 
10694 	/* clear bits array to a clean slate */
10795 	bitmap_zero(bits, chip->ngpio);
10896 
109
-	/* get bits are evaluated a gpio port register at a time */
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-	for (i = 0; i < ARRAY_SIZE(ports); i++) {
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-		/* gpio offset in bits array */
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-		bits_offset = i * gpio_reg_size;
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+	for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
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+		port_addr = idi48gpio->base + ports[offset / 8];
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+		port_state = inb(port_addr) & gpio_mask;
113100 
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-		/* word index for bits array */
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-		word_index = BIT_WORD(bits_offset);
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-
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-		/* gpio offset within current word of bits array */
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-		word_offset = bits_offset % BITS_PER_LONG;
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-
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-		/* mask of get bits for current gpio within current word */
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-		word_mask = mask[word_index] & (port_mask << word_offset);
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-		if (!word_mask) {
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-			/* no get bits in this port so skip to next one */
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-			continue;
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-		}
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-
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-		/* read bits from current gpio port */
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-		port_state = inb(idi48gpio->base + ports[i]);
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-
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-		/* store acquired bits at respective bits array offset */
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-		bits[word_index] |= port_state << word_offset;
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+		bitmap_set_value8(bits, port_state, offset);
132102 	}
133103 
134104 	return 0;
....@@ -277,10 +247,22 @@
277247 	"Bit 18 B", "Bit 19 B", "Bit 20 B", "Bit 21 B", "Bit 22 B", "Bit 23 B"
278248 };
279249 
250
+static int idi_48_irq_init_hw(struct gpio_chip *gc)
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+{
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+	struct idi_48_gpio *const idi48gpio = gpiochip_get_data(gc);
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+
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+	/* Disable IRQ by default */
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+	outb(0, idi48gpio->base + 7);
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+	inb(idi48gpio->base + 7);
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+
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+	return 0;
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+}
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+
280261 static int idi_48_probe(struct device *dev, unsigned int id)
281262 {
282263 	struct idi_48_gpio *idi48gpio;
283264 	const char *const name = dev_name(dev);
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+	struct gpio_irq_chip *girq;
284266 	int err;
285267 
286268 	idi48gpio = devm_kzalloc(dev, sizeof(*idi48gpio), GFP_KERNEL);
....@@ -305,23 +287,22 @@
305287 	idi48gpio->chip.get_multiple = idi_48_gpio_get_multiple;
306288 	idi48gpio->base = base[id];
307289 
290
+	girq = &idi48gpio->chip.irq;
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+	girq->chip = &idi_48_irqchip;
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+	/* This will let us handle the parent IRQ in the driver */
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+	girq->parent_handler = NULL;
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+	girq->num_parents = 0;
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+	girq->parents = NULL;
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+	girq->default_type = IRQ_TYPE_NONE;
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+	girq->handler = handle_edge_irq;
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+	girq->init_hw = idi_48_irq_init_hw;
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+
308300 	raw_spin_lock_init(&idi48gpio->lock);
309301 	spin_lock_init(&idi48gpio->ack_lock);
310302 
311303 	err = devm_gpiochip_add_data(dev, &idi48gpio->chip, idi48gpio);
312304 	if (err) {
313305 		dev_err(dev, "GPIO registering failed (%d)\n", err);
314
-		return err;
315
-	}
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-
317
-	/* Disable IRQ by default */
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-	outb(0, base[id] + 7);
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-	inb(base[id] + 7);
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-
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-	err = gpiochip_irqchip_add(&idi48gpio->chip, &idi_48_irqchip, 0,
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-		handle_edge_irq, IRQ_TYPE_NONE);
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-	if (err) {
324
-		dev_err(dev, "Could not add irqchip (%d)\n", err);
325306 		return err;
326307 	}
327308